Cypress CY62147DV18L-70BVI 4-mb (256k x 16) static ram Datasheet

CY62147DV18
MoBL2™
4-Mb (256K x 16) Static RAM
Features
•
•
•
•
•
•
•
•
•
mode reducing power consumption by more than 99% when
deselected (CE HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Very high speed: 55 ns and 70 ns
Wide voltage range: 1.65V – 2.25V
Pin-compatible with CY62147CV18
Ultra-low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 6 mA @ f = fmax
Ultra low standby power
Easy memory expansion with CE, and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered 48-ball BGA
Functional Description[1]
The CY62147DV18 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
Writing to the device is accomplished by asserting Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/O7), is written into the location specified on the address pins
(A0 through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by asserting Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table for a complete description of read and write
modes.
The CY62147DV18 is available in a 48-ball FBGA package.
Logic Block Diagram
SENSE AMPS
ROW DECODER
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
256K x 16
RAM Array
I/O0 – I/O7
I/O8 – I/O15
BHE
WE
CE
OE
BLE
A17
A13
A14
A15
A16
A11
A12
COLUMN DECODER
Power -Down
Circuit
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05343 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 26, 2004
CY62147DV18
MoBL2™
Pin Configuration[2, 3, 4]
FBGA (Top View)
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
Vcc
D
VCC
I/O12 DNU
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Notes:
2. NC pins are not internally connected on the die.
3. DNU pins have to be left floating or tied to Vss to ensure proper application.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
Document #: 38-05343 Rev. *B
Page 2 of 11
CY62147DV18
MoBL2™
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied............................................ –55°C to + 125°C
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Supply Voltage to Ground
Potential ......................................–0.2V to + VCC(MAX) + 0.2V
DC Voltage Applied to Outputs
in High Z State[5,6] ..........................–0.2V to VCC(MAX) + 0.2V
DC Input Voltage[5,6] .....................–0.2V to VCC (MAX) + 0.2V
Device
Range
Ambient
Temperature
(TA)
VCC[7]
CY62147DV18L Industrial –40°C to +85°C 1.65V to 2.25V
CY62147DV18LL
Product Portfolio
Power Dissipation
Operating ICC (mA)
VCC Range (V)
Product
CY62147DV18L
f = 1MHz
f = fmax
Typ.[7]
Max.
Speed
(ns)
Typ.[7]
Max.
Typ.[7]
Max.
Typ.[7]
Max.
1.65
1.8
2.25
55
1.0
2.0
6
15
0.5
18
CY62147DV18LL
CY62147DV18L
Standby ISB2 (µA)
Min.
10
1.65
1.8
2.25
70
1.0
2.0
6
CY62147DV18LL
12
15
0.5
18
10
12
Electrical Characteristics Over the Operating Range
CY62147DV18-55
Parameter
Description
Test Conditions
Min.
Typ.[7]
Max.
VOH
Output HIGH
Voltage
IOH = –0.1 mA
VCC = 1.65V
VOL
Output LOW
Voltage
IOL = 0.1 mA
VCC = 1.65V
VIH
Input HIGH
Voltage
VCC =1.65V to 2.25V
1.4
VIL
Input LOW
Voltage
VCC =1.65V to 2.25V
–0.2
0.4
IIX
Input Leakage
Current
GND < VI < VCC
–1
IOZ
Output Leakage GND < VO < VCC, Output Disabled
Current
–1
ICC
VCC Operating f = fMAX = 1/tRC
Supply Current
f = 1 MHz
1.4
CY62147DV18-70
Min. Typ.[7]
Max.
1.4
Unit
V
0.2
0.2
V
VCC + 0.2V
V
–0.2
0.4
V
+1
–1
+1
µA
+1
–1
+1
µA
12
mA
VCC + 0.2V 1.4
VCC(max) = 1.95V L
IOUT = 0 mA
LL
CMOS levels
6
12
6
VCC(max) = 2.25V L
IOUT = 0 mA
LL
CMOS levels
6
VCC(max) = 1.95V L
1
1.5
1
1.5
mA
1
2
1
2
mA
8
15
8
6
10
15
mA
10
LL
VCC(max) = 2.25V L
LL
Notes:
5. VIL(min.) = –2.0V for pulse durations less than 20 ns.
6. VIH(max)=VCC+0.75V for pulse durations less than 20ns.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05343 Rev. *B
Page 3 of 11
CY62147DV18
MoBL2™
Electrical Characteristics Over the Operating Range (continued)
CY62147DV18-55
Parameter
ISB1
Description
Automatic CE
Power-Down
Current —
CMOS Inputs
ISB2
Min. Typ.[7]
Test Conditions
Automatic CE
Power-down
Current —
CMOS Inputs
CE > VCC−0.2V,
VCC(max)=1.95V
VIN>VCC–0.2V,
VIN<0.2V); f = fMAX
(Address and Data VCC(max)=2.25V
Only), f = 0 (OE,
WE, BHE and BLE)
L
CE > VCC – 0.2V, VCC(max)=1.95V
VIN > VCC – 0.2V or
VIN < 0.2V, f = 0
VCC(max)=2.25V
L
0.5
LL
Max.
CY62147DV18-70
Min. Typ.[7]
12
Max.
Unit
12
µA
0.5
8
L
0.5
LL
8
18
0.5
18
12
0.5
LL
12
12
0.5
L
0.5
LL
µA
12
8
8
18
0.5
18
12
12
Capacitance for all Packages[8]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
10
pF
10
pF
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Thermal Resistance
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)[8]
ΘJC
Thermal Resistance
(Junction to Case)[8]
Test Conditions
BGA
Unit
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
75
°C/W
10
°C/W
AC Test Loads and Waveforms
R1
VCC
OUTPUT
30 pF
VCC
R2
10%
GND
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
1.80V
Unit
R1
13500
Ω
R2
10800
Ω
RTH
6000
Ω
VTH
0.80
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[8]
Chip Deselect to Data Retention Time
tR
Operation Recovery Time
Conditions
Min.
Typ.[7]
Max.
Unit
6
µA
1.0
VCC= 1.0V CE > VCC – 0.2V,
L
VIN > VCC – 0.2V or VIN < 0.2V LL
V
4
0
ns
tRC
ns
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05343 Rev. *B
Page 4 of 11
CY62147DV18
MoBL2™
Data Retention Waveform[9]
wqewqewq
DATA RETENTION MODE
VCC(min)
VCC
VDR > 1.0 V
VCC(min)
tR
tCDR
CE or
BHE.BLE
Switching Characteristics Over the Operating Range [10.]
55 ns
Parameter
Description
Min.
70 ns
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
55
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
55
Z[11]
tLZOE
OE LOW to LOW
tHZOE
OE HIGH to High Z[11, 12]
CE LOW to Low
tHZCE
CE HIGH to High Z[11, 12]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
tDBE
BLE / BHE LOW to Data Valid
tLZBE
BLE / BHE LOW to Low Z[11]
70
ns
16
10
20
0
0
55
10
ns
ns
70
ns
70
ns
10
20
ns
ns
25
55
ns
ns
5
10
Z[11, 12]
ns
10
16
Z[11]
BLE / BHE HIGH to HIGH
10
5
tLZCE
tHZBE
70
ns
25
ns
Write Cycle[13]
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
40
50
ns
tAW
Address Set-up to Write End
40
50
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
45
ns
tBW
BLE / BHE LOW to Write End
40
50
ns
tSD
Data Set-Up to Write End
25
30
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High-Z[11, 12]
tLZWE
[11]
WE HIGH to Low-Z
0
20
10
ns
25
10
ns
ns
Notes:
9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signal or by disabling both BHE and BLE.
10. Test conditions for all parameters other than three-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
13. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05343 Rev. *B
Page 5 of 11
CY62147DV18
MoBL2™
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[14, 15]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
Read Cycle No. 2 (OE Controlled)
DATA VALID
[15, 16]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
BHE/BLE
tLZOE
tHZBE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes:
14. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
Document #: 38-05343 Rev. *B
Page 6 of 11
CY62147DV18
MoBL2™
Switching Waveforms (continued)
[13, 17, 18]
Write Cycle No. 1 (WE Controlled)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tSD
DATA I/O
NOTE 19
tHD
DATAIN
tHZOE
Write Cycle No. 2 (CE Controlled)
[13, 17, 18]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 19
tHZOE
Notes:
17. Data I/O is high impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.
19. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05343 Rev. *B
Page 7 of 11
CY62147DV18
MoBL2™
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[18]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATAI/O
NOTE 19
tHD
DATAIN
tLZWE
tHZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
[18]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 19
tSD
tHD
DATAIN
tLZWE
Document #: 38-05343 Rev. *B
Page 8 of 11
CY62147DV18
MoBL2™
Truth Table
CE
WE
OE
BHE
BLE
Inputs/Outputs
Mode
Power
H
X
X
X
X
High Z
Deselect/Power-Down
Standby (ISB)
X
X
X
H
H
High Z
Deselect/Power-Down
Standby (ISB)
L
H
L
L
L
Data Out (I/OO–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read (Lower byte only)
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read (Higher byte only)
Active (ICC)
L
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (I/OO–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Write (Lower byte only)
Active (ICC)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write (Higher byte only)
Active (ICC)
Ordering Information
Speed
(ns)
55
Ordering Code
CY62147DV18L-55BVI
Package
Name
Package Type
Operating
Range
BV48A
48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm)
Industrial
BV48A
48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm)
Industrial
BV48A
48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Pb-free
Industrial
BV48A
48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Pb-free
Industrial
CY62147DV18LL-55BVI
70
CY62147DV18L-70BVI
CY62147DV18LL-70BVI
55
CY62147DV18L-55BVXI
CY62147DV18LL-55BVXI
70
CY62147DV18L-70BVXI
CY62147DV18LL-70BVXI
Document #: 38-05343 Rev. *B
Page 9 of 11
CY62147DV18
MoBL2™
Package Diagram
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05343 Rev. *B
Page 10 of 11
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62147DV18
MoBL2™
Document History Page
Document Title:CY62147DV18 MoBL2™ 4-Mb (256K x 16) Static RAM
Document Number: 38-05343
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
127482
06/17/03
HRT
New Data Sheet
*A
131009
11/26/03
CBD
Changed From Advance to Preliminary
*B
229908
See ECN
AJU
Changed From Preliminary to Final
Added 70 ns speed bin
Changed Vcc MAX spec from 2.20V to 2.25V
Modified VIH spec on footnote #6 from VCC (MAX) + 0.5V to VCC (MAX) + 0.75V
Changed ICC TYP values from 8 mA to 6 mA
Changed ICC MAX values at Vcc (max) = 1.95V from 15 mA to 12 mA (L bin)
and 10 mA to 8mA (LL bin)
Changed ICC MAX values at Vcc (max) = 2.25V from 18 mA to 15 mA (L bin)
and 12mA to 10 mA (LL bin)
With modified Vcc MAX spec, changed ISB1 and ISB2 MAX values from 15 uA
to 18 uA (L bin) and 10 uA to 12 uA (LL bin)
Modified input and output capacitance values
Removed footnote #9 from earlier rev
Removed MAX value for VDR
Modified tHZOE from 20 ns to 16 ns
Added Pb-free ordering information
Document #: 38-05343 Rev. *B
Page 11 of 11
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