TI1 CY74FCT16501T 18-bit registered transceiver Datasheet

1CY74FCT162H501
T
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
SCCS057B - August 1994 - Revised September 2001
18-Bit Registered Transceivers
Features
Functional Description
• Ioff supports partial-power-down mode operation
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6 mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40˚C to +85˚C
• VCC = 5V ± 10%
CY74FCT16501T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25˚C
These 18-bit universal bus transceivers can be operated in
transparent, latched or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For
A-to-B data flow, the device operates in transparent mode
when LEAB is HIGH. When LEAB is LOW, the A data is latched
if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW,
the A bus data is stored in the latch/flip-flop on the
LOW-to-HIGH transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and CLKBA.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device
when it is powered down.
CY74FCT162501T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
The CY74FCT16501T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
CY74FCT162H501T Features:
• Bus hold retains last active state
• Eliminates the need for external pull-up or pull-down
resistors
THE CY74FCT162501T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for minimal
undershoot
and
reduced
ground
bounce.
The
CY74FCT162501T is ideal for driving transmission lines.
The CY74FCT162H501T is a 24-mA balanced output part, that
has “bus hold” on the data inputs. The device retains the input’s
last state whenever the input goes to high impedance. This
eliminates the need for pull-up/down resistors and prevents
floating inputs.
Pin Configuration
Functional Block Diagram
SSOP/TSSOP
Top View
OEAB
LEAB
A1
GND
A2
OEAB
A3
CLKBA
VCC
A4
A5
A6
LEBA
OEBA
CLKAB
LEAB
A1
C
C
D
D
B1
C
C
D
D
TO 17 OTHER CHANNELS
GND
A7
A8
A9
A 10
A 11
A 12
GND
A 13
A 14
A 15
VCC
FCT16501-1
A 16
A 17
GND
A 18
OEBA
LEBA
1
2
56
55
3
4
54
53
5
6
7
52
51
50
8
9
49
48
10
11
12
13
14
15
16
17
18
19
20
21
22
23
47
46
45
44
43
42
41
40
39
38
37
36
35
34
24
25
26
27
28
33
32
31
30
29
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
FCT16501-2
Copyright
© 2001, Texas Instruments Incorporated
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Maximum Ratings[6, 7]
Pin Description
Name
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Description
OEAB
A-to-B Output Enable Input
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
DC Input Voltage................................................. −0.5V to +7.0V
CLKAB
A-to-B Clock Input
DC Output Voltage.............................................. −0.5V to +7.0V
CLKBA
B-to-A Clock Input
A
A-to-B Data Inputs or B-to-A Three-State
Outputs[1]
DC Output Current
(Maximum Sink Current/Pin)........................... −60 to +120 mA
B
B-to-A Data Inputs or A-to-B Three-State
Outputs[1]
Storage Temperature .................................... −55°C to +125°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Power Dissipation.......................................................... 1.0W
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Operating Range
Function Table[2, 3]
Inputs
Range
Outputs
OEAB
LEAB
CLKAB
A
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
L
L
H
L
H
H
H
L
L
X
B[4]
H
L
H
X
B[5]
Industrial
Ambient
Temperature
VCC
−40°C to +85°C
5V ± 10%
Notes:
1. On the 74FCT162H501T these pins have bus hold.
2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-impedance
= LOW-to-HIGH Transition
4. Output level before the indicated steady-state input conditions were established.
5. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
6. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
7. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
2
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Electrical Characteristics Over the Operating Range
Parameter
Description
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Test Conditions
Min.
Input Hysteresis
VIK
Input Clamp Diode Voltage
IIH
Input HIGH Current
100
−0.7
VCC=Min., IIN=−18 mA
Standard
Input LOW Current
Standard
VCC=Max., VI=VCC
V
mV
−1.2
V
±1
µA
±100
VCC=Max., VI=GND
Bus Hold
[10]
Unit
V
0.8
Bus Hold
IIL
Max.
2.0
[9]
VH
Typ.[8]
VCC=Min.,
±1
µA
±100
µA
VI=2.0V
−50
µA
VI=0.8V
+50
µA
IBBH
IBBL
Bus Hold Sustain Current on Bus Hold Input
IBHHO
IBHLO
Bus Hold Overdrive Current on Bus Hold Input[10]
VCC=Max., VI=1.5V
IOZH
High Impedance Output Current
(Three-State Output pins)
IOZL
IOS
TBD
mA
VCC=Max., VOUT=2.7V
±1
µA
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=0.5V
±1
µA
Short Circuit Current[11]
VCC=Max., VOUT=GND
−80
−200
mA
Current[11]
VCC=Max., VOUT=2.5V
−50
−180
mA
±1
µA
Max.
Unit
IO
Output Drive
IOFF
Power-Off Disable
−140
VCC=0V, VOUT≤4.5V[12]
Output Drive Characteristics for CY74FCT16501T
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Min.
Typ.[8]
VCC=Min., IOH=−3 mA
2.5
3.5
VCC=Min., IOH=−15 mA
2.4
3.5
VCC=Min., IOH=−32 mA
2.0
3.0
Test Conditions
VCC=Min., IOL=64 mA
V
0.2
0.55
V
Min.
Typ.[8]
Max.
Unit
Output Drive Characteristics for CY74FCT162501T, CY74FCT162H501T
Parameter
Description
Test Conditions
Output LOW
Current[11]
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
60
115
150
mA
IODH
Output HIGH
Current[11]
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
−60
−115
−150
mA
VOH
Output HIGH Voltage
VCC=Min., IOH=−24 mA
2.4
3.3
VOL
Output LOW Voltage
VCC=Min., IOL=24 mA
IODL
0.3
V
0.55
V
Notes:
8. Typical values are at VCC= 5.0V, TA= +25˚C ambient.
9. This parameter is specified but not tested.
10. Pins with bus hold are described in Pin Description.
11. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
12. Tested at +25˚C.
3
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Capacitance[9] (TA = +25˚C, f = 1.0 MHz)
Parameter
Description
Test Conditions
Typ.[8]
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6.0
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8.0
pF
Power Supply Characteristics
Sym.
Test Conditions[13]
Parameter
VIN<0.2V
VIN>VCC−0.2V
Min.
Typ.[8]
Max.
Unit
—
5
500
µA
—
0.5
1.5
mA
ICC
Quiescent Power Supply
Current
VCC=Max.
∆ICC
Quiescent Power Supply
Current TTL inputs HIGH
VCC= Max., VIN = 3.4V[14]
ICCD
Dynamic Power Supply
Current[15]
VCC=Max., Outputs Open
OEAB=OEBA=VCC or GND
One Input Toggling,
50% Duty Cycle
VIN=VCC or
VIN=GND
—
75
120
µA/
MHz
IC
Total Power Supply
Current[16]
VCC=Max., Outputs Open
f0 =10MHz (CLKAB)
50% Duty Cycle
OEAB=OEBA=VCC
LEAB = GND, One Bit Toggling
f1 = 5MHz, 50% Duty Cycle
VIN=VCC or
VIN=GND
—
0.8
1.7
mA
VIN=3.4V or
VIN=GND
—
1.3
3.2
VIN=VCC or
VIN=GND
—
3.8
6.5[17]
VIN=3.4V or
VIN=GND
—
8.5
20.8[17]
VCC=Max., Outputs Open
f0 = 10MHz (CLKAB)
50% Duty Cycle
OEAB=OEBA=VCC
LEAB=GND
Eighteen Bits Toggling
f1=2.5MHz, 50% Duty Cycle
Notes:
13. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
14. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
15. This parameter is not directly testable, but is derived for use in Total Power Supply.
16. IC= IQUIESCENT + IINPUTS + IDYNAMIC
IC
= ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
= Duty Cycle for TTL inputs HIGH
DH
= Number of TTL inputs at DH
NT
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
f0
= Input signal frequency
f1
= Number of inputs changing at f1
N1
All currents are in milliamps and all frequencies are in megahertz.
17. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
4
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Switching Characteristics Over the Operating Range[18]
CY74FCT16501AT
CY74FCT162501AT
Parameter
Description
CY74FCT162501CT
CY74FCT162H501CT
Min.
Max.
Min.
Max.
Unit
Fig.
No.[19]
fMAX
CLKAB or CLKBA
frequency[20]
—
150
—
150
MHz
—
tPLH
tPHL
Propagation Delay
A to B or B to A
1.5
5.1
1.5
4.6
ns
1,3
tPLH
tPHL
Propagation Delay
LEBA to A, LEAB to B
1.5
5.6
1.5
5.3
ns
1,5
tPLH
tPHL
Propagation Delay
CLKBA to A,
CLKAB to B
1.5
5.6
1.5
5.3
ns
1,5
tPZH
tPZL
Output Enable Time
OEBA to A, OEAB to B
1.5
6.0
1.5
5.6
ns
1,7,8
tPHZ
tPLZ
Output Disable Time
OEBA to A, OEAB to B
1.5
5.6
1.5
5.2
ns
1,7,8
tSU
Set-Up Time, HIGH or LOW
A to CLKAB,
B to CLKBA
3.0
—
3.0
—
ns
4
tH
Hold Time HIGH or LOW
A to CLKAB,
B to CLKBA
0
—
0
—
ns
4
tSU
Set-Up Time, HIGH or LOW
A to LEAB,
B to LEBA
Clock LOW
3.0
—
3.0
—
ns
4
Clock HIGH
1.5
—
1.5
—
ns
4
tH
Hold Time, HIGH or LOW, A to LEAB,
B to LEBA
1.5
—
1.5
—
ns
4
tW
LEAB or LEBA Pulse Width HIGH[20]
3.0
—
3.0
—
ns
5
tW
CLKAB or CLKBA Pulse Width HIGH or
LOW[20]
3.0
—
3.0
—
ns
5
tSK(O)
Output Skew[21]
—
0.5
—
0.5
ns
—
Notes:
18. Minimum limits are specified, but not tested, on propagation delays.
19. See “Parameter Measurement Information” in the General Information section.
20. This parameter is guaranteed but not tested.
21. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.
5
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Ordering Information CY74FCT16501T
Speed
(ns)
5.1
Ordering Code
Package
Name
CY74FCT16501ATPVC/PVCT
O56
Package Type
56-Lead (300-Mil) SSOP
Operating
Range
Industrial
Ordering Information CY74FCT162501T
Speed
(ns)
4.6
5.1
Ordering Code
Package
Name
Package Type
74FCT162501CTPACT
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162501CTPVC
O56
56-Lead (300-Mil) SSOP
74FCT162501CTPVCT
O56
56-Lead (300-Mil) SSOP
74FCT162501ATPACT
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162501ATPVC
O56
56-Lead (300-Mil) SSOP
74FCT162501ATPVCT
O56
56-Lead (300-Mil) SSOP
Operating
Range
Industrial
Industrial
Ordering Information CY74FCT162H501T
Speed
(ns)
4.6
Ordering Code
Package
Name
Package Type
74FCT162H501CTPACT
Z56
56-Lead (240-Mil) TSSOP
74FCT162H501CTPVC/PVCT
O56
56-Lead (300-Mil) SSOP
6
Operating
Range
Industrial
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
7
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74FCT162501ATPVCT
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74FCT162501CTPACT
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74FCT162501CTPVCT
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74FCT162501ETPACT
OBSOLETE
TSSOP
DGG
56
TBD
Call TI
Call TI
74FCT162501ETPVCT
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
74FCT162H501CTPACT
ACTIVE
TSSOP
DGG
56
74FCT162H501CTPVC
ACTIVE
SSOP
DL
56
2000 Green (RoHS &
no Sb/Br)
20
Lead/Ball Finish
MSL Peak Temp (3)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74FCT162H501ETPAC
OBSOLETE
TSSOP
DGG
56
TBD
Call TI
Call TI
74FCT162H501ETPACT
OBSOLETE
TSSOP
DGG
56
TBD
Call TI
Call TI
74FCT162H501ETPVC
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
74FCT162H501ETPVCT
OBSOLETE
SSOP
DL
56
Call TI
74FCT16501ATPVCG4
ACTIVE
SSOP
DL
56
CY74FCT162501ETPAC
OBSOLETE
TSSOP
DGG
56
CY74FCT162501ETPVC
OBSOLETE
SSOP
DL
56
CY74FCT16501ATPVC
ACTIVE
SSOP
DL
56
20
20
TBD
Call TI
Green (RoHS &
no Sb/Br)
CU NIPDAU
TBD
Call TI
Call TI
Call TI
TBD
Call TI
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CY74FCT16501ETPAC
OBSOLETE
TSSOP
DGG
56
TBD
Call TI
Call TI
CY74FCT16501ETPACT
OBSOLETE
TSSOP
DGG
56
TBD
Call TI
Call TI
CY74FCT16501ETPVC
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
CY74FCT16501ETPVCT
OBSOLETE
SSOP
DL
56
Call TI
Call TI
FCT162501ATPVCTG4
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
FCT162501CTPACTE4
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
FCT162501CTPACTG4
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
FCT162501CTPVCTG4
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
FCT162H501CTPACTE4
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
FCT162H501CTPACTG4
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
FCT162H501CTPVCG4
ACTIVE
SSOP
DL
56
CU NIPDAU
Level-1-260C-UNLIM
TBD
20
(1)
Green (RoHS &
no Sb/Br)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
18.67
3.1
16.0
32.0
Q1
74FCT162501ATPVCT
SSOP
DL
56
1000
330.0
32.4
74FCT162501CTPACT
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
74FCT162501CTPVCT
SSOP
DL
56
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
74FCT162H501CTPACT
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
Pack Materials-Page 1
11.35
B0
(mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74FCT162501ATPVCT
SSOP
DL
56
1000
346.0
346.0
49.0
74FCT162501CTPACT
TSSOP
DGG
56
2000
346.0
346.0
41.0
74FCT162501CTPVCT
SSOP
DL
56
1000
346.0
346.0
49.0
74FCT162H501CTPACT
TSSOP
DGG
56
2000
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
74FCT162501ATPVCT
ACTIVE
SSOP
DL
56
74FCT162501CTPACT
OBSOLETE
TSSOP
DGG
56
74FCT162501CTPVCT
ACTIVE
SSOP
DL
56
74FCT162501ETPACT
OBSOLETE
TSSOP
DGG
56
74FCT162501ETPVCT
OBSOLETE
SSOP
DL
56
74FCT162H501CTPACT
ACTIVE
TSSOP
DGG
56
74FCT162H501CTPVC
OBSOLETE
SSOP
DL
74FCT162H501ETPAC
OBSOLETE
TSSOP
DGG
74FCT162H501ETPACT
OBSOLETE
TSSOP
74FCT162H501ETPVC
OBSOLETE
SSOP
74FCT162H501ETPVCT
OBSOLETE
CY74FCT162501ETPAC
CY74FCT162501ETPVC
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TBD
Call TI
Call TI
-40 to 85
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TBD
Call TI
Call TI
-40 to 85
(4/5)
TBD
Call TI
Call TI
-40 to 85
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
56
TBD
Call TI
Call TI
-40 to 85
56
TBD
Call TI
Call TI
-40 to 85
DGG
56
TBD
Call TI
Call TI
-40 to 85
DL
56
TBD
Call TI
Call TI
-40 to 85
SSOP
DL
56
TBD
Call TI
Call TI
-40 to 85
OBSOLETE
TSSOP
DGG
56
TBD
Call TI
Call TI
-40 to 85
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
-40 to 85
CY74FCT16501ATPVC
ACTIVE
SSOP
DL
56
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CY74FCT16501ETPAC
OBSOLETE
TSSOP
DGG
56
TBD
Call TI
Call TI
-40 to 85
CY74FCT16501ETPACT
OBSOLETE
TSSOP
DGG
56
TBD
Call TI
Call TI
-40 to 85
CY74FCT16501ETPVC
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
-40 to 85
CY74FCT16501ETPVCT
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
-40 to 85
FCT162501CTPACTE4
ACTIVE
TSSOP
DGG
56
TBD
Call TI
Call TI
-40 to 85
FCT162501CTPACTG4
ACTIVE
TSSOP
DGG
56
TBD
Call TI
Call TI
-40 to 85
FCT162H501CTPVCG4
ACTIVE
SSOP
DL
56
TBD
Call TI
Call TI
-40 to 85
2000
20
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
Device Marking
FCT162501A
FCT162501C
FCT162H501C
FCT16501A
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
74FCT162501ATPVCT
Package Package Pins
Type Drawing
SSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DL
56
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
74FCT162501CTPVCT
SSOP
DL
56
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
74FCT162H501CTPACT
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74FCT162501ATPVCT
SSOP
DL
56
1000
367.0
367.0
55.0
74FCT162501CTPVCT
SSOP
DL
56
1000
367.0
367.0
55.0
74FCT162H501CTPACT
TSSOP
DGG
56
2000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
SCALE 1.200
SMALL OUTLINE PACKAGE
C
8.3
TYP
7.9
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
6.2
6.0
29
56X
0.27
0.17
0.08
1.2 MAX
C A
B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
29
28
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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