Cypress CY7C1011CV33-15BVI 128k x 16 static ram Datasheet

CY7C1011CV33
128K x 16 Static RAM
Features
• Pin equivalent to CY7C1011BV33
• High speed
— tAA = 10 ns
• Low active power
— 360 mW (max.)
• Data Retention at 2.0
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Easy memory expansion with CE and OE features
• Available in 44-pin TSOP II, 44-pin TQFP, and 48-ball
VFBGA
Functional Description
The CY7C1011CV33 is a high-performance CMOS Static
RAM organized as 131,072 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011CV33 is available in a standard 44-pin TSOP
II package with center power and ground pinout, a 44-pin Thin
Plastic Quad Flatpack (TQFP), as well as a 48-ball fine-pitch
ball grid array (VFBGA) package.
Logic Block Diagram
Pin Configuration
TSOP II
Top View
256K x 16
ARRAY
1024 x 4096
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
I/O0 – I/O7
I/O8 – I/O15
A9
A10
A 11
A 12
A 13
A14
A15
A16
COLUMN
DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document #: 38-05232 Rev. *B
•
3901 North First Street
•
San Jose
•
1
44
2
3
4
43
42
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
CA 95134 • 408-943-2600
Revised October 10, 2002
CY7C1011CV33
Selection Guide
-10
-12
-15
Unit
10
12
15
ns
Comm’l
90
85
80
mA
Ind’l
100
95
90
10
10
10
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current Com’l/Ind’l
mA
Pin Configurations
BLE
BHE
OE
A9
A11
A10
A12
A13
A14
A15
A16
44-pin TQFP
(Top View)
1
CE
I/O15
I/O0
I/O14
I/O1
I/O13
I/O2
I/O12
I/O3
VSS
VCC
VCC
A4
A8
NC
A7
I/O7
A6
I/O8
A5
I/O6
NC
I/O9
A3
I/O5
A2
I/O10
A1
I/O4
WE
A0
VSS
I/O11
48-ball VFBGA
(Top View)
Document #: 38-05232 Rev. *B
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11 NC
A7
I/O3
VCC
D
VCC
I/O12
NC
A16
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Page 2 of 11
CY7C1011CV33
Maximum Ratings
DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Current into Outputs (LOW)......................................... 20 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
3.3V ± 0.3V
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND
[2]
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[2] ....................................–0.5V to VCC + 0.5V
Industrial
–40°C to +85°C
DC Electrical Characteristics Over the Operating Range
-10
Parameter
Description
Test Conditions
Min.
-12
Max.
2.4
VOH
Output HIGH Voltage
VCC = Min.,
IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[1]
IIX
Input Load Current
IOZ
Output Leakage Current GND < VOUT < VCC,
Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max., f = fMAX =
1/tRC
ISB1
Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Min.
-15
Max.
2.4
0.4
Min.
Max.
2.4
0.4
Unit
V
0.4
V
V
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
–1
+1
–1
+1
–1
+1
µA
–1
+1
–1
+1
–1
+1
µA
80
mA
GND < VI < VCC
Com’l
90
Ind’l
100
95
90
mA
40
40
40
mA
10
10
10
mA
Com’l/
Ind’l
85
Capacitance[2]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max.
Unit
8
pF
8
pF
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05232 Rev. *B
Page 3 of 11
CY7C1011CV33
AC Test Loads and Waveforms[3]
12-, 15-ns devices:
10-ns devices:
Z = 50Ω
50 Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R 317Ω
3.3V
OUTPUT
OUTPUT
30 pF*
R2
351Ω
30 pF
1.5V
(b)
(a)
High-Z characteristics:
R 317Ω
3.3V
ALL INPUT PULSES
3.0V
90%
90%
10%
GND
OUTPUT
10%
(c)
Rise Time: 1 V/ns
R2
351Ω
5 pF
Fall Time: 1 V/ns
(d)
AC Switching Characteristics Over the Operating Range [4]
-10
Parameter
Description
Min.
-12
Max.
Min.
-15
Max.
Min.
Max.
Unit
Read Cycle
tpower[5]
VCC(typical) to the first access
1
1
1
µs
tRC
Read Cycle Time
10
12
15
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
10
12
15
ns
tDOE
OE LOW to Data Valid
5
6
7
ns
tLZOE
OE LOW to Low-Z
10
3
tHZOE
OE HIGH to
tLZCE
CE LOW to Low-Z[7]
3
0
High-Z[6, 7]
12
5
High-Z[6, 7]
3
0
3
15
6
ns
7
3
ns
CE HIGH to
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
10
12
15
ns
tDBE
Byte Enable to Data Valid
5
6
7
ns
tLZBE
Byte Enable to Low-Z
Write
tWC
0
0
0
Byte Disable to High-Z
6
ns
tHZCE
tHZBE
5
ns
0
3
ns
0
0
6
7
ns
0
6
ns
ns
7
ns
Cycle[8, 9]
Write Cycle Time
10
12
15
ns
Notes:
3. AC characteristics (except High-Z) for all 10-ns parts are tested using the load conditions shown in (a). All other speeds are tested using the Thevenin load
shown in (b). High-Z characteristics are tested for all speeds using the test load shown in (d).
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05232 Rev. *B
Page 4 of 11
CY7C1011CV33
AC Switching Characteristics Over the Operating Range (continued)[4]
-10
Parameter
Description
Min.
-12
Max.
Min.
-15
Max.
Min.
Max.
Unit
tSCE
CE LOW to Write End
7
8
10
ns
tAW
Address Set-up to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
ns
tSD
Data Set-up to Write End
5
6
7
ns
tHD
Data Hold from Write End
0
0
0
ns
3
3
3
ns
[7]
tLZWE
WE HIGH to Low-Z
High-Z[6, 7]
tHZWE
WE LOW to
tBW
Byte Enable to End of Write
5
7
6
7
8
10
ns
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
VDR > 2V
3.0V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
11. WE is HIGH for read cycle.
Document #: 38-05232 Rev. *B
Page 5 of 11
CY7C1011CV33
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled) [11, 12]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
tHZBE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
IICC
CC
50%
50%
IISB
SB
Write Cycle No. 1 (CE Controlled)[13, 14]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
t BW
BHE, BLE
tSD
tHD
DATAI/O
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high-impedance if OE or BHE and/or BLE = VIH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05232 Rev. *B
Page 6 of 11
CY7C1011CV33
Switching Waveforms (continued)
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
tSA
BHE, BLE
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATAI/O
Write Cycle No. 3 (WE Controlled,
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Document #: 38-05232 Rev. *B
Page 7 of 11
CY7C1011CV33
Truth Table
CE
OE
WE
BLE
BHE
I/O0–I/O7
I/O8–I/O15
Mode
Power
H
X
X
X
X
High-Z
High-Z
Power-down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read All Bits
Active (ICC)
L
L
H
L
H
Data Out
High-Z
Read Lower Bits Only
Active (ICC)
L
L
H
H
L
High-Z
Data Out
Read Upper Bits Only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write All Bits
Active (ICC)
L
X
L
L
H
Data In
High-Z
Write Lower Bits Only
Active (ICC)
L
X
L
H
L
High-Z
Data In
Write Upper Bits Only
Active (ICC)
L
H
H
X
X
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
10
12
15
Ordering Code
CY7C1011CV33-10ZC
CY7C1011CV33-10BVC
CY7C1011CV33-10ZI
CY7C1011CV33-10BVI
CY7C1011CV33-12ZC
CY7C1011CV33-12AC
CY7C1011CV33-12BVC
CY7C1011CV33-12ZI
CY7C1011CV33-12AI
CY7C1011CV33-12BVI
CY7C1011CV33-15ZC
CY7C1011CV33-15AC
CY7C1011CV33-15BVC
CY7C1011CV33-15ZI
CY7C1011CV33-15AI
CY7C1011CV33-15BVI
Document #: 38-05232 Rev. *B
Package
Name
Z44
BV48A
Z44
BV48A
Z44
A44
BV48A
Z44
A44
BV48A
Z44
A44
BV48A
Z44
A44
BV48A
Package Type
44-pin TSOP II
48-ball VFBGA
44-pin TSOP II
48-ball VFBGA
44-pin TSOP II
44-pin TQFP
48-ball VFBGA
44-pin TSOP II
44-pin TQFP
48-ball VFBGA
44-pin TSOP II
44-pin TQFP
48-ball VFBGA
44-pin TSOP II
44-pin TQFP
48-ball VFBGA
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 8 of 11
CY7C1011CV33
Package Diagrams
44-Pin TSOP II Z44
51-85087-*A
44-Lead Thin Plastic Quad Flat Pack A44
51-85064-*B
Document #: 38-05232 Rev. *B
Page 9 of 11
CY7C1011CV33
Package Diagrams (continued)
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05232 Rev. *B
Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1011CV33
Document History Page
Document Title: CY7C1011CV33 128K x 16 Static RAM
Document Number: 38-05232
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
117132
07/31/02
HGK
New Data Sheet
*A
118057
08/19/02
HGK
Pin configuration for 48-ball FBGA correction
*B
119702
10/11/02
DFP
Updated FBGA to VFBGA; updated package code on page 8 to BV48A.
Updated address pinouts on page 1 to A0 to A16. Updated CMOS standby
current on page 1 from 8 to 10 mA.
Document #: 38-05232 Rev. *B
Page 11 of 11
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