CYPRESS CY7C1049BV33-12ZC

049BV33
CY7C1049BV33
512K x 8 Static RAM
Features
• High speed
— tAA = 15 ns
• Low active power
— 504 mW (max.)
• Low CMOS standby power (Commercial L version)
— 1.8 mW (max.)
• 2.0V Data Retention (660 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Functional Description[1]
The CY7C1049BV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O0 through I/O7) is then written into the location specified on
the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049BV33 is available in a standard 400-mil-wide
36-pin SOJ and 44-pin TSOPII packages with center power
and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
Top View
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
I/O0
INPUT BUFFER
CE
I/O1
I/O2
512K x 8
ARRAY
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
I/O3
I/O4
I/O5
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
OE
A 11
A 12
A 13
A14
A15
A16
A17
A18
WE
TSOP II
Top View
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
VSS
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
44
2
3
43
42
4
5
6
41
40
39
7
38
8
9
36
10
11
12
37
35
34
33
13
32
14
15
16
17
18
19
20
21
22
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
Selection Guide
-12
-15
-17
-20
-25
Maximum Access Time (ns)
12
15
17
20
25
Maximum Operating Current (mA) Comm’l
200
180
170
160
150
220
200
180
170
170
8
8
8
8
8
0.5
0.5
0.5
0.5
0.5
Ind’l
Maximum CMOS Standby
Current (mA)
Com’l/Ind’l
Com’l
L
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05139 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 13, 2002
CY7C1049BV33
DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Range
Ambient
Temperature
VCC
Supply Voltage on VCC to Relative GND[2].....–0.5V to +4.6V
Commercial
0°C to +70°C
3.3V ± 0.3V
DC Voltage Applied to Outputs[2]
in High Z State .......................................–0.5V to VCC + 0.5V
Industrial
–40°C to +85°C
DC Electrical Characteristics Over the Operating Range
Parameter
-12
Description
Test Conditions
Min.
-15
Max.
2.4
Min.
-17
Max.
2.4
Max.
2.4
VOH
Output HIGH Voltage
VCC = Min.,
IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
2.2
VCC
+ 0.5
2.2
VCC
+ 0.5
VIL
Input LOW Voltage[2]
–0.5
0.8
–0.5
IIX
Input Load Current
GND < VI < VCC
–1
+1
IOZ
Output Leakage
Current
GND < VOUT < VCC,
Output Disabled
–1
+1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
0.4
Min.
0.4
Unit
V
0.4
V
2.2
VCC
+ 0.5
V
0.8
–0.5
0.8
V
–1
+1
–1
+1
µA
–1
+1
–1
+1
µA
Comm’l
200
180
170
mA
Ind’l
220
200
180
mA
30
30
30
mA
8
8
8
mA
0.5
0.5
0.5
mA
Com’l/Ind’l
Com’l
L
Note:
2. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
Document #: 38-05139 Rev. *A
Page 2 of 10
CY7C1049BV33
DC Electrical Characteristics Over the Operating Range (continued)
-20
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min.,
IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
Min.
-25
Max.
2.4
Min.
Max.
V
0.4
[2]
Unit
2.4
0.4
V
V
2.2
VCC + 0.5
2.2
VCC + 0.5
VIL
Input LOW Voltage
–0.5
0.8
–0.5
0.8
V
IIX
Input Load Current
GND < VI < VCC
–1
+1
–1
+1
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC,
Output Disabled
–1
+1
–1
+1
µA
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Com’l
160
150
mA
Ind’l
170
170
mA
30
30
mA
8
8
mA
0.5
0.5
mA
Com’l/Ind’l
Com’l
L
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
8
pF
8
pF
AC Test Loads and Waveforms
R1 317Ω
3.3V
THÉVENIN EQUIVALENT
167Ω
OUTPUT
OUTPUT
30 pF
R2
351Ω
INCLUDING
JIG AND
SCOPE
(a)
(b)
ALL INPUT PULSES
3.3V
90%
1.73V
GND
RiseTime:1 V/ns
10%
90%
10%
Fall time:
1 V/ns
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05139 Rev. *A
Page 3 of 10
CY7C1049BV33
AC Switching Characteristics[4] Over the Operating Range
-12
Parameter
Description
Min.
-15
Max.
Min.
-17
Max.
Min.
Max.
Unit
Read Cycle
tpower
VCC(typical) to the First Access[5]
1
1
1
µs
tRC
Read Cycle Time
12
15
17
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
12
15
17
ns
tDOE
OE LOW to Data Valid
6
7
8
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[6, 7]
tLZCE
CE LOW to Low
Z[7]
12
3
0
3
CE HIGH to High
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
6
3
0
12
ns
8
7
ns
ns
8
ns
17
ns
0
15
ns
ns
0
7
3
0
17
3
0
6
Z[6, 7]
tHZCE
15
3
ns
Write Cycle[8, 9]
tWC
Write Cycle Time
12
15
17
ns
tSCE
CE LOW to Write End
10
12
13
ns
tAW
Address Set-Up to Write End
10
12
13
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
10
12
13
ns
tSD
Data Set-Up to Write End
7
8
9
ns
tHD
Data Hold from Write End
0
0
0
ns
3
3
3
ns
tLZWE
tHZWE
WE HIGH to Low
Z[7]
WE LOW to High
Z[6, 7]
6
7
8
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. T.power time has to be provided initially before a read/write operation
is started.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05139 Rev. *A
Page 4 of 10
CY7C1049BV33
AC Switching Characteristics[4] Over the Operating Range (continued)
-20
Parameter
Description
Min.
-25
Max.
Min.
Max.
Unit
Read Cycle
tpower
VCC(typical) to the First Access[6]
1
1
µs
tRC
Read Cycle Time
20
25
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[6, 7]
tLZCE
CE LOW to Low
25
ns
20
25
ns
8
10
ns
3
3
0
0
3
Z[6, 7]
tHZCE
CE HIGH to High
CE LOW to Power-Up
ns
ns
8
Z[7]
tPU
tPD
20
10
3
ns
8
0
CE HIGH to Power-Down
ns
10
ns
0
ns
20
25
ns
Cycle[9]
Write
tWC
Write Cycle Time
20
25
ns
tSCE
CE LOW to Write End
13
15
ns
tAW
Address Set-Up to Write End
13
15
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
13
15
ns
tSD
Data Set-Up to Write End
9
10
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low Z[7]
3
3
ns
tHZWE
WE LOW to High
Z[6, 7]
8
10
ns
Data Retention Characteristics Over the Operating Range (For L version only)
Parameter
VDR
VCC for Data Retention
ICCDR
tCDR
Conditions[10]
Description
[3]
tR[11]
Data Retention Current
Chip Deselect to Data Retention
Time
Min.
Max
2.0
VCC = VDR = 2.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
Operation Recovery Time
Unit
V
330
µA
0
ns
tRC
ns
Notes:
10. No input may exceed VCC + 0.5V
11. .tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 ns and slower speeds.
Document #: 38-05139 Rev. *A
Page 5 of 10
CY7C1049BV33
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
3.0V
VDR > 2V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
ICC
50%
ISB
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05139 Rev. *A
Page 6 of 10
CY7C1049BV33
Switching Waveforms (continued)
Write Cycle No. 1(WE Controlled, OE HIGH During Write)[15, 16]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 17
tHZOE
Write Cycle No. 2 (WE Controlled, OE LOW)[16]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
NOTE 17
DATA I/O
tHD
DATA VALID
tLZWE
tHZWE
Truth Table
CE
OE
WE
I/O0 – I/O7
Mode
Power
H
X
X
High Z
Power-Down
Standby (ISB)
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Notes:
15. Data I/O is high-impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05139 Rev. *A
Page 7 of 10
CY7C1049BV33
Ordering Information
Speed
(ns)
12
15
17
20
25
Ordering Code
CY7C1049BV33-12VC
Package
Name
Package Type
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BV33-12ZC
Z44
44-Pin TSOP II Z44
CY7C1049BV33L-12VC
V36
36-Lead (400-Mil) Molded SOJ
Operating
Range
Commercial
CY7C1049BV33-12VI
V36
36-Lead (400-Mil) Molded SOJ
Industrial
CY7C1049BV33-15VC
V36
36-Lead (400-Mil) Molded SOJ
Commercial
CY7C1049BV33L-15VC
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BV33-15ZC
Z44
44-Pin TSOP II Z44
CY7C1049BV33L-15ZC
Z44
44-Pin TSOP II Z44
CY7C1049BV33-15VI
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BV33-15ZI
Z44
44-Pin TSOP II Z44
CY7C1049BV33-17VC
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BV33L-17VC
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BV33-17ZC
Z44
44-Pin TSOP II Z44
CY7C1049BV33L-17ZC
Z44
44-Pin TSOP II Z44
CY7C1049BV33-17VI
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BV33L-17VI
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BV33-17ZI
Z44
44-Pin TSOP II Z44
CY7C1049BV33-20VC
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BV33L-20VC
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BV33-20ZC
Z44
44-Pin TSOP II Z44
CY7C1049BV33L-20ZC
Z44
44-Pin TSOP II Z44
CY7C1049BV33-20VI
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BV33-20ZI
Z44
44-Pin TSOP II Z44
CY7C1049BV33-25VC
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BV33L-25VC
V36
36-Lead (400-Mil) Molded SOJ
CY7C1049BV33-25ZC
Z44
44-Pin TSOP II Z44
CY7C1049BV33L-25ZC
Z44
44-Pin TSOP II Z44
CY7C1049BV33-25VI
v36
36-Lead (400-Mil) Molded SOJ
Document #: 38-05139 Rev. *A
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 8 of 10
CY7C1049BV33
Package Diagrams
36-Lead (400-Mil) Molded SOJ V36
51-85090-*B
44-Pin TSOP II Z44
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05139 Rev. *A
Page 9 of 10
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1049BV33
Document History Page
Document Title: CY7C1049BV33 512K x 8 Static RAM
Document Number: 38-05139
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
113091
02/13/02
DSG
Change from Spec number: 38-00931 to 38-05139
*A
116475
09/16/02
CEA
Add applications foot note to data sheet, page 1
Document #: 38-05139 Rev. *A
Description of Change
Page 10 of 10