CY7C1231F 2-Mbit (128K x 18) Flow-through SRAM with NoBL™ Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation The CY7C1231F is a 3.3V, 128K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1231F is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 7.5 ns (117-MHz device). • Byte Write capability • 128K x 18 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 7.5 ns (for 117-MHz device) Write operations are controlled by the two Byte Write Select (BW[A:B]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. — 8.5 ns (for 100-MHz device) • Clock Enable (CEN) pin to suspend operation Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. • Synchronous self-timed writes • Asynchronous Output Enable • JEDEC-standard 100 TQFP package • Burst Capability—linear or interleaved burst order • Low standby power Logic Block Diagram ADDRESS REGISTER A0, A1, A A1 D1 A0 D0 MODE CLK CEN C CE ADV/LD C BURST LOGIC Q1 A1' A0' Q0 WRITE ADDRESS REGISTER ADV/LD BWA WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWB WRITE DRIVERS MEMORY ARRAY S E N S E A M P S WE OE CE1 CE2 CE3 ZZ INPUT REGISTER D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQPA DQPB E E READ LOGIC SLEEP CONTROL Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05437 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 5, 2004 CY7C1231F Selection Guide CY7C1231F-117 CY7C1231F-100 Unit Maximum Access Time 7.5 8.5 ns Maximum Operating Current 220 205 mA Maximum CMOS Standby Current 40 40 mA Shaded areas contain advance information. Please contact your local CYpress sales representative for availability of this part. Pin Configuration Document #: 38-05437 Rev. *A A A OE 86 81 CEN 87 82 WE 88 NC(9M) CLK 89 83 VSS 90 ADV/LD VDD 91 NC(18M) CE3 92 84 BWA 93 85 NC NC 96 BWB CE2 97 94 A CE1 98 A 99 95 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A A A1 A0 NC NC VSS VDD NC(72M) NC(36M) A A A A A A NC CY7C1231F A BYTE B VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB VSS VDD VDD VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE NC NC NC 100 100-lead TQFP A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS VSS VDD ZZ BYTE A DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC Page 2 of 12 CY7C1231F Pin Definitions (100-pin TQFP Package) Name A0, A1, A BW[A:B] TQFP I/O Description 37,36,32,33,34, InputAddress Inputs used to select one of the 128K address locations. Sampled 35,44,45,46, Synchronous at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter. 47,48,49,80,81, 82,99,100 93,94 InputByte Write Inputs, active LOW. Qualified with WE to conduct writes to the Synchronous SRAM. Sampled on the rising edge of CLK. WE 88 InputWrite Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is Synchronous active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD 85 InputAdvance/Load Input. Used to advance the on-chip address counter or load a Synchronous new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK 89 CE1 98 InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE2, and CE3 to select/deselect the device. CE2 97 InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE1 and CE3 to select/deselect the device. CE3 92 InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE1 and CE2 to select/deselect the device. OE 86 InputOutput Enable, asynchronous input, active LOW. Combined with the Asynchronous synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. CEN 87 InputClock Enable Input, active LOW. When asserted LOW the Clock signal is recogSynchronous nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. ZZ 64 InputZZ “sleep” Input. This active HIGH input places the device in a non-time critical Asynchronous “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to VSS or left floating. 58,59,62,63, 68,69,72,73,8, 9,12,13,18,19, 22,23 I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register Synchronous that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. 74,24 I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to Synchronous DQs. During write sequences, DQP[A:B] is controlled by BWx correspondingly. DQs DQP[A:B] Mode 31 Input-Clock Input Strap Pin Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. VDD 15,16,41,65,91 Power Supply Power supply inputs to the core of the device. VDDQ 4,11,20,27,54, 61,70,77 I/O Power Supply VSS 5,10,14,17,21, 26,40,55,60, 66,67,71,76,90 Ground Document #: 38-05437 Rev. *A Power supply for the I/O circuitry. Ground for the device. Page 3 of 12 CY7C1231F Pin Definitions (100-pin TQFP Package) (continued) Name NC TQFP I/O 1,2,3,6,7,25,28, 29,30,38,39, 42,43,50,51,52, 53,56,57,75,78, 79,83,84,95,96 – Description No Connects. Not Internally connected to the die. 9M,18M,36M and 72M are address expansion pins and are not internally connected to the die. Functional Overview The CY7C1231F is a synchronous flow-through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 7.5 ns (117-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[A:B] can be used to conduct Byte Write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 7.5 ns (117-MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be three-stated immediately. Burst Read Accesses The CY7C1231F has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE Document #: 38-05437 Rev. *A input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of Chip Enable inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the Write signal WE is asserted LOW. The address presented to the address bus is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQP[A:B]. On the next clock rise the data presented to DQs and DQP[A:B] (or a subset for Byte Write operations, see Truth Table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by BW[A:B] signals. The CY7C1231F provides Byte Write capability that is described in the Truth Table. Asserting the Write Enable input (WE) with the selected Byte Write Select input will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the Write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1231F is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQP[A:B] inputs. Doing so will three-state the output drivers. As a safety precaution, DQs and DQP[A:B].are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1231F has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW[A:B] inputs must be driven in each cycle of the burst write, in order to write the correct bytes of data. Page 4 of 12 CY7C1231F Sleep Mode Interleaved Burst Sequence The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. First Address Second Address Third Address Fourth Address A1, A0 A1, A0 A1, A0 A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ Active to snooze current ZZ inactive to exit snooze current IDDZZ tZZS tZZREC tZZI tRZZI Test Conditions ZZ > VDD − 0.2V ZZ > VDD − 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled Min. Max. 40 2tCYC 2tCYC 2tCYC 0 Unit mA ns ns ns ns Truth Table[2, 3, 4, 5, 6, 7, 8] Operation Deselect Cycle Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK None H X X L L X X X L L->H Deselect Cycle None X Deselect Cycle None Continue Deselect Cycle None READ Cycle (Begin Burst) READ Cycle (Continue Burst) NOP/DUMMY READ (Begin Burst) DUMMY READ (Continue Burst) WRITE Cycle (Begin Burst) X H L X L X X X X External L H L Next X X X External L H L Next X X X DQ Three-State L X X X L L->H Three-State L L X X X L L->H Three-State L H X X X L L->H Three-State L L H X L L L->H Data Out (Q) L H X X L L L->H Data Out (Q) L L H X H L L->H Three-State L H X X H L L->H Three-State External L H L L L L L X L L->H Data In (D) WRITE Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D) NOP/WRITE ABORT (Begin Burst) None L H L L L L H X L L->H Three-State WRITE ABORT (Continue Burst) Next X X X L H X H X L L->H Three-State IGNORE CLOCK EDGE (Stall) SNOOZE MODE Current X X X L X X X X H L->H – None X X X H X X X X X X Three-State Notes: 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Truth Table for details. 3. Write is defined by BW[A:B], and WE. See Truth Table for Read/Write. 4. When a write cycle is detected, all I/Os are three-stated, even during byte writes. 5. The DQs and DQP[A:B] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CEN = H, inserts wait states. 7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:B] = Three-state when OE is inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active. Document #: 38-05437 Rev. *A Page 5 of 12 CY7C1231F Truth Table for Read/Write [2, 3] Function WE H BWA X BWB X Write – No bytes written L H H Write Byte A – (DQA and DQPA) L H H Write Byte B – (DQB and DQPB) L H H Write All Bytes L L L Read Document #: 38-05437 Rev. *A Page 6 of 12 CY7C1231F Maximum Ratings Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-up Current.................................................... > 200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND ...... –0.5V to +4.6V Range DC Voltage Applied to Outputs in Three-State ..................................... –0.5V to VDDQ + 0.5V Ambient Temperature (TA) Com’l 0°C to +70°C VDD VDDQ 3.3V – 5%/+10% 3.3V – 5% to VDD DC Input Voltage....................................–0.5V to VDD + 0.5V Electrical Characteristics Over the Operating Range [9,10] Parameter Description Test Conditions Min. Max. Unit VDD Power Supply Voltage 3.135 3.6 V VDDQ I/O Supply Voltage 3.135 VDD V VOH Output HIGH Voltage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA VOL Output LOW Voltage VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VIH Input HIGH Voltage VDDQ = 3.3V VIL Input LOW Voltage[9] VDDQ = 3.3V IX Input Load Current (except ZZ and MODE) GND ≤ VI ≤ VDDQ −5 Input Current of MODE Input = VSS –30 2.4 V 2.0 VDD + 0.3V V –0.3 0.8 V 5 µA Input = VDD Input Current of ZZ Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled Output Short Circuit Current VDD = Max., VOUT = GND IDD VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX= 1/tCYC ISB1 Automatic CE Power-down VDD = Max, Device Deselected, Current—TTL Inputs VIN ≥ VIH or VIN ≤ VIL, f = fMAX, inputs switching ISB2 Automatic CE Power-down VDD = Max, Device Deselected, Current—CMOS Inputs VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static ISB3 ISB4 µA µA –5 Input = VDD IOS µA 5 Input = VSS IOZ V 0.4 30 µA 5 µA –300 µA 8.5-ns cycle, 117 MHz 220 mA 10-ns cycle, 100 MHz 205 mA 8.5-ns cycle, 117 MHz 85 mA 10-ns cycle, 100 MHz 80 mA All speeds 40 mA Automatic CE Power-down VDD = Max, Device Deselected, 8.5-ns cycle, 117 MHz Current—CMOS Inputs VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V, 10-ns cycle, 100 MHz f = fMAX, inputs switching 70 mA 65 mA Automatic CE Power-down VDD = Max, Device Deselected, All speeds Current—TTL Inputs VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static 45 mA –5 Notes: 9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2). 10. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05437 Rev. *A Page 7 of 12 CY7C1231F Thermal Resistance[11] Parameters Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions TQFP Typ. Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 41.83 °C/W 9.99 °C/W Capacitance[11] Parameter Description CIN Input Capacitance CCLOCK Clock Input Capacitance CI/O I/O Capacitance Test Conditions Max. Unit 5 pF 5 pF 5 pF TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ=3.3V AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω VL = 1.5V (a) ALL INPUT PULSES VDDQ GND 5 pF INCLUDING JIG AND SCOPE R = 351Ω 90% 10% 90% 10% ≤ 1ns ≤ 1ns (c) (b) Switching Characteristics Over the Operating Range [12, 13] 117 MHz Parameter tPOWER Description VDD(Typical) to the first Access[14] Min. Max. 100 MHz Min. Max. Unit 1 1 ms Clock tCYC Clock Cycle Time 8.5 10 ns tCH Clock HIGH 3.0 4.0 ns tCL Clock LOW 3.0 4.0 ns Output Times tCDV Data Output Valid after CLK Rise tDOH Data Output Hold after CLK Rise tCLZ Clock to Low-Z[15, 16, 17] tCHZ Clock to High-Z[15, 16, 17] 3.5 3.5 ns tOEV OE LOW to Output Valid 3.5 3.5 ns [15, 16, 17] tOELZ OE LOW to Output Low-Z tOEHZ OE HIGH to Output High-Z[15, 16, 17] 7.5 8.5 ns 2.0 2.0 ns 0 0 ns 0 0 3.5 ns 3.5 ns Set-up Times tAS Address Set-up before CLK Rise 2.0 2.0 ns tALS ADV/LD Set-up before CLK Rise 2.0 2.0 ns tWES WE, BW[A:B] Set-up before CLK Rise 2.0 2.0 ns Notes: 11. Tested initially and after any design or process changes that may affect these parameters. 12. Timing reference level is 1.5V when VDDQ = 3.3V. 13. Test conditions shown in (a) of AC Test Loads, unless otherwise noted. 14. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can be initiated. 15. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 16. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve Three-state prior to Low-Z under the same system conditions. 17. This parameter is sampled and not 100% tested. Document #: 38-05437 Rev. *A Page 8 of 12 CY7C1231F Switching Characteristics Over the Operating Range (continued)[12, 13] 117 MHz Parameter Description Min. 100 MHz Max. Min. Max. Unit tCENS CEN Set-up before CLK Rise 2.0 2.0 ns tDS Data Input Set-up before CLK Rise 2.0 2.0 ns tCES Chip Enable Set-up before CLK Rise 2.0 2.0 ns tAH Address Hold after CLK Rise 0.5 0.5 ns tALH ADV/LD Hold after CLK Rise 0.5 0.5 ns tWEH WE, BW[A:B] Hold after CLK Rise 0.5 0.5 ns tCENH CEN Hold after CLK Rise 0.5 0.5 ns tDH Data Input Hold after CLK Rise 0.5 0.5 ns tCEH Chip Enable Hold after CLK Rise 0.5 0.5 ns Hold Times Switching Waveforms Read/Write Waveforms[18, 19, 20] 1 2 3 tCYC 4 5 6 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCES tCEH tCH tCL CEN CE ADV/LD WE BW[A:B] A1 ADDRESS tAS A2 A4 A3 tCDV tAH tDOH tCLZ DQ D(A1) tDS D(A2) Q(A3) D(A2+1) tOEV Q(A4+1) Q(A4) tOELZ WRITE D(A1) WRITE D(A2) D(A5) Q(A6) D(A7) WRITE D(A7) DESELECT tOEHZ tDH OE COMMAND tCHZ BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) tDOH WRITE D(A5) READ Q(A6) UNDEFINED Notes: 18. For this waveform ZZ is tied LOW. 19. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 20. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. Document #: 38-05437 Rev. *A Page 9 of 12 CY7C1231F Switching Waveforms NOP, STALL and Deselect Cycles[18, 19, 21] 1 2 3 A1 A2 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BW[A:B] ADDRESS A5 tCHZ D(A1) DQ Q(A2) Q(A3) D(A4) Q(A5) tDOH COMMAND WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL DON’T CARE NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED ZZ Mode Timing[22, 23] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON’T CARE Ordering Information Speed (MHz) 100 Ordering Code CY7C1231F-100AC Package Name A101 Package Type 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Operating Range Commercial Please contact your local Cypress sales representative for availability of 117MHz speed grade option. Notes: 21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. 22. Device must be deselected when entering ZZ mode. See Truth Table for all possible signal conditions to deselect the device. 23. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05437 Rev. *A Page 10 of 12 CY7C1231F Package Diagram 100-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05437 Rev. *A Page 11 of 12 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1231F Document History Page Document Title: CY7C1231F 2-Mbit (128K x 18) Flow-through SRAM with NoBL™ Architecture Document Number: 38-05437 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201060 See ECN NJY New Data Sheet *A 213321 See ECN VBL Updated Ordering Info section: shaded part number, added explanation Shaded Selection guide and Characteristics table Document #: 38-05437 Rev. *A Page 12 of 12