Cypress CY7C1367A-150AJC 256k x 36/512k x 18 pipelined sram Datasheet

CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K x 36/512K x 18 Pipelined SRAM
Features
and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2
and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write
(GW). However, the CE2 Chip Enable input is only available for
the TA(GVTI)/A(CY) package version.
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and
150 MHz
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Optimal for performance (two cycle chip deselect, depth
expansion without wait state)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to V SS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
• Address pipeline capability
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down for portable applications
• JTAG boundary scan for B and T package version
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide, as controlled by the write control inputs.
Individual byte write allows an individual byte to be written.
BWa controls DQa. BWb controls DQb. BWc controls DQc.
BWd controls DQd. BWa, BWb, BWc, and BWd can be active
only with BWE being LOW. GW being LOW causes all bytes
to be written. The x18 version only has 18 data inputs/outputs
(DQa and DQb) along with BWa and BWb (no BWc, BWd,
DQc, and DQd).
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package versions, four pins are used to implement JTAG test capabilities:
Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),
and Test Data-Out (TDO). The JTAG circuitry is used to serially
shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode of
operation. The TA package version does not offer the JTAG
capability.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
The
CY7C1366A/GVT71256C36
and
CY7C1367A/
GVT71512C18 operate from a +3.3V power supply. All inputs
and outputs are LVTTL compatible.
The
CY7C1366A/GVT71256C36
and
CY7C1367A/
GVT71512C18 SRAMs integrate 262,144 x 36 and 524,288 x
18 SRAM cells with advanced synchronous peripheral circuitry
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
Maximum CMOS Standby Current (mA)
Cypress Semiconductor Corporation
•
7C1366A-225/
71256C36-4.4
7C1367A-225/
71512C18-4.4
7C1366A-200/
71256C36-5
7C1367A-200/
71512C18-5
7C1366A-166/
71256C36-6
7C1367A-166/
71512C18-6
7C1366A-150/
71256C36-6.7
7C1367A-150/
71512C18-6.7
2.5
3.0
3.5
3.5
570
510
425
380
10
10
10
10
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 12, 2001
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Functional Block Diagram—256K x 36[1]
BYTE a WRITE
BWa#
BWE#
D
Q
CLK
BYTE b WRITE
BWb#
D
Q
GW#
BYTE c WRITE
BWc#
D
Q
BYTE d WRITE
CE2
CE2#
ENABLE
D
[2]
Q
D
Q
byte b write
byte a write
CE#
Q
byte c write
D
byte d write
BWd#
OE#
Power Down Logic
Input
Register
ADSP#
A
16
Address
Register
CLR
ADV#
OUTPUT
REGISTER
256K x 9 x 4
SRAM Array
ADSC#
D
Q
Binary
Counter
& Logic
A1-A0
Output Buffers
ZZ
DQa,DQb
DQc,DQd
MODE
Functional Block Diagram—512K x 18[1]
BYTE b
WRITE
BWb#
BWE#
D
BWa#
D
Q
BYTE a
WRITE
Q
ENABLE
D
CE2
[2]
CE2#
ZZ
Q
D
Q
byte b write
CE#
byte a write
GW#
Power Down Logic
OE#
ADSP#
Input
Register
17
Address
Register
CLR
ADV#
A1-A0
OUTPUT
REGISTER
D
Binary
Counter
& Logic
Q
Output Buffers
ADSC#
512K x 9 x 2
SRAM Array
A
DQa,D
Qb
MODE
Notes:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
2. CE2 is for TA version only.
2
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1366A/GVT71256C36
(256K X 36)
T Package Version
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
NC
NC
NC
VCCQ
VSS
NC
NC
DQb
DQb
VSS
VCCQ
DQb
DQb
NC
VCC
NC
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
VSS
VCCQ
NC
NC
NC
CY7C1367A/GVT71512C18
(512K x 18)
T Package Version
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VCCQ
VSS
NC
DPa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
MODE
A
A
A
A
A1
A0
TMS
TDI
VSS
VCC
TDO
TCK
A
A
A
A
A
A
A
MODE
A
A
A
A
A1
A0
TMS
TDI
VSS
VCC
TDO
TCK
A
A
A
A
A
A
A
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1366A/GVT71256C36
(256K X 36)
TA Package Version
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
NC
NC
NC
VCCQ
VSS
NC
NC
DQb
DQb
VSS
VCCQ
DQb
DQb
NC
VCC
NC
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
VSS
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1367A/GVT71512C18
(512K x 18)
TA Package Version
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VCC
NC
A
A
A
A
A
A
A
A
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VCC
NC
A
A
A
A
A
A
A
A
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
NC
VCC
NC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
NC
VCC
NC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
CE2
NC
NC
BWb
BWa
A
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE
CE2
BWd
BWc
BWb
BWa
A
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin TQFP
Top View
3
A
NC
NC
VCCQ
VSS
NC
DPa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
NC
VSS
VCCQ
NC
NC
NC
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Pin Configurations (continued)
119-Ball BGA
Top View
256Kx36
A
1
2
3
4
5
6
7
VCCQ
A
A
ADSP
A
A
VCCQ
B
NC
CE2
A
ADSC
A
A
NC
C
NC
A
A
VCC
A
A
NC
D
DQc
DQc
VSS
NC
VSS
DQb
DQb
E
DQc
DQc
VSS
CE
VSS
DQb
DQb
F
VCCQ
DQc
VSS
OE
VSS
DQb
VCCQ
G
DQc
DQc
BWc
ADV
BWb
DQb
DQb
H
DQc
DQc
VSS
GW
VSS
DQb
DQb
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VCCQ
DQd
VSS
BWE
VSS
DQa
VCCQ
N
DQd
DQd
VSS
A1
VSS
DQa
DQa
P
DQd
DQd
VSS
A0
VSS
DQa
DQa
R
NC
A
MODE
VCC
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
4
5
6
7
512Kx18
1
2
3
A
VCCQ
A
A
ADSP
A
A
VCCQ
B
NC
CE2
A
ADSC
A
CE2
NC
C
NC
A
A
VCC
A
A
NC
D
DQb
NC
VSS
NC
VSS
DQa
NC
E
NC
DQb
VSS
CE
VSS
NC
DQa
F
VCCQ
NC
VSS
OE
VSS
DQa
VCCQ
G
NC
DQb
BWb
ADV
VSS
NC
DQa
H
DQb
NC
VSS
GW
VSS
DQa
NC
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
NC
DQb
VSS
CLK
VSS
NC
DQa
L
DQb
NC
VSS
NC
BWa
DQa
NC
M
VCCQ
DQb
VSS
BWE
VSS
NC
VCCQ
N
DQb
NC
VSS
A1
VSS
DQa
NC
P
NC
DQb
VSS
A0
VSS
NC
DQa
R
NC
A
MODE
VCC
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
4
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K X 36 Pin Descriptions
X36 PBGA Pins
X36 QFP Pins
Name
Type
Description
4P
4N
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 3T, 4T,
5T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
44, 45, 46, 47,
48, 49, 50
92 (T Version)
43 (TA Version)
A0
A1
A
InputSynchronous
Addresses: These inputs are registered and must meet the set
up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
5L
5G
3G
3L
93
94
95
96
BWa
BWb
BWc
BWd
InputSynchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH
for a READ cycle. BWa controls DQa. BWb controls DQb. BWc
controls DQc. BWd controls DQd. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE
being LOW.
4M
87
BWE
InputSynchronous
Write Enable: This active LOW input gates byte write operations and must meet the set-up and hold times around the
rising edge of CLK.
4H
88
GW
InputSynchronous
Global Write: This active LOW input allows a full 36-bit Write
to occur independent of the BWE and BWn lines and must
meet the set-up and hold times around the rising edge of CLK.
4K
89
CLK
InputSynchronous
Clock: This signal registers the addresses, data, chip enables,
write control, and burst control inputs on its rising edge. All
synchronous inputs must meet set up and hold times around
the clock’s rising edge.
4E
98
CE
InputSynchronous
Chip Enable: This active LOW input is used to enable the device and to gate ADSP.
2B
97
CE2
InputSynchronous
Chip Enable: This active HIGH input is used to enable the device.
(not available for
PBGA)
92 (for TA
Version only)
CE2
InputSynchronous
Chip Enable: This active LOW input is used to enable the device. Not available for B and T package versions.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input enables
the data output drivers.
4G
83
ADV
InputSynchronous
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
4A
84
ADSP
InputSynchronous
Address Status Processor: This active LOW input, along with
CE being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address.
4B
85
ADSC
InputSynchronous
Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon write control inputs.
3R
31
MODE
InputStatic
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interleaved Burst.
7T
64
ZZ
InputSnooze: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
5
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K X 36 Pin Descriptions (continued)
X36 PBGA Pins
X36 QFP Pins
Name
Type
Description
(a) 6P, 7P, 7N, 6N,
6M, 6L, 7L, 6K, 7K,
(b) 7H, 6H, 7G, 6G,
6F, 6E, 7E, 7D, 6D,
(c) 2D, 1D, 1E, 2E,
2F, 1G, 2G, 1H, 2H,
(d) 1K, 2K, 1L, 2L,
2M, 1N, 2N, 1P, 2P
(a) 51, 52, 53, 56,
57, 58, 59, 62, 63
(b) 68, 69, 72, 73,
74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8,
9, 12, 13
(d) 18, 19, 22, 23,
24, 25, 28, 29, 30
DQa
DQb
DQc
DQd
Input/
Output
Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb.
Third Byte is DQc. Fourth Byte is DQd. Input data must meet
set-up and hold times around the rising edge of CLK.
2U
3U
4U
38
39
43
for B and T
version
TMS
TDI
TCK
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. Not available for
TA package version.
5U
42
for B and T
version
TDO
Output
IEEE 1149.1 test output. LVTTL-level output. Not available for
TA package version.
4C, 2J, 4J, 6J, 4R
15, 41,65, 91
VCC
Supply
Core power Supply: +3.3V –5% and +10%
3D, 5D, 3E, 5E, 3F, 5, 10, 17, 21, 26,
5F, 3H, 5H, 3K, 5K, 40, 55, 60, 67,
71, 76, 90
3M, 5M, 3N, 5N,
3P, 5P
VSS
Ground
Ground: GND.
1A, 7A, 1F, 7F, 1J, 4, 11, 20, 27, 54,
7J, 1M, 7M, 1U, 7U
61, 70, 77
VCCQ
I/O Supply
1B, 7B, 1C, 7C, 4D,
14, 16, 66
3J, 5J, 4L, 1R, 5R,
7R, 1T, 2T, 6T, 6U 38, 39, 42 for TA
Version
NC
-
Output Buffer Supply: +2.5V or +3.3V.
No Connect: These signals are not internally connected. User
can leave it floating or connect it to VCC or VSS.
512K X 18 Pin Descriptions
X18 PBGA Pins
X18 QFP Pins
Name
Type
Description
4P
4N
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 2T, 3T,
5T, 6T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
80, 48, 47, 46,
45, 44, 49, 50
92 (T Version)
43 (TA Version)
A0
A1
A
InputSynchronous
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
5L
3G
93
94
BWa
BWb
InputSynchronous
Byte Write Enables: A byte write enable is LOW for a WRITE
cycle and HIGH for a READ cycle. BWa controls DQa. BWb
controls DQb. Data I/O are high impedance if either of these
inputs are LOW, conditioned by BWE being LOW.
4M
87
BWE
InputSynchronous
Write Enable: This active LOW input gates byte write operations and must meet the set up and hold times around the rising
edge of CLK.
4H
88
GW
InputSynchronous
Global Write: This active LOW input allows a full 18-bit WRITE
to occur independent of the BWE and WEn lines and must
meet the set up and hold times around the rising edge of CLK.
4K
89
CLK
InputSynchronous
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around
the clock’s rising edge.
4E
98
CE
InputSynchronous
Chip Enable: This active LOW input is used to enable the device and to gate ADSP.
6
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
512K X 18 Pin Descriptions (continued)
X18 PBGA Pins
X18 QFP Pins
Name
Type
2B
97
CE2
InputSynchronous
Chip Enable: This active HIGH input is used to enable the
device.
(not available for
PBGA)
92 (for TA Version only)
CE2
InputSynchronous
Chip Enable: This active LOW input is used to enable the device. Not available for B and T package versions.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input enables
the data output drivers.
4G
83
ADV
InputSynchronous
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
4A
84
ADSP
InputSynchronous
Address Status Processor: This active LOW input, along with
CE being LOW, causes a new external address to be registered
and a Read cycle is initiated using the new address.
4B
85
ADSC
InputSynchronous
Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon write control inputs.
3R
31
MODE
InputStatic
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interlinear Burst.
7T
64
ZZ
(a) 6D, 7E, 6F, 7G, (a) 58, 59, 62, 63,
6H, 7K, 6L, 6N, 7P 68, 69, 72, 73, 74
(b) 1D, 2E, 2G, 1H, (b) 8, 9, 12, 13,
2K, 1L, 2M, 1N, 2P 18, 19, 22, 23, 24
Description
InputSnooze: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
DQa
DQb
Input/
Output
Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb. Input
data must meet set up and hold times around the rising edge
of CLK.
2U
3U
4U
38
39
43
for B and T
version
TMS
TDI
TCK
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. Not available for
TA package version.
5U
42
for B and T
version
TDO
Output
IEEE 1149.1 test output. LVTTL-level output. Not available for
TA package version.
4C, 2J, 4J, 6J, 4R
15, 41,65, 91
VCC
Supply
Core power Supply: +3.3V –5% and +10%
3D, 5D, 3E, 5E, 3F, 5, 10, 17, 21, 26,
5F, 5G, 3H, 5H, 3K, 40, 55, 60, 67,
71, 76, 90
5K, 3L, 3M, 5M,
3N, 5N, 3P, 5P
VSS
Ground
Ground: GND.
1A, 7A, 1F, 7F, 1J, 4, 11, 20, 27, 54,
7J, 1M, 7M, 1U, 7U
61, 70, 77
VCCQ
I/O Supply
NC
-
1B, 7B, 1C, 7C, 2D,
4D, 7D, 1E, 6E, 2F,
1G, 6G, 2H, 7H,
3J, 5J, 1K, 6K, 2L,
4L, 7L, 6M, 2N, 7N,
1P, 6P, 1R, 5R, 7R,
1T, 4T, 6U
1-3, 6, 7, 14, 16,
25, 28-30, 51-53,
56, 57, 66, 75,
78, 79, 80, 95, 96
Output Buffer Supply: +2.5V or +3.3V.
No Connect: These signals are not internally connected. User
can leave it floating or connect it to V CC or VSS.
38, 39, 42 for TA
Version
7
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Burst Address Table (MODE = NC/VCC)
Burst Address Table (MODE = GND)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
A...A11
A...A00
A...A01
A...A10
Truth Table[3, 4, 5, 6, 7, 8, 9]
Operation
Address Used CE
CE2
CE2
ADSP
ADSC
ADV WRITE OE
CLK
DQ
Deselected Cycle, Power
Down
None
H
X
X
X
L
X
X
X
L-H
High-Z
Deselected Cycle, Power
Down
None
L
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power
Down
None
L
H
X
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power
Down
None
L
X
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power
Down
None
L
H
X
H
L
X
X
X
L-H
High-Z
READ Cycle, Begin Burst
External
L
L
H
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
X
X
X
H
L-H
High-Z
WRITE Cycle, Begin Burst
External
L
L
H
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
H
L
X
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
L-H
High-Z
WRITE Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
L-H
D
Notes:
3. X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For X36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
4. BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
5. All inputs except OE must meet set up and hold times around the rising edge (LOW to HIGH) of CLK.
6. Suspending burst generates wait cycle.
7. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
8. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
9. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for
the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
8
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Partial Truth Table for READ/WRITE[10]
GW
BWE
BWa
BWb
BWc
BWd
READ
Function
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE one byte
H
L
L
H
H
H
WRITE all bytes
H
L
L
L
L
L
WRITE all bytes
L
X
X
X
X
X
IEEE 1149.1 Serial Boundary Scan (JTAG)
TDO - Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1, TAP Controller State
Diagram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed between TDI and TDO. TDO is connected to the Least Significant
Bit (LSB) of any register (see Figure 2).
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra
delays in the critical speed path of the device. Nevertheless,
the device supports the standard TAP controller architecture
(the TAP controller is the state machine that controls the TAPs
operation) and can be expected to function in a manner that
does not conflict with the operation of devices with IEEE Standard 1149.1 compliant TAPs. The TAP operates using LVTTL/
LVCMOS logic level signaling.
Performing a TAP Reset
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
performed for the TAP controller by forcing TMS HIGH (VCC)
for five rising edges of TCK and pre-loads the instruction register with the IDCODE command. This type of reset does not
affect the operation of the system logic. The reset affects test
logic only.
Disabling the JTAG Feature
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to prevent clocking the device. TDI and TMS are internally pulled up
and may be unconnected. They may alternately be pulled up
to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Test Access Port (TAP) Registers
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
Test Access Port (TAP)
TCK - Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
Instruction Register
The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle
or the various data register states. The instructions are three
bits long. The register can be loaded when it is placed between
the TDI and TDO pins. The parallel outputs of the instruction
register are automatically preloaded with the IDCODE instruction upon power-up or whenever the controller is placed in the
test-logic reset state. When the TAP controller is in the Capture-IR state, the two least significant bits of the serial instruction register are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
TMS - Test Mode Select (INPUT)
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
TDI - Test Data In (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register see
Figure 1. It is allowable to leave this pin unconnected if it is not
used in an application. The pin is pulled up internally, resulting
in a logic HIGH level. TDI is connected to the Most Significant
Bit (MSB) of any register (see Figure 2).
Bypass Register
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (V SS)
when the BYPASS instruction is executed.
Note:
10. For the X18 product, There are only BWa and BWb.
9
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Boundary Scan Register
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
The Boundary Scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for x36 device and 51
bits for x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the
device I/O ring when the controller is in Capture-DR state and
then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to
capture the contents of the I/O ring.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and
TDO pins in Shift-DR mode. The IDCODE instruction is the
default instruction loaded in the instruction upon power-up and
at any time the TAP controller is placed in the test-logic reset
state.
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s position in the boundary scan register. The MSB of the register is
connected to TDI, and LSB is connected to TDO. The second
column is the signal name, the third column is the TQFP pin
number, and the fourth column is the BGA bump number.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded in the instruction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture set up plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
TAP Controller Instruction Set
Overview
There are two classes of instructions defined in the IEEE Standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implemented.
The TAP on this device may be used to monitor all input and
I/O pads, but can not be used to load address, data, or control
signals into the device or to preload the I/O buffers. In other
words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command.
Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the
PRELOAD portion of the command is not implemented in this
device, moving the controller to the Update-DR state with the
SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the Pause-DR command.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the instruction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction sets
for this device are listed in the following tables.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP controller is in the Shift-DR state, the bypass
register is placed between TDI and TDO. This allows the board
level scan path to be shortened to facilitate testing of other
devices in the scan path.
EXTEST
Reserved
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
Do not use these instructions. They are reserved for future
use.
10
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
1
TEST-LOGIC
RESET
0
0
REUN-TEST/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
SHIFT-IR
0
1
0
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
Figure 1. TAP Controller State Diagram [11]
Note:
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
11
UPDATE-IR
1
0
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
x
.
.
.
.
2
Boundary Scan Register [12]
TDI
TAP Controller
TDI
Figure 2. TAP Controller Block Diagram
TAP Electrical Characteristics Over the Operating Range
Parameter
VIH
Description
Test Conditions
Input High (Logic 1) Voltage
[13, 14]
[13, 14]
Min.
Max.
Unit
2.0
VCC + 0.3
V
–0.3
0.8
V
VIl
Input Low (Logic 0) Voltage
ILI
Input Leakage Current
0V < V IN < VCC
–5.0
5.0
µA
ILI
TMS and TDI Input Leakage Current
0V < V IN < VCC
–30
30
µA
ILO
Output Leakage Current
Output disabled,
0V < V IN < VCCQ
–5.0
5.0
µA
VOLC
LVCMOS Output Low Voltage[13, 15]
IOLC = 100 µA
0.2
V
VOHC
[13, 15]
IOHC = 100 µA
VOLT
VOHT
LVCMOS Output High Voltage
LVTTL Output Low Voltage
[13]
IOLT = 8.0 mA
[13]
IOHT = 8.0 mA
LVTTL Output High Voltage
VCC – 0.2
V
0.4
2.4
V
V
Notes:
12. X = 69 for the x36 configuration;
X = 50 for the x18 configuration.
13. All Voltage referenced to VSS (GND).
14. Overshoot: VIH(AC)<VCC+1.5V for t<t KHKH/2, Undershoot: VIL (AC)<–0.5V for t<tKHKH/2, Power-up: VIH<3.6V and VCC<3.135V and VCCQ<1.4V for t<200 ms.
During normal operation, VCCQ must not exceed VCC. Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than tKHKL (min.).
15. This parameter is sampled.
12
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
TAP AC Switching Characteristics Over the Operating Range [16, 17]
Parameter
Description
Min.
Max
Unit
Clock
tTHTH
Clock Cycle Time
20
ns
fTF
Clock Frequency
tTHTL
Clock HIGH Time
8
ns
tTLTH
Clock LOW Time
8
ns
tTLQX
TCK LOW to TDO Unknown
0
ns
tTLQV
TCK LOW to TDO Valid
tDVTH
TDI Valid to TCK HIGH
5
ns
tTHDX
TCK HIGH to TDI Invalid
5
ns
tMVTH
TMS Set-up
5
ns
tCS
Capture Set-up
5
ns
tTHMX
TMS Hold
5
ns
tCH
Capture Hold
5
ns
50
MHz
Output Times
10
ns
Set-up Times
Hold Times
Notes:
16. t CS and t CH refer to the set-up and hold time requirements of latching data from the boundary scan register.
17. Test conditions are specified using the load in TAP AC Test Conditions.
13
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
TAP Timing and Test Conditions
ALL INPUT PULSES
TDO
Z0 = 50Ω
50Ω
3.0V
20 pF
1.5V
VSS
Vt = 1.5V
1.5 ns
1.5 ns
(b)
(a)
t
tT H T H
THTL
TEST CLOCK
(TCK)
tM V T H
tT H M X
tD V T H
tT H D X
TEST MODE SELECT
(TMS)
TEST DATA IN
(TDI)
tT L Q V
tT L Q X
TEST DATA OUT
(TDO)
14
t
TLTH
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Identification Register Definitions
Instruction Field
256K x 36
512K x 18
REVISION NUMBER
(31:28)
XXXX
XXXX
Reserved for revision number.
DEVICE DEPTH
(27:23)
00110
00111
Defines depth of 256K or 512K words.
DEVICE WIDTH
(22:18)
00100
00011
Defines width of x36 or x18 bits.
XXXXXX
XXXXXX
CYPRESS JEDEC ID
CODE (11:1)
00011100100
00011100100
ID Register Presence
Indicator (0)
1
1
RESERVED
(17:12)
Description
Reserved for future use.
Allows unique identification of DEVICE vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary Scan
70
51
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state. This instruction is not
IEEE 1149.1-compliant.
IDCODE
001
Preloads ID register with vendor ID code and places it between TDI and
TDO. This instruction does not affect device operations.
SAMPLE-Z
010
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state.
RESERVED
011
Do not use these instructions; they are reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. This instruction does not affect device operations. This instruction
does not implement IEEE 1149.1 PRELOAD function and is therefore not
1149.1-compliant.
RESERVED
101
Do not use these instructions; they are reserved for future use.
RESERVED
110
Do not use these instructions; they are reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This instruction does not
affect device operations.
15
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Boundary Scan Order (256K x 36) (continued)
Boundary Scan Order (256K x 36)
Bit#
Signal
Name
TQFP
Bump ID
Bit#
Signal
Name
TQFP
Bump ID
A
92
6B
1
A
44
2R
36
2
A
45
3T
37
BWa
93
5L
3
A
46
4T
38
BWb
94
5G
4
A
47
5T
39
BWc
95
3G
BWd
96
3L
5
A
48
6R
40
6
A
49
3B
41
CE2
97
2B
7
A
50
5B
42
CE
98
4E
8
DQa
51
6P
43
A
99
3A
A
100
2A
9
DQa
52
7N
44
10
DQa
53
6M
45
DQc
1
2D
11
DQa
56
7L
46
DQc
2
1E
12
DQa
57
6K
47
DQc
3
2F
DQc
6
1G
13
DQa
58
7P
48
14
DQa
59
6N
49
DQc
7
2H
15
DQa
62
6L
50
DQc
8
1D
16
DQa
63
7K
51
DQc
9
2E
DQc
12
2G
17
ZZ
64
7T
52
18
DQb
68
6H
53
DQc
13
1H
19
DQb
69
7G
54
NC
14
5R
20
DQb
72
6F
55
DQd
18
2K
DQd
19
1L
21
DQb
73
7E
56
22
DQb
74
6D
57
DQd
22
2M
23
DQb
75
7H
58
DQd
23
1N
24
DQb
78
6G
59
DQd
24
2P
DQd
25
1K
25
DQb
79
6E
60
26
DQb
80
7D
61
DQd
28
2L
27
A
81
6A
62
DQd
29
2N
28
A
82
5A
63
DQd
30
1P
MODE
31
3R
29
ADV
83
4G
64
30
ADSP
84
4A
65
A
32
2C
31
ADSC
85
4B
66
A
33
3C
32
OE
86
4F
67
A
34
5C
A
35
6C
33
BWE
87
4M
68
34
GW
88
4H
69
A1
36
4N
35
CLK
89
4K
70
A0
37
4P
16
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Boundary Scan Order (512K x 18) (continued)
Boundary Scan Order (512K x 18)
Bit#
Signal
Name
TQFP
Bump ID
Bit#
Signal
Name
TQFP
Bump ID
CLK
89
4K
1
A
44
2R
27
2
A
45
2T
28
A
92
6B
3
A
46
3T
29
BWa
93
5L
4
A
47
5T
30
BWb
94
3G
CE2
97
2B
5
A
48
6R
31
6
A
49
3B
32
CE
98
4E
7
A
50
5B
33
A
99
3A
8
DQa
58
7P
34
A
100
2A
DQb
8
1D
9
DQa
59
6N
35
10
DQa
62
6L
36
DQb
9
2E
11
DQa
63
7K
37
DQb
12
2G
12
ZZ
64
7T
38
DQb
13
1H
NC
14
5R
13
DQa
68
6H
39
14
DQa
69
7G
40
DQb
18
2K
15
DQa
72
6F
41
DQb
19
1L
16
DQa
73
7E
42
DQb
22
2M
DQb
23
1N
17
DQa
74
6D
43
18
A
80
6T
44
DQb
24
2P
19
A
81
6A
45
MODE
31
3R
20
A
82
5A
46
A
32
2C
A
33
3C
21
ADV
83
4G
47
22
ADSP
84
4A
48
A
34
5C
23
ADSC
85
4B
49
A
35
6C
24
OE
86
4F
50
A1
36
4N
51
A0
37
4P
25
BWE
87
4M
26
GW
88
4H
17
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Power Dissipation ......................................................... 1.0W
Maximum Ratings
Short Circuit Output Current........................................ 50 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V
Operating Range
VIN ...........................................................–0.5V to VCC+0.5V
Range
Ambient
Temperature[18]
VCC
Com’l
0°C to +70°C
3.3V –5%/+10%
Storage Temperature (plastic) .......................–55°C to +150°
Junction Temperature ...................................................+150°
Electrical Characteristics Over the Operating Range
Parameter
VIHD
Description
Test Conditions
Input High (Logic 1) Voltage
[13, 19]
VIH
VIl
Input Low (Logic 0) Voltage
ILI
Input Leakage Current
Min.
Max.
Unit
Data Inputs (DQx)
2.0
VCC+0.3
V
All Other Inputs
2.0
4.6
V
–0.5
0.8
V
0V < VIN < V CC
–5
5
µA
[13, 19]
ILI
MODE and ZZ Input Leakage Current
0V < VIN < V CC
–30
30
µA
ILO
Output Leakage Current
Output(s) disabled,
0V < VOUT < VCC
–5
5
µA
VOH
Output High Voltage[13]
IOH = –5.0 mA
2.4
VOL
Output Low Voltage[13]
IOL = 8.0 mA
[20]
VCC
Supply Voltage
VCCQ
VCCQ
[13]
V
0.4
V
3.135
3.6
V
I/O Supply Voltage (3.3V)
[13]
3.135
VCC
V
I/O Supply Voltage (2.5V)
[13]
2.375
VCC
V
Parameter
Description
Conditions
Typ.
-4.4
225
MHz
-5
200
MHz
-6
166
MHz
-6.7
150
MHz
Unit
150
570
510
425
380
mA
ICC
Power Supply Current:
Operating[21, 22, 23]
Device selected; all inputs < V IL
or> VIH; cycle time > tKC min.;
VCC = Max.; outputs open
ISB2
CMOS Standby[22, 23]
Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or >VCC – 0.2;
all inputs static; CLK frequency = 0
5
10
10
10
10
mA
ISB3
TTL Standby[22, 23]
Device deselected; all inputs < VIL
or > VIH; all inputs static;
VCC = MAX; CLK frequency = 0
15
30
30
30
30
mA
ISB4
Clock Running[22, 23]
Device deselected;
all inputs < VIL or > VIH; VCC = Max.
CLK cycle time > tKC Min.
40
125
110
90
80
mA
Capacitance[15]
Parameter
Description
CI
Input Capacitance
CO
Input/Output Capacitance (DQ)
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Typ.
Max.
Unit
5
7
pF
7
8
pF
Notes:
18. TA is the case temperature.
19. Overshoot: VIH < +6.0V for t < tKC /2
Undershoot:VIL < –2.0V for t < tKC /2.
20. Output loading is specified with CL=5 pF as in AC Test Loads.
21. I CC is given with no output current. ICC increases with greater output loading and faster cycle times.
22. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.
23. Typical values are measured at 3.3V, 25°C, and 20 ns cycle time.
18
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Thermal Resistance
Description
Test Conditions
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch,
4-layer PCB
Thermal Resistance (Junction to Case)
Symbol
TQFP Typ.
Unit
ΘJA
25
°C/W
ΘJC
9
°C/W
AC Test Loads and Waveforms for 3.3V I/O
317Ω
3.3V
DQ
ALL INPUT PULSES
DQ
Z0 =50Ω
3.0V
10%
50Ω
5 pF
351Ω
0V
≤ 1.0 ns
≤ 1.0 ns
Vt = 1.5V
(a)
90%
10%
90%
(c)
(b)
AC Test Loads and Waveforms for 2.5V I/O
DQ
ALL INPUT PULSES
Z0 =50Ω
2.5V
50Ω
10%
90%
10%
90%
0V
≤ 1.0 ns
≤ 1.0 ns
Vt = 1.25V
(c)
(a)
19
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Switching Characteristics Over the Operating Range[24]
-4.4
225 MHz
Parameter
Description
Min.
Max.
-5
200 MHz
Min.
Max.
-6
166 MHz
Min.
Max.
-6.7
150 MHz
Min.
Max.
Unit
Clock
tKC
Clock Cycle Time
4.4
5.0
6.0
6.7
ns
tKH
Clock HIGH Time
1.7
2.0
2.4
2.6
ns
tKL
Clock LOW Time
1.7
2.0
2.4
2.6
ns
Output Times
tKQ
Clock to Output Valid
VCCQ = 3.3V
2.5
3.0
3.5
3.5
ns
4.5
ns
VCCQ = 2.5V
tKQX
Clock to Output Invalid
3.0
[15, 25, 26]
tKQLZ
Clock to Output in Low-Z
tKQHZ
Clock to Output in High-Z [15, 25, 26]
tOEQ
OE to Output Valid
[27]
VCCQ = 3.3V
3.5
4.0
1.25
1.25
1.25
1.25
ns
0
0
0
0
ns
1.25
3.0
1.25
3.0
1.25
4.0
1.25
4.0
ns
VCCQ = 2.5V
tOELZ
OE to Output in Low-Z
tOEHZ
[15, 25, 26]
OE to Output in High-Z
[15, 25, 26]
2.5
3.0
3.5
3.5
ns
3.0
3.5
4.0
4.5
ns
Set-up Times
tS
Address, Controls, and Data In[28]
1.5
1.5
1.5
2.0
ns
Address, Controls, and Data In[28]
0.5
0.5
0.5
0.5
ns
Hold Times
tH
Typical Output Buffer Characteristics
Output High Voltage
Pull-Up Current
Output Low Voltage
Pull-Down Current
VOH (V)
IOH (mA) Min.
IOH (mA) Max.
VOL (V)
IOL (mA) Min.
IOL (mA) Max.
–0.5
–38
–105
–0.5
0
0
0
–38
–105
0
0
0
0.8
–38
–105
0.4
10
20
1.25
–26
–83
0.8
20
40
1.5
–20
–70
1.25
31
63
2.3
0
–30
1.6
40
80
2.7
0
–10
2.8
40
80
2.9
0
0
3.2
40
80
3.4
0
0
3.4
40
80
Notes:
24. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
25. Output loading is specified with CL=5 pF as in part (a) of AC Test Loads.
26. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than t OELZ.
27. OE is a “Don’t Care” when a byte write enable is sampled LOW.
28. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for “Don’t Care” as defined in the truth table.
20
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Switching Waveforms
Read Timing[29, 30]
tKC
tKL
CLK
tKH
tS
ADSP#
tH
ADSC#
tS
ADDRESS
BWa#, BWb#,
BWc#, BWd#
BWE#, GW#
A1
A2
tH
tS
CE#
tS
ADV#
tH
OE#
tKQ
DQ
tKQLZ
tOELZ
Q(A1)
tKQ
tOEQ
Q(A2)
SINGLE READ
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
BURST READ
Notes:
29. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. CE2 is only available for TA package version.
30. For the X18 product, there are only BWa and BWb for byte write control.
21
Q(A2+1)
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Switching Waveforms (continued)
Write Timing[29, 30]
CLK
tS
ADSP#
tH
ADSC#
tS
A1
ADDRESS
A2
A3
tH
BWa#, BWb#,
BWc#, BWd#,
BWE#
GW#
CE#
tS
ADV#
tH
OE#
tKQX
DQ
Q
tOEHZ
D(A1)
D(A2)
D(A2+1)
SINGLE WRITE
D(A2+1)
D(A2+2)
BURST WRITE
22
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
BURST WRITE
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Switching Waveforms (continued)
Read/Write Timing[29, 30]
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS
BWa#, BWb#,
BWc#, BWd#,
BWE#, GW#
A1
A2
A3
A4
A5
tH
CE#
ADV#
OE#
DQ
Q(A1)
Single Reads
Q(A2)
D(A3)
Single Write
23
Q(A4)
Q(A4+1)
Burst Read
Q(A4+2)
D(A5)
D(A5+1)
Burst Write
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Ordering Information
Speed
(MHz)
225
200
166
150
Package
Name
Package Type
Operating
Range
CY7C1366A-225AJC/
GVT71256C36T-4.4
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1366A-225AC/
GVT71256C36TA-4.4
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-225BGC/
GVT71256C36B-4.4
BG119
CY7C1366A-200AJC/
GVT71256C36T-5
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-200AC/
GVT71256C36TA-5
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Ordering Code
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1366A-200BGC/
GVT71256C36B-5
BG119
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1366A-166AJC/
GVT71256C36T-6
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-166AC/
GVT71256C36TA-6
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-166BGC/
GVT71256C36B-6
BG119
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1366A-150AJC/
GVT71256C36T-6.7
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-150AC/
GVT71256C36TA-6.7
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1366A-150BGC/
GVT71256C36B-6.7
BG119
119-Lead BGA (14 x 22 x 2.4 mm)
24
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Ordering Information (continued)
Speed
(MHz)
225
200
166
150
Package
Name
Package Type
Operating
Range
CY7C1367A-225AJC/
GVT71512C18T-4.4
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1367A-225AC/
GVT71512C18TA-4.4
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-225BGC/
GVT71512C18B-4.4
BG119
CY7C1367A-200AJC/
GVT71512C18T-5
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-200AC/
GVT71512C18TA-5
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Ordering Code
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-200BGC/
GVT715152C18B-5
BG119
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-166AJC/
GVT715152C18T-6
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-166AC/
GVT71512C18TA-6
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-166BGC/
GVT71512C18B-6
BG119
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1367A-150AJC/
GVT71512C18T-6.7
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-150AC/
GVT71512C18TA-6.7
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1367A-150BGC/
GVT71512C18B-6.7
BG119
119-Lead BGA (14 x 22 x 2.4 mm)
Document #: 38-01011-*B
25
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
26
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4 mm) BG119
51-85115
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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