Cypress CY7C1381C-117AC 18-mb (512k x 36/1m x 18) flow-through sram Datasheet

CY7C1381C
CY7C1383C
18-Mb (512K x 36/1M x 18) Flow-Through SRAM
Functional Description[1]
Features
•
•
•
•
•
Supports 133-MHz bus operations
512K X 36/1M X 18 common I/O
3.3V –5% and +10% core power supply (VDD)
2.5V or 3.3V I/O supply (VDDQ)
Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
•
•
•
•
•
•
•
•
— 8.5 ns (100-MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Offered in JEDEC-standard 100-pin TQFP ,119-ball BGA
and 165-ball fBGA packages
JTAG boundary scan for BGA and fBGA packages
“ZZ” Sleep Mode option
The CY7C1381C/CY7C1383C is a 3.3V, 512K x 36 and 1M x
18 Synchronous Flowthrough SRAMs, respectively designed
to interface with high-speed microprocessors with minimum
glue logic. Maximum access delay from clock rise is 6.5 ns
(133-MHz version). A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
The CY7C1381C/CY7C1383C allows either interleaved or
linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be
initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement
(ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1381C/CY7C1383C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz
117 MHz
100 MHz
Unit
Maximum Access Time
6.5
7.5
8.5
ns
Maximum Operating Current
210
190
175
mA
Maximum CMOS Standby Current
70
70
70
mA
1
2
3
4
5
6
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE3, CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.
Cypress Semiconductor Corporation
Document #: 38-05238 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 26, 2004
CY7C1381C
CY7C1383C
7
Logic Block Diagram – CY7C1381C (512K x 36)
ADDRESS
REGISTER
A0, A1, A
A[1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADV
CLK
ADSC
ADSP
DQD, DQPD
DQD, DQPD
BWD
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
ADDRESS
DQBREGISTER
, DQPB
A0, A1, A
BWB
A1
D1
A0
D0
BYTE
MODE
CLK
DQC, DQPC
DQC, DQPC
BWC
WRITE REGISTER
CE
C
ADV/LD
C
DQA, DQPA
BW
A
CEN
BYTE
BWE
BURST
LOGIC
DQB, DQPB
Q1 A1' BYTE
A0'
Q0 WRITE REGISTER
MEMORY
ARRAY
DQPC
DQA, DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
CE2
CE3
OE
ADV/LD
SLEEP
CONTROL
BWA
8
BWB
Logic Block Diagram –
WE
WRITE REGISTRY
AND DATA COHERENCY
CY7C1383C
(1MLOGIC
x 18)
CONTROL
MEMORY
ARRAY
D
A
T
A
S
E
N
S
E
S
T
E
E
R
I
N
G
A
M
P
S
A[1:0]
BURST Q1
COUNTER AND
LOGIC
READ
CLR LOGICQ0
ADV
CLK
ADSP
WRITE
DRIVERS
ADDRESS
REGISTER
MODE
ADSC
DQPB
DQPD
ADDRESS
REGISTER
CE1
A0,A1,A
DQs
DQPA
WRITE REGISTER WRITE
GW
ZZ
OUTPUT
BUFFERS
SENSE
AMPS
OE
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
BWB
DQB,DQPB
WRITE REGISTER
BWA
DQA,DQPA
WRITE REGISTER
O
U
T
P
U
T
INPUT
REGISTERS
B
U
F
F
E
R
S
DQs
DQPA
DQPB
E
INPUT E
REGISTER
DQB,DQPB
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
DQA,DQPA
WRITE DRIVER
BWE
GW
CE1
CE2
CE3
ENABLE
REGISTER
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document #: 38-05238 Rev. *B
Page 2 of 36
CY7C1381C
CY7C1383C
Pin Configurations
NC
NC
NC
CY7C1383C
(1M x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 38-05238 Rev. *B
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS/DNU
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1381C
(512K x 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
VSS/DNU
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-pin TQFP Pinout
Page 3 of 36
CY7C1381C
CY7C1383C
Pin Configurations (continued)
119-ball BGA (1 Chip Enable with JTAG)
1
CY7C1381C (512K x 36)
3
4
5
A
A
ADSP
A
VDDQ
2
A
B
C
NC
NC
A
A
A
A
ADSC
VDD
A
A
A
A
NC
NC
D
E
DQC
DQC
DQPC
DQC
VSS
VSS
NC
CE1
VSS
VSS
DQPB
DQB
DQB
DQB
F
VDDQ
DQC
VSS
OE
VSS
DQB
VDDQ
G
H
J
K
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQD
BWC
VSS
NC
VSS
ADV
BWB
VSS
NC
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
BWA
VSS
DQA
DQA
DQA
VDDQ
VSS
DQA
DQA
GW
VDD
CLK
NC
6
A
7
VDDQ
L
DQD
DQD
M
VDDQ
DQD
BWD
VSS
N
DQD
DQD
VSS
BWE
A1
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
NC
A
MODE
VDD
NC
A
NC
T
U
NC
VDDQ
NC
TMS
A
TDI
A
TCK
A
TDO
NC
NC
ZZ
VDDQ
3
4
5
6
7
A
ADSP
A
A
VDDQ
ADSC
VDD
A
A
A
NC
A
CY7C1383C (1M x 18)
1
2
A
VDDQ
A
B
NC
A
A
C
NC
A
A
D
DQB
NC
VSS
NC
VSS
DQPA
NC
E
NC
DQB
VSS
CE1
VSS
NC
DQA
OE
ADV
VSS
DQA
VDDQ
VSS
VSS
NC
DQA
VDD
DQA
NC
VDDQ
NC
DQA
BWA
VSS
DQA
NC
NC
VDDQ
NC
F
VDDQ
NC
VSS
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
BWB
VSS
NC
K
NC
DQB
VSS
L
M
DQB
VDDQ
NC
DQB
VSS
VSS
N
DQB
NC
VSS
BWE
A1
VSS
DQA
NC
P
NC
DQPB
VSS
A0
VSS
NC
DQA
R
T
U
NC
NC
VDDQ
A
A
TMS
MODE
A
TDI
VDD
NC
TCK
NC
A
TDO
A
A
NC
NC
ZZ
VDDQ
Document #: 38-05238 Rev. *B
GW
VDD
CLK
NC
NC
VSS
Page 4 of 36
CY7C1381C
CY7C1383C
Pin Configurations (continued)
165-ball fBGA (3 Chip Enable)
CY7C1381C (512K x 36)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC / 288M
A
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
R
NC
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC / 144M
DQPC
DQC
NC
DQC
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VSS
VDD
VDDQ
NC
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
DQB
DQC
NC
DQD
DQC
VSS
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC / 72M
A
A
TDI
A
A1
VSS
NC
TDO
A
A
A
A
MODE
NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
CY7C1383C (1M x 18)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC / 288M
A
CE1
BWB
NC
CE3
BWE
ADSC
ADV
A
A
NC
A
CE2
NC
BWA
CLK
GW
OE
ADSP
A
NC
NC
NC
DQB
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
VSS
DQB
DQB
VSS
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
NC / 72M
A
A
TDI
A1
TDO
A
A
A
A
R
MODE
NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
Document #: 38-05238 Rev. *B
NC / 144M
DQPA
DQA
Page 5 of 36
CY7C1381C
CY7C1383C
CY7C1381C–Pin Definitions
TQFP
(3-Chip
Enable)
BGA
(1-Chip
Enable)
fBGA
(3-Chip
Enable)
A0, A1 , A
37,36,32,33,34,
35,42,43,44,45,
46,47,48,49,50,
81,82,99,100
P4,N4,A2,B2,C2
,R2,A3,B3,C3,T
3,T4,A5,B5,C5,
T5,A6,B6,C6,R6
R6,P6,A2,A10,
B2,B10,N6,P3,
P4,P8,P9,P10,
P11,R3,R4,R8,
R9,R10,R11
InputAddress Inputs used to select one of the
Synchronous 512K address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is
active LOW, and CE1, CE2, and CE3[2] are
sampled active. A[1:0] feed the 2-bit counter.
BWA,BWB
93,94,95,96
L5,G5,G3,L3
B5,A5,A4,B4
InputByte Write Select Inputs, active LOW.
Synchronous Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of
CLK.
GW
88
H4
B7
InputGlobal Write Enable Input, active LOW.
Synchronous When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on
BW[A:D]and BWE).
CLK
89
K4
B6
98
E4
A3
InputChip Enable 1 Input, active LOW. Sampled
Synchronous on the rising edge of CLK. Used in
conjunction with CE2 and CE3[2] to
select/deselect the device. ADSP is ignored
if CE1 is HIGH.
CE2
97
-
B3
InputChip Enable 2 Input, active HIGH.
Synchronous Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3[2] to
select/deselect the device.
CE3[2]
92
-
A6
InputChip Enable 3 Input, active LOW. Sampled
Synchronous on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to
select/deselect the device.
OE
86
F4
B8
InputOutput Enable, asynchronous input,
Asynchronous active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins
are tri-stated, and act as input data pins. OE
is masked during the first clock of a read
cycle when emerging from a deselected
state.
ADV
83
G4
A9
InputAdvance Input signal, sampled on the
Synchronous rising edge of CLK. When asserted, it
automatically increments the address in a
burst cycle.
ADSP
84
A4
B9
InputAddress Strobe from Processor, sampled
Synchronous on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented
to the device are captured in the address
registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH
Name
BWC,BWD
CE1
Document #: 38-05238 Rev. *B
I/O
InputClock
Description
Clock Input. Used to capture all
synchronous inputs to the device. Also used
to increment the burst counter when ADV is
asserted LOW, during a burst operation.
Page 6 of 36
CY7C1381C
CY7C1383C
CY7C1381C–Pin Definitions (continued)
Name
ADSC
BWE
ZZ
DQs
DQP[A:D]
MODE
VDD
TQFP
(3-Chip
Enable)
BGA
(1-Chip
Enable)
fBGA
(3-Chip
Enable)
85
B4
A8
InputAddress Strobe from Controller, sampled
Synchronous on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented
to the device are captured in the address
registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
87
M4
A7
InputByte Write Enable Input, active LOW.
Synchronous Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
byte write.
64
T7
H11
InputZZ “sleep” Input, active HIGH. When
Asynchronous asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
52,53,56,57,58,
59,62,63,68,69,
72,73,74,75,78,
79,2,3,6,7,8,9,
12,13,18,19,22,
23,24,25,28,29
K6,L6,M6,N6,K7 M11,L11,K11,
J11,J10,K10,
,L7,N7,P7,E6,F
6,G6,H6,D7,E7, L10,M10,D10,
G7,H7,D1,E1,G E10,F10,G10,
1,H1,E2,F2,G2, D11,E11,F11,
G11,D1,E1,
H2,K1,L1,N1,P1
F1,G1,D2,E2,
,K2,L2,M2,N2
F2,G2,J1,K1,
L1,M1,J2,
K2,L2,M2,
51,80,1,30
P6,D6,D2,P2
N11,C11,C1,N1
31
R3
R1
15,41,65,91
J2,C4,J4,R4,J6
D4,D8,E4,
E8,F4,F8,
G4,G8,H4,
H8,J4,J8,
K4,K8,L4,
L8,M4,M8
Document #: 38-05238 Rev. *B
I/O
Description
I/OBidirectional Data I/O lines. As inputs, they
Synchronous feed into an on-chip data register that is
triggered by the rising edge of CLK. As
outputs, they deliver the data contained in
the memory location specified by the
addresses presented during the previous
clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP[A:D] are placed
in a tri-state condition.The outputs are
automatically tri-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE.
I/OBidirectional Data Parity I/O Lines.
Synchronous Functionally, these signals are identical to
DQs. During write sequences, DQP[A:D] is
controlled by BW[A:D] correspondingly.
Input-Static
Selects Burst Order. When tied to GND
selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
Power Supply Power supply inputs to the core of the
device.
Page 7 of 36
CY7C1381C
CY7C1383C
CY7C1381C–Pin Definitions (continued)
TQFP
(3-Chip
Enable)
BGA
(1-Chip
Enable)
fBGA
(3-Chip
Enable)
VDDQ
4,11,20,27,
54,61,70,77
A1,F1,J1,M1,U1
,
A7,F7,J7,M7,U7
C3,C9,D3,
D9,E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
I/O Power
Supply
Power supply for the I/O circuitry.
VSS
17,40,67,90
H2,D3,E3,F3,H3
,K3,
M3,N3,
P3,D5,E5,F5,H5
,K5,
M5,N5,P5
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
E6,E7,F5,
F6,F7,G5,
G6,G7,H5,
H6,H7,J5,
J6,J7,K5,K6,K7,
L5,L6,L7,M5,M6
,M7,N4,N8
Ground
Ground for the core of the device.
VSSQ
5,10,21,26,
55,60,71,76
-
-
I/O Ground
TDO
-
U5
P7
TDI
-
U3
P5
JTAG serial Serial data-In to the JTAG circuit. Sampled
input
on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be left
floating or connected to VDD through a pull
up resistor. This pin is not available on TQFP
packages.
TMS
-
U2
R5
JTAG serial Serial data-In to the JTAG circuit. Sampled
on the rising edge of TCK. If the JTAG feature
input
Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
-
U4
R7
JTAG-Clock
NC
16,38,39,66
Name
VSS/DNU
14
Document #: 38-05238 Rev. *B
B1,C1,R1,T1,T2
A1,A11,B1,
,J3,D4,L4,J5,R5 B11,C2,C10,H1,
,T6,U6,B7,C7,R
H3,H9,
7
H10,N2,N5,N7,
N10,P1,P2,R2
-
-
I/O
JTAG serial
output
Synchronous
-
Description
Ground for the I/O circuitry.
Serial data-out to the JTAG circuit.
Delivers data on the negative edge of TCK.
If the JTAG feature is not being utilized, this
pin should be left unconnected. This pin is
not available on TQFP packages.
Clock input to the JTAG circuitry. If the
JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not
available on TQFP packages.
No Connects. Not internally connected to
the die. 18M, 36M, 72M, 144M and 288M are
address expansion pins are not internally
connected to the die.
Ground/DNU This pin can be connected to Ground or
should be left floating.
Page 8 of 36
CY7C1381C
CY7C1383C
CY7C1383C:Pin Definitions
TQFP
(3-Chip
Enable)
BGA
(1-Chip
Enable)
fBGA
(3-Chip
Enable)
A0, A1 , A
37,36,32,33,34,
35,42,43,44,45,
46,47,48,49,50,
80,81,82,99,100
P4,N4,A2,B2,
C2,R2,T2,A3,
B3,C3,T3,A5,
B5,C5,T5,A6,
B6,C6,R6,T6
BWA,BWB
93,94
GW
Name
I/O
Description
R6,P6,A2,
A10,A11,B2,
B10,N6,P3,P4,
P8,P9,P10,
P11,R3,R4,
R8,R9,R10,R11
InputSynchronous
Address Inputs used to select one of the
1M address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is
active LOW, and CE1, CE2, and CE3[2] are
sampled active. A[1:0] feed the 2-bit counter.
L5,G3
B5,A4
InputSynchronous
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of
CLK.
88
H4
B7
InputSynchronous
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on
BW[A:B] and BWE).
BWE
87
M4
A7
InputSynchronous
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
byte write.
CLK
89
K4
B6
InputClock
Clock Input. Used to capture all
synchronous inputs to the device. Also used
to increment the burst counter when ADV is
asserted LOW, during a burst operation.
98
E4
A3
InputSynchronous
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3[2] to
select/deselect the device. ADSP is ignored
if CE1 is HIGH.
CE2
97
-
B3
InputSynchronous
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3[2] to
select/deselect the device.
CE3[2]
92
-
A6
InputSynchronous
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to
select/deselect the device.
OE
86
F4
B8
InputOutput Enable, asynchronous input,
Asynchronous active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins
are tri-stated, and act as input data pins. OE
is masked during the first clock of a read
cycle when emerging from a deselected
state.
ADV
83
G4
A9
InputSynchronous
CE1
Document #: 38-05238 Rev. *B
Advance Input signal, sampled on the
rising edge of CLK. When asserted, it
automatically increments the address in a
burst cycle.
Page 9 of 36
CY7C1381C
CY7C1383C
CY7C1383C:Pin Definitions (continued)
TQFP
(3-Chip
Enable)
BGA
(1-Chip
Enable)
fBGA
(3-Chip
Enable)
ADSP
84
A4
ADSC
85
ZZ
64
Name
DQs
DQP[A:B]
MODE
I/O
Description
B9
InputSynchronous
Address Strobe from Processor,
sampled on the rising edge of CLK,
active LOW. When asserted LOW,
addresses presented to the device are
captured in the address registers. A[1:0] are
also loaded into the burst counter. When
ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when
CE1 is deasserted HIGH
B4
A8
InputSynchronous
Address Strobe from Controller,
sampled on the rising edge of CLK,
active LOW. When asserted LOW,
addresses presented to the device are
captured in the address registers. A[1:0] are
also loaded into the burst counter. When
ADSP and ADSC are both asserted, only
ADSP is recognized.
T7
H11
InputZZ “sleep” Input, active HIGH. When
Asynchronous asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
58,59,62,63,68, P7,K7,G7,E7,F6
J10,K10,
69,72,73,8,9,12, ,H6,L6,N6,D1,H
L10,M10,
13,
1,L1,N1,E2,G2,
D11,E11,
18,19,22,23
K2,M2
F11,G11,J1,K1,
L1,M1,
D2,E2,F2,
G2
I/OSynchronous
Bidirectional Data I/O lines. As inputs,
they feed into an on-chip data register that
is triggered by the rising edge of CLK. As
outputs, they deliver the data contained in
the memory location specified by the
addresses presented during the previous
clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP[A:B] are placed
in a tri-state condition.The outputs are
automatically tri-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE.
74,24
D6,P2
C11,N1
I/OSynchronous
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to
DQs. During write sequences, DQP[A:B] is
controlled by BW[A:B] correspondingly.
31
R3
R1
Input-Static
Selects Burst Order. When tied to GND
selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
Document #: 38-05238 Rev. *B
Page 10 of 36
CY7C1381C
CY7C1383C
CY7C1383C:Pin Definitions (continued)
TQFP
(3-Chip
Enable)
BGA
(1-Chip
Enable)
fBGA
(3-Chip
Enable)
VDD
15,41,65,91
C4,J2,J4,J6,R4
D4,D8,E4,
E8,F4,F8,
G4,G8,
H4,H8,J4,
J8,K4,K8,
L4,L8,M4,
M8
VDDQ
4,11,20,27,
54,61,70,77
A1,A7,F1,F7,J1,
J7,M1,M7,U1,U
7
C3,C9,D3,
D9,E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
I/O Power
Supply
Power supply for the I/O circuitry.
VSS
17,40,67,90
D3,D5,E3,E5,F3
,F5,G5,H3,
H5,K3,K5,L3,M3
,
M5,N3,
N5,P3,P5
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
E6,E7,F5,
F6,F7,G5,
G6,G7,H1,
H2,H5,H6,
H7,J5,J6,J7,K5,
K6,K7,L5,L6,L7,
M5,
M6,M7,N4,
N8
Ground
Ground for the core of the device.
VSSQ
5,10,21,26,
55,60,71,76,
-
-
I/O Ground
TDO
-
U5
P7
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit.
Delivers data on the negative edge of TCK.
If the JTAG feature is not being utilized, this
pin should be left unconnected. This pin is
not available on TQFP packages.
TDI
-
U3
P5
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit.
Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin
can be left floating or connected to VDD
through a pull up resistor. This pin is not
available on TQFP packages.
TMS
-
U2
R5
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit.
Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin
can be disconnected or connected to VDD.
This pin is not available on TQFP packages.
TCK
-
U4
R7
JTAG-Clock
Clock input to the JTAG circuitry. If the
JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not
available on TQFP packages.
Name
Document #: 38-05238 Rev. *B
I/O
Description
Power Supply Power supply inputs to the core of the
device.
Ground for the I/O circuitry.
Page 11 of 36
CY7C1381C
CY7C1383C
CY7C1383C:Pin Definitions (continued)
Name
NC
VSS/DNU
TQFP
(3-Chip
Enable)
BGA
(1-Chip
Enable)
fBGA
(3-Chip
Enable)
1,2,3,6,7,16,25,
28,29,30,38,39,
51,52,53,56,57,
66,75,78,79,95,
96
B1,B7,C1,C7,D
2,D4,D7,E1,E6,
H2,F2,G1,G6,H
7,J3,J5,K1,K6,L
4,L2,L7,M6,N2,
N7,L7,P1,P6,R1
,R5,R7,T1,T4,U
6
14
-
Document #: 38-05238 Rev. *B
I/O
Description
A1,A5,B1,
B4,B11,C1,C2,C
10,D1,D10,E1,E
10,F1,F10,G1,G
10,H3,H9,H10,J
2,J11,K2,K11,
L2,L11,M2,M11,
N2,N5,N7,N10,
N11,P1,P2,R2
-
No Connects. Not internally connected to
the die. 36M, 72M, 144M and 288M are
address expansion pins are not internally
connected to the die.
-
Ground/DNU
This pin can be connected to Ground or
should be left floating.
Page 12 of 36
CY7C1381C
CY7C1383C
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t C0) is 6.5 ns (133-MHz device).
The CY7C1381C/CY7C1383C supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium® and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
rise. ADSP is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3[2] are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BWX)are ignored during this first clock
cycle. If the write inputs are asserted active ( see Write Cycle
Descriptions table for appropriate states that indicate a write)
on the next clock rise,the appropriate data will be latched and
written into the device.Byte writes are allowed. All I/Os are
tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
Document #: 38-05238 Rev. *B
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[A:D] will be
written into the specified address location. Byte writes are
allowed. All I/Os are tri-stated when a write is detected, even
a byte write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be tri-stated prior to the presentation of data to DQs.
As a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1381C/CY7C1383C provides an on-chip two-bit
wraparound burst counter inside the SRAM. The burst counter
is fed by A[1:0], and can follow either a linear or interleaved
burst order. The burst order is determined by the state of the
MODE input. A LOW on MODE will select a linear burst
sequence. A HIGH on MODE will select an interleaved burst
order. Leaving MODE unconnected will cause the device to
default to a interleaved burst sequence.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1: A0
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Page 13 of 36
CY7C1381C
CY7C1383C
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3[2], ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Test Conditions
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to snooze current
ZZ Inactive to exit snooze current
Min.
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Max.
Unit
60
2tCYC
mA
ns
ns
ns
ns
2tCYC
2tCYC
0
Truth Table[ 3, 4, 5, 6, 7]
Cycle Description
Deselected Cycle,
Power-down
ADDRESS
Used
CE1 CE2 CE3 ZZ
None
H
X
X
L
ADSP
ADSC
ADV WRITE
OE
CLK
DQ
X
L
X
X
X
L-H Tri-State
Deselected Cycle,
Power-down
None
L
L
X
L
L
X
X
X
X
L-H Tri-State
Deselected Cycle,
Power-down
None
L
X
H
L
L
X
X
X
X
L-H Tri-State
Deselected Cycle,
Power-down
None
L
L
X
L
H
L
X
X
X
L-H Tri-State
Deselected Cycle,
Power-down
None
X
X
X
L
H
L
X
X
X
L-H Tri-State
Snooze Mode, Power-down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
External
External
External
External
External
Next
Next
L
L
L
L
L
X
X
H
H
H
H
H
X
X
L
L
L
L
L
X
X
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
L
L
L
H
H
X
X
X
X
X
L
L
X
X
L
H
H
H
H
L
H
X
L
H
L
H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Q
Tri-State
D
Q
Tri-State
Q
Tri-State
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Notes:
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H..
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
9
Document #: 38-05238 Rev. *B
Page 14 of 36
CY7C1381C
CY7C1383C
Truth Table[ 3, 4, 5, 6, 7]
Cycle Description
ADDRESS
Used
CE1 CE2 CE3 ZZ
ADSP
ADSC
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
ADV WRITE
L
H
OE
L
CLK
L-H Q
DQ
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H D
Partial Truth Table for Read/Write[3, 8]
Function (CY7C1381C)
Read
GW
H
BWE
H
BWD
X
BWC
X
BWB
X
BWA
X
Read
H
L
H
H
H
H
Write Byte A (DQA, DQPA)
H
L
H
H
H
L
Write Byte B(DQB, DQPB)
H
L
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
H
L
H
H
L
L
Write Byte C (DQC, DQPC)
H
L
H
L
H
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC,
DQPB, DQPA)
H
L
H
L
L
L
Write Byte D (DQD, DQPD)
H
L
L
H
H
H
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes D, B, A (DQD, DQB, DQA, DQPD,
DQPB, DQPA)
H
L
L
H
L
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes D, B, A (DQD, DQC, DQA, DQPD,
DQPC, DQPA)
H
L
L
L
H
L
Write Bytes D, C, A ( DQD, DQB, DQA, DQPD,
DQPB, DQPA)
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Note:
8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
Truth Table for Read/Write[3]
Function (CY7C1383C)
Read
GW
H
BWE
H
BWB
X
BWA
X
Read
H
L
H
H
Write Byte A - ( DQA and DQPA)
H
L
H
L
Write Byte B - ( DQB and DQPB)
H
L
L
H
Write All Bytes
H
L
L
L
Document #: 38-05238 Rev. *B
Page 15 of 36
CY7C1381C
CY7C1383C
Truth Table for Read/Write[3]
Function (CY7C1383C)
Write All Bytes
Document #: 38-05238 Rev. *B
GW
L
BWE
X
BWB
X
BWA
X
Page 16 of 36
CY7C1381C
CY7C1383C
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test MODE SELECT (TMS)
The CY7C1381C/CY7C1383C incorporates a serial boundary
scan test access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the set of
functions required for full 1149.1 compliance. These functions
from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of
the SRAM. Note that the TAP controller functions in a manner
that does not conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
The CY7C1381C/CY7C1383C contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
1
0
Bypass Register
TEST-LOGIC
RESET
2 1 0
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
CAPTURE-DR
0
TDO
x . . . . . 2 1 0
SHIFT-IR
0
Boundary Scan Register
1
EXIT1-DR
1
EXIT1-IR
0
1
TCK
0
PAUSE-DR
0
PAUSE-IR
1
0
TMS
TAP CONTROLLER
1
EXIT2-DR
0
EXIT2-IR
1
Performing a TAP Reset
1
UPDATE-DR
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05238 Rev. *B
Selection
Circuitry
Identification Register
CAPTURE-IR
1
Instruction Register
31 30 29 . . . 2 1 0
0
SHIFT-DR
1
TDI
Selection
Circuitry
0
0
0
1
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Page 17 of 36
CY7C1381C
CY7C1383C
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
Boundary Scan Register
IDCODE
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The x36 configuration has a
70-bit-long register and the x18 configuration has a 51-bit long
register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Document #: 38-05238 Rev. *B
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (tCS plus tCH).
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
Page 18 of 36
CY7C1381C
CY7C1383C
BYPASS
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
Test Clock
(TCK)
3
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the operating Range[9, 10]
Parameter
Clock
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
Output Times
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
Setup Times
TMS Set-Up to TCK Clock Rise
TDI Set-Up to TCK Clock Rise
Capture Set-Up to TCK Rise
Hold Times
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
Symbol
Min
tTCYC
tTF
tTH
tTL
100
Max
10
40
40
20
Units
ns
MHz
ns
ns
ns
ns
tTDOV
tTDOX
0
tTMSS
tTDIS
tCS
10
10
10
ns
ns
tTMSH
tTDIH
tCH
10
10
10
ns
ns
ns
Notes:
9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1ns
Document #: 38-05238 Rev. *B
Page 19 of 36
CY7C1381C
CY7C1383C
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ........ ........................................VSS to 3.3V
Input pulse levels...............................................VSS to 2.5V
Input rise and fall times ...................... ..............................1ns
Input rise and fall time ......................................................1ns
Input timing reference levels ...........................................1.5V
Input timing reference levels................... ......................1.25V
Output reference levels...................................................1.5V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage...............................1.5V
Test load termination supply voltage .................... ........1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
TDO
50Ω
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; Vdd = 3.3V ±0.165V unless otherwise noted)[11]
PARAMETER
DESCRIPTION
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
CONDITIONS
MIN
Output HIGH Voltage IOH = -4.0 mA
VDDQ = 3.3V
2.4
V
IOH = -1.0 mA
VDDQ = 2.5V
2.0
V
Output HIGH Voltage IOH = -100 µA
VDDQ = 3.3V
2.9
V
VDDQ = 2.5V
2.1
V
Output LOW Voltage
Output LOW Voltage
DESCRIPTION
UNITS
IOL = 8.0 mA
VDDQ = 3.3V
0.4
V
IOL = 8.0 mA
VDDQ = 2.5V
0.4
V
IOL = 100 µA
VDDQ = 3.3V
0.2
V
VDDQ = 2.5V
0.2
V
Input HIGH Voltage
Input LOW Voltage
Input Load Current
MAX
GND < VIN < VDDQ
VDDQ = 3.3V
2.0
VDD + 0.3
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 3.3V
-0.3
0.8
V
VDDQ = 2.5V
-0.3
0.7
V
-5
5
µA
Note:
11. All voltages referenced to VSS (GND).
Document #: 38-05238 Rev. *B
Page 20 of 36
CY7C1381C
CY7C1383C
Identification Register Definitions
CY7C1381C
(512KX36)
CY7C1383C
(1MX18)
010
010
Device Depth (28:24)
01010
01010
Reserved for Internal Use
Device Width (23:18)
000001
000001
Defines memory type and architecture
Cypress Device ID (17:12)
100101
010101
Defines width and density
00000110100
00000110100
1
1
INSTRUCTION FIELD
Revision Number (31:29)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
DESCRIPTION
Describes the version number.
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
REGISTER NAME
BIT SIZE(X36)
BIT SIZE(X18)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order
72
72
Identification Codes
INSTRUCTION
CODE
DESCRIPTION
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operations.
Document #: 38-05238 Rev. *B
Page 21 of 36
CY7C1381C
CY7C1383C
119-Ball BGA Boundary Scan Order
CY7C1381C (512K x 36)
BIT
#
BALL ID
BIT
#
BALL ID
1
K4
37
B2
2
H4
38
P4
3
M4
39
N4
4
F4
40
R6
5
B4
41
T5
6
A4
42
T3
7
G4
43
R2
8
C6
44
R3
9
A6
45
P2
10
D6
46
P1
11
D7
47
N2
12
E6
48
L2
13
G6
49
K1
14
H7
50
N1
15
E7
51
M2
16
F6
52
L1
17
G7
53
K2
18
H6
54
Not Bonded (Preset to 0)
19
T7
55
H1
20
K7
56
G2
21
L6
57
E2
22
N6
58
D1
23
P7
59
H2
24
K6
60
G1
25
L7
61
F2
26
M6
62
E1
27
N7
63
D2
28
P6
64
A5
29
B5
65
A3
30
B3
66
E4
31
C5
67
Internal
32
C3
68
L3
33
C2
69
G3
34
A2
70
G5
35
T4
71
L5
36
B6
72
Internal
Document #: 38-05238 Rev. *B
Page 22 of 36
CY7C1381C
CY7C1383C
119-Ball BGA Boundary Scan Order
CY7C1383C (1M x 18)
BIT
#
BALL ID
BIT
#
BALL ID
1
K4
37
B2
2
H4
38
P4
3
M4
39
N4
4
F4
40
R6
5
B4
41
T5
6
A4
42
T3
7
G4
43
R2
8
C6
44
R3
9
A6
45
Not Bonded (Preset to 0)
10
T6
46
Not Bonded (Preset to 0)
11
Not Bonded (Preset to 0)
47
Not Bonded (Preset to 0)
12
Not Bonded (Preset to 0)
48
Not Bonded (Preset to 0)
13
Not Bonded (Preset to 0)
49
P2
14
D6
50
N1
15
E7
51
M2
16
F6
52
L1
17
G7
53
K2
18
H6
54
Internal
19
T7
55
H1
20
K7
56
G2
21
L6
57
E2
22
N6
58
D1
23
P7
59
Not Bonded (Preset to 0)
24
Not Bonded (Preset to 0)
60
Not Bonded (Preset to 0)
25
Not Bonded (Preset to 0)
61
Not Bonded (Preset to 0)
26
Not Bonded (Preset to 0)
62
Not Bonded (Preset to 0)
27
Not Bonded (Preset to 0)
63
Not Bonded (Preset to 0)
28
Not Bonded (Preset to 0)
64
A5
29
B5
65
A3
30
B3
66
E4
31
C5
67
Internal
32
C3
68
Not Bonded (Preset to 0)
33
C2
69
Internal
34
A2
70
G3
35
T2
71
L5
36
B6
72
Internal
Document #: 38-05238 Rev. *B
Page 23 of 36
CY7C1381C
CY7C1383C
165-Ball fBGA Boundary Scan Order
CY7C1381C (512K x 36)
BIT#
BALL ID
BIT#
BALL ID
1
B6
37
N6
2
B7
38
R6
3
A7
39
P6
4
B8
40
R4
5
A8
41
R3
6
B9
42
P4
7
A9
43
P3
8
B10
44
R1
9
A10
45
N1
10
C11
46
L2
11
E10
47
K2
12
F10
48
J2
13
G10
49
M2
14
D10
50
M1
15
D11
51
L1
16
E11
52
K1
17
F11
53
J1
18
G11
54
Not Bonded (Preset to 0)
19
H11
55
G2
20
J10
56
F2
21
K10
57
E2
22
L10
58
D2
23
M10
59
G1
24
J11
60
F1
25
K11
61
E1
26
L11
62
D1
27
M11
63
C1
28
N11
64
A2
29
R11
65
B2
30
R10
66
A3
31
R9
67
B3
32
R8
68
B4
33
P10
69
A4
34
P9
70
A5
35
P8
71
B5
36
P11
72
A6
Document #: 38-05238 Rev. *B
Page 24 of 36
CY7C1381C
CY7C1383C
165-Ball fBGA Boundary Scan Order
CY7C1383C (1M x 18)
BIT#
BALL ID
BIT#
BALL ID
1
B6
37
N6
2
B7
38
R6
3
A7
39
P6
4
B8
40
R4
5
A8
41
R3
6
B9
42
P4
7
A9
43
P3
8
B10
44
R1
9
A10
45
Not Bonded (Preset to 0)
10
A11
46
Not Bonded (Preset to 0)
11
Not Bonded (Preset to 0)
47
Not Bonded (Preset to 0)
12
Not Bonded (Preset to 0)
48
Not Bonded (Preset to 0)
13
Not Bonded (Preset to 0)
49
N1
14
C11
50
M1
15
D11
51
L1
16
E11
52
K1
17
F11
53
J1
18
G11
54
Not Bonded (Preset to 0)
19
H11
55
G2
20
J10
56
F2
21
K10
57
E2
22
L10
58
D2
23
M10
59
Not Bonded (Preset to 0)
24
Not Bonded (Preset to 0)
60
Not Bonded (Preset to 0)
25
Not Bonded (Preset to 0)
61
Not Bonded (Preset to 0)
26
Not Bonded (Preset to 0)
62
Not Bonded (Preset to 0)
27
Not Bonded (Preset to 0)
63
Not Bonded (Preset to 0)
28
Not Bonded (Preset to 0)
64
A2
29
R11
65
B2
30
R10
66
A3
31
R9
67
B3
32
R8
68
Not Bonded (Preset to 0)
33
P10
69
Not Bonded (Preset to 0)
34
P9
70
A4
35
P8
71
B5
36
P11
72
A6
Document #: 38-05238 Rev. *B
Page 25 of 36
CY7C1381C
CY7C1383C
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Ambient
Range
Temperature
VDD
VDDQ
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
to VDD
Industrial
-40°C to +85°C
Electrical Characteristics Over the Operating Range[12, 13]
Parameter
Description
VDD
VDDQ
Power Supply Voltage
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage[12]
VIL
Input LOW Voltage[12]
IX
Input Load
Test Conditions
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
GND ≤ VI ≤ VDDQ
Input Current of MODE Input = VSS
Min.
Max.
Unit
3.135
3.135
2.375
2.4
2.0
3.6
VDD
2.625
V
V
V
V
V
V
V
V
V
V
V
µA
2.0
1.7
–0.3
–0.3
–5
30
Input = VSS
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
IOS
Output Short Circuit
Current
VDD = Max., VOUT = GND
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
µA
µA
–30
Input = VDD
IOZ
µA
–30
Input = VDD
Input Current of ZZ
0.4
0.4
VDD + 0.3V
VDD + 0.3V
0.8
0.7
5
30
µA
5
µA
-300
µA
7.5-ns cycle, 133 MHz
210
mA
8.8-ns cycle, 117 MHz
190
mA
10-ns cycle, 100 MHz
175
mA
–5
7.5-ns cycle, 133 MHz
120
mA
8.8-ns cycle, 117 MHz
110
mA
10-ns cycle, 100 MHz
100
ISB2
Automatic CE
Max. VDD, Device Deselected,
Power-down
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = 0, inputs static
All speeds
70
mA
ISB3
Automatic CE
Max. VDD, Device Deselected,
Power-down
VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = fMAX, inputs switching
7.5-ns cycle, 133 MHz
105
mA
8.8-ns cycle, 117 MHz
100
mA
10-ns cycle, 100 MHz
95
mA
Automatic CE
Power-down
Current—TTL Inputs
All Speeds
80
mA
ISB4
Max. VDD, Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
Notes:
12. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).
13. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD
Document #: 38-05238 Rev. *B
Page 26 of 36
CY7C1381C
CY7C1383C
Thermal Resistance[14]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
TQFP
Package
BGA
Package
fBGA
Package
Unit
31
45
46
°C/W
6
7
3
°C/W
Test conditions follow standard
test methods and procedures
for measuring thermal
impedence, per EIA / JESD51.
Capacitance[14]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
TQFP
Package
BGA
Package
fBGA
Package
Unit
5
8
9
pF
5
8
9
pF
5
8
9
pF
TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 2.5V
Notes:
14. Tested initially and after any design or process change that may affect these parameters
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R = 351Ω
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
≤ 1ns
≤ 1ns
VL = 1.5V
(a)
ALL INPUT PULSES
VDD
(c)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R =1538Ω
VL = 1.25V
(a)
Document #: 38-05238 Rev. *B
ALL INPUT PULSES
VDD
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
≤ 1ns
≤ 1ns
(c)
Page 27 of 36
CY7C1381C
CY7C1383C
Switching Characteristics Over the Operating Range[19, 20]
133 MHz
Parameter
tPOWER
Description
Min.
[15]
VDD(Typical) to the first Access
Max.
117 MHz
Min.
1
1
Max.
100 MHz
Min.
Max.
Unit
1
ms
Clock
tCYC
Clock Cycle Time
7.5
8.5
10
ns
tCH
Clock HIGH
2.1
2.3
2.5
ns
tCL
Clock LOW
2.1
2.3
2.5
ns
Output Times
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
2.0
tCLZ
Clock to
Low-Z[16, 17, 18]
2.0
tCHZ
Clock to High-Z[16, 17, 18]
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
OE LOW to Output
6.5
0
7.5
2.0
2.0
4.0
0
3.2
Low-Z[16, 17, 18]
0
[16, 17, 18]
0
3.4
ns
5.0
ns
3.8
ns
0
4.0
ns
ns
2.0
4.0
0
4.0
OE HIGH to Output High-Z
8.5
2.0
ns
5.0
ns
Setup Times
tAS
Address Set-up Before CLK Rise
1.5
1.5
1.5
ns
tADS
ADSP, ADSC Set-up Before CLK Rise
1.5
1.5
1.5
ns
tADVS
ADV Set-up Before CLK Rise
GW, BWE, BW[A:D] Set-up Before CLK
Rise
1.5
1.5
1.5
ns
tWES
1.5
1.5
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.5
1.5
1.5
ns
tCES
Chip Enable Set-up
1.5
1.5
1.5
ns
Address Hold After CLK Rise
0.5
0.5
0.5
ns
ADSP, ADSC Hold After CLK Rise
GW,BWE, BW[A:D] Hold After CLK Rise
0.5
0.5
0.5
ns
0.5
0.5
0.5
ns
0.5
0.5
ns
tDH
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
0.5
ns
Hold Times
tAH
tADH
tWEH
tADVH
Notes:
15. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD( minimum) initially, before a read or write operation
can be initiated.
16. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
17. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
18. This parameter is sampled and not 100% tested.
19. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05238 Rev. *B
Page 28 of 36
CY7C1381C
CY7C1383C
Timing Diagrams
Read Cycle Timing[21]
tCYC
CLK
t
tADS
t CL
CH
tADH
ADSP
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
t
WES
t
WEH
GW, BWE,BW
X
Deselect Cycle
tCES t CEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t OELZ
tCDV
t CHZ
tDOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
Document #: 38-05238 Rev. *B
Q(A2 + 3)
UNDEFINED
Page 29 of 36
CY7C1381C
CY7C1383C
Timing Diagrams
(continued)
[21, 22]
10
Write Cycle Timing
t CYC
CLK
t
tADS
t
CH
CL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BWX
t
t
WES WEH
GW
tCES
tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
OEHZ
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Document #: 38-05238 Rev. *B
Extended BURST WRITE
UNDEFINED
Page 30 of 36
CY7C1381C
CY7C1383C
Timing Diagrams (continued)
Read/Write Cycle Timing[21, 23, 24]
tCYC
CLK
t
CH
tADS
tADH
tAS
tAH
t
CL
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
t
t
WES WEH
BWE, BWX
tCES
tCEH
CE
ADV
OE
tDS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
tOELZ
D(A3)
tCDV
Q(A2)
Back-to-Back READs
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Note:
21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
23. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
24. GW is HIGH.
25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
26. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05238 Rev. *B
Page 31 of 36
CY7C1381C
CY7C1383C
Timing Diagrams (continued)
ZZ Mode Timing [25, 26]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
(MHz)
133
117
Ordering Code
CY7C1381C-133AC
CY7C1383C-133AC
Package
Name
A101
Part and Package Type
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
CY7C1381C-133BGC
CY7C1383C-133BGC
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
CY7C1381C-133BZC
CY7C1383C-133BZC
BB165A
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
CY7C1381C-117AC
A101
CY7C1383C-117AC
CY7C1381C-117BGC
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
BB165A
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
CY7C1383C-117BGC
CY7C1381C-117BZC
CY7C1383C-117BZC
CY7C1381C-117AI
CY7C1383C-117AI
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
CY7C1381C-117BGI
CY7C1383C-117BGI
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
CY7C1381C-117BZI
CY7C1383C-117BZI
BB165A
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
Document #: 38-05238 Rev. *B
Operating
Range
Commercial
Commercial
Industrial
Page 32 of 36
CY7C1381C
CY7C1383C
Ordering Information
Speed
(MHz)
Package
Name
Ordering Code
100
CY7C1381C-100AC
CY7C1383C-100AC
A101
CY7C1381C-100BGC
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
BB165A
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
CY7C1383C-100BGC
CY7C1381C-100BZC
CY7C1383C-100BZC
CY7C1381C-100AI
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
CY7C1383C-100AI
CY7C1381C-100BGI
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
BB165A
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
CY7C1383C-100BGI
CY7C1381C-100BZI
Operating
Range
Part and Package Type
CY7C1383C-100BZI
Commercial
Industrial
Shaded areas contain advance information.
Please contact your local sales representative for availability of these parts.
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
50
A
0.20 MAX.
1.60 MAX.
STAND-OFF
0.05 MIN.
0.15 MAX.
GAUGE PLANE
0.10
0° MIN.
0.25
0°-7°
SEE DETAIL
51
31
R 0.08 MIN.
0.20 MAX.
12°±1°
(8X)
SEATING PLANE
R 0.08 MIN.
0.20 MAX.
0.60±0.15
0.20 MIN.
1.00 REF.
DETAIL
Document #: 38-05238 Rev. *B
A
51-85050-*A
Page 33 of 36
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1381C
CY7C1383C
Package Diagrams (continued)
51-85115-*B
Document #: 38-05238 Rev. *B
Page 34 of 36
CY7C1381C
CY7C1383C
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05238 Rev. *B
Page 35 of 36
CY7C1381C
CY7C1383C
Document History Page
Document Title: CY7C1381C/CY7C1383C 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
Document Number: 38-05238
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
116278
08/27/02
SKX
New Data Sheet
*A
121541
11/21/02
DSG
Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122
(BB165A) to rev. *C
*B
206081
See ECN
RKF
Final Datasheet
Document #: 38-05238 Rev. *B
Page 36 of 36
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