Cypress CY7C1382C-200BZC 18-mb (512k x 36/1m x 18) pipelined sram Datasheet

CY7C1380C
CY7C1382C
18-Mb (512K x 36/1M x 18) Pipelined SRAM
Functional Description[1]
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 225, 200,166 and
133MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.8 ns (for 225-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 166-MHz device)
— 4.2 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA
and 165-Ball fBGA packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36
and 1,048,576 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3 [2]), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BWX, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1380C/CY7C1382C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
225 MHz
200 MHz
167 MHz
133 MHz
Unit
Maximum Access Time
2.6
2.8
3.0
3.4
4.2
ns
Maximum Operating Current
350
325
300
275
245
mA
Maximum CMOS Standby Current
70
70
70
70
70
mA
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE3 , CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.
Cypress Semiconductor Corporation
Document #: 38-05237 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 26, 2004
CY7C1380C
CY7C1382C
1
Logic Block Diagram – CY7C1380C (512K x 36)
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
ADSC
ADSP
BWD
DQD ,DQPD
BYTE
WRITE REGISTER
DQD ,DQPD
BYTE
WRITE DRIVER
BWC
DQC ,DQPC
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE DRIVER
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
DQA ,DQPA
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
MEMORY
ARRAY
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
2
Logic Block Diagram – CY7C1382C (1M x 18)
A0, A1, A
ADDRESS
REGISTER
2 A[1:0]
MODE
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BWB
DQB,DQPB
WRITE DRIVER
DQB,DQPB
WRITE REGISTER
MEMORY
ARRAY
BWA
DQA,DQPA
WRITE DRIVER
DQA,DQPA
WRITE REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
E
BWE
GW
CE1
CE2
CE3
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document #: 38-05237 Rev. *D
Page 2 of 36
CY7C1380C
CY7C1382C
Pin Configurations
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1382C
(1M x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 38-05237 Rev. *D
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
MODE
A
A
A
A
A1
A0
NC / 72M
NC / 36M
VSS
VDD
CY7C1380C
(512K X 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC / 72M
NC / 36M
VSS
VDD
A
A
A
A
A
A
A
A
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-pin TQFP Pinout
Page 3 of 36
CY7C1380C
CY7C1382C
Pin Configurations (continued)
119-ball BGA (1 Chip Enable with JTAG)
1
CY7C1380C (512K x 36)
3
4
5
A
A
ADSP
A
VDDQ
2
A
B
C
NC
NC
A
A
A
A
ADSC
VDD
A
A
A
A
NC
NC
D
E
DQC
DQC
DQPC
DQC
VSS
VSS
NC
CE1
VSS
VSS
DQPB
DQB
DQB
DQB
F
VDDQ
DQC
VSS
OE
VSS
DQB
VDDQ
G
H
J
K
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQD
BWC
VSS
NC
VSS
ADV
BWB
VSS
NC
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
BWA
VSS
DQA
DQA
DQA
VDDQ
VSS
DQA
DQA
GW
VDD
CLK
NC
6
A
7
VDDQ
L
DQD
DQD
M
VDDQ
DQD
BWD
VSS
N
DQD
DQD
VSS
BWE
A1
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
NC
A
MODE
VDD
NC
A
NC
T
U
NC
VDDQ
NC / 72M
TMS
A
TDI
A
TCK
A
TDO
NC / 36M
NC
ZZ
VDDQ
3
4
5
6
7
A
ADSP
A
A
VDDQ
ADSC
VDD
A
A
NC
A
A
NC
CY7C1382C (512K x 18)
1
2
A
VDDQ
A
B
NC
A
A
C
NC
A
A
D
DQB
NC
VSS
NC
VSS
DQPA
NC
E
NC
DQB
VSS
CE1
VSS
NC
DQA
OE
ADV
VSS
DQA
VDDQ
GW
VDD
VSS
VSS
NC
NC
DQA
VDD
DQA
NC
VDDQ
CLK
VSS
NC
DQA
NC
BWA
VSS
DQA
NC
NC
VDDQ
F
VDDQ
NC
VSS
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
BWB
VSS
NC
K
NC
DQB
VSS
L
M
DQB
VDDQ
NC
DQB
VSS
VSS
N
DQB
NC
VSS
BWE
A1
VSS
DQA
NC
P
NC
DQPB
VSS
A0
VSS
NC
DQA
R
T
U
NC
NC / 72M
VDDQ
A
A
TMS
MODE
A
TDI
VDD
NC / 36M
TCK
NC
A
TDO
A
A
NC
NC
ZZ
VDDQ
Document #: 38-05237 Rev. *D
Page 4 of 36
CY7C1380C
CY7C1382C
Pin Configurations (continued)
165-ball fBGA
CY7C1380C (512K x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC / 288M
R
2
A
3
4
5
6
7
8
9
10
11
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC
A
CE2
BWD
BWA
CLK
GW
A
NC / 144M
NC
DQC
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VSS
VDD
OE
VSS
VDD
ADSP
DQPC
DQC
VDDQ
NC
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
NC
DQD
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
DQB
DQC
VSS
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC / 72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
NC / 36M
A
A
TMS
TCK
A
A
A
A
7
8
9
10
11
A
A0
CY7C1382C (1M x 18)
1
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC / 288M
A
3
4
5
6
NC
CE3
A
CE1
CE2
BWB
NC
NC
BWA
NC
NC
NC
DQB
VDDQ
VSS
VDD
VSS
VDDQ
R
CLK
BWE
GW
ADSC
OE
ADV
ADSP
A
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VSS
VDDQ
NC
NC
A
NC / 144M
DQPA
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
DQB
DQB
VSS
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
NC / 72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
Document #: 38-05237 Rev. *D
Page 5 of 36
CY7C1380C
CY7C1382C
CY7C1380C–Pin Definitions
Name
TQFP
BGA
fBGA
I/O
Description
R6,P6,A2,
InputAddress Inputs used to select one of the
P4,N4,
A10,B2,
Synchronous 256K address locations. Sampled at the rising
A2,B2,
B10,N6,P3,P4,
edge of the CLK if ADSP or ADSC is active
C2,R2,
P8,P9,P10,
LOW, and CE1, CE2, and CE3 [2]are sampled
A3,B3,C3,
T3,T4,A5,B5, P11,R3,R4,R8,
active. A1: A0 are fed to the two-bit counter..
R9,R10,R11
C5,
T5,A6,B6,C6,
R6
A0, A1 , A
37,36,32,
33,34,35,
42,43,44,45,
46,47,48,
49,50,81,
82,99,100
BWA,BWB
93,94,95,
96
L5,G5,
G3,L3
B5,A5,A4,
B4
InputByte Write Select Inputs, active LOW.
Synchronous Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
88
H4
B7
InputGlobal Write Enable Input, active LOW.
Synchronous When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are
written, regardless of the values on BWX and
BWE).
BWE
87
M4
A7
InputByte Write Enable Input, active LOW. SamSynchronous pled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
CLK
89
K4
B6
98
E4
A3
InputChip Enable 1 Input, active LOW. Sampled on
Synchronous the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
ADSP is ignored if CE1 is HIGH.
CE2[2]
97
-
B3
InputChip Enable 2 Input, active HIGH. Sampled
Synchronous on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
CE3[2]
92
-
A6
InputChip Enable 3 Input, active LOW. Sampled on
Synchronous the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.Not
available for AJ package version.Not
connected for BGA. Where referenced, CE3 is
assumed active throughout this document for
BGA.
OE
86
F4
B8
InputOutput Enable, asynchronous input, active
Asynchronous LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during
the first clock of a read cycle when emerging
from a deselected state.
ADV
83
G4
A9
InputAdvance Input signal, sampled on the rising
Synchronous edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
BWC,BWD
CE1
Document #: 38-05237 Rev. *D
InputClock
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW,
during a burst operation.
Page 6 of 36
CY7C1380C
CY7C1382C
CY7C1380C–Pin Definitions (continued)
Name
TQFP
BGA
fBGA
84
A4
B9
InputAddress Strobe from Processor, sampled
Synchronous on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the
device are captured in the address registers.
A1: A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when
CE1 is deasserted HIGH.
ADSC
85
B4
A8
InputAddress Strobe from Controller, sampled on
Synchronous the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the
device are captured in the address registers.
A1: A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only
ADSP is recognized.
ZZ
64
T7
H11
InputZZ “sleep” Input, active HIGH. When
Asynchronous asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,7,8,9,
12,13,18,19,22
,
23,24,25,
28,29,51,
80,1,30
K6,L6,
M6,N6,
K7,L7,
N7,P7,
E6,F6,
G6,H6,
D7,E7,
G7,H7,
D1,E1,
G1,H1,
E2,F2,
G2,H2,
K1,L1,
N1,P1,
K2,L2,
M2,N2,
P6,D6,
D2,P2
M11,L11,
K11,J11,
J10,K10,
L10,M10,
D10,E10,
F10,G10,
D11,E11,
F11,G11,
D1,E1,F1,
G1,D2,E2,F2,
G2,J1,
K1,L1,M1,
J2,K2,L2,
M2,N11,
C11,C1,N1
I/OBidirectional Data I/O lines. As inputs, they
Synchronous feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs,
they deliver the data contained in the memory
location specified by the addresses presented
during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQs and DQPX are
placed in a tri-state condition.
VDD
15,41,65,
91
J2,C4,J4,R4,
J6
VSS
17,40,67,
90
D3,E3,
F3,H3,
K3,M3,
N3,P3,
D5,E5,
F5,H5,
K5,M5,
N5,P5
ADSP
DQs, DQPs
Document #: 38-05237 Rev. *D
I/O
Description
D4,D8,E4,E8, Power Supply Power supply inputs to the core of the deF4,F8,
vice.
G4,G8,H4,H8,
J4,J8,
K4,K8,L4,
L8,M4,M8
C4,C5,C6,C7,
C8,D5,D6,D7,
E5,E6,E7,F5,
F6,F7,G5,G6,
G7,H2,H5,H6,
H7,J5,J6,J7,
K5,K6,K7,
L5,L6,L7,
M5,M6,M7,N4,
N8
Ground
Ground for the core of the device.
Page 7 of 36
CY7C1380C
CY7C1382C
CY7C1380C–Pin Definitions (continued)
Name
TQFP
BGA
fBGA
I/O
VSSQ
5,10,21,26,55,
60,71,
76
-
-
I/O Ground
Ground for the I/O circuitry.
VDDQ
4,11,20,27,54, A1,F1,J1,M1, C3,C9,D3,D9,
61,70,
U1,
E3,E9,F3,F9,G
77
A7,F7,J7,M7,
3,
U7
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,N3,
N9
I/O Power
Supply
Power supply for the I/O circuitry.
MODE
31
R3
R1
TDO
-
U5
P7
TDI
-
U3
P5
JTAG serial Serial data-In to the JTAG circuit. Sampled
input
on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TMS
-
U2
R5
JTAG serial Serial data-In to the JTAG circuit. Sampled
input
on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
-
U4
R7
JTAG-Clock
Clock input to the JTAG circuitry. If the JTAG
feature is not being utilized, this pin must be
connected to VSS. This pin is not available on
TQFP packages.
NC
14,16,66,
39,38
-
No Connects. Not internally connected to the
die
Document #: 38-05237 Rev. *D
A11,B1,C2,C1
B1,C1,
R1,T1,T2,J3, 0,H1,H3,H9,
H10,
D4,
L4,J5,R5,6T, N2,N5,N7,N10
,P1,A1,B11,P2
6U,
,R2,N6
B7,C7,
R7
InputStatic
Description
JTAG serial
output
Synchronous
Selects Burst Order. When tied to GND
selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst
sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an
internal pull-up.
Serial data-out to the JTAG circuit. Delivers
data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin should be
disconnected. This pin is not available on TQFP
packages.
Page 8 of 36
CY7C1380C
CY7C1382C
CY7C1382C:Pin Definitions
Name
TQFP
BGA
A0, A1 , A
37,36,32,
33,34,35,
42,43,44,
45,46,47,
48,49,50,
80,81,82,
99,100
P4,N4,
A2,B2,
C2,R2,
T2,A3,
B3,C3,
T3,A5,
B5,C5,
T5,A6,
B6,C6,
R6,T6
BWA,BWB
93,94
G3,L5
B5,A4
InputByte Write Select Inputs, active LOW. Qualified
Synchronous with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
88
H4
B7
InputGlobal Write Enable Input, active LOW. When
Synchronous asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written,
regardless of the values on BWX and BWE).
BWE
87
M4
A7
InputByte Write Enable Input, active LOW. Sampled
Synchronous on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK
89
K4
B6
98
E4
A3
InputChip Enable 1 Input, active LOW. Sampled on the
Synchronous rising edge of CLK. Used in conjunction with CE2
and CE3 to select/deselect the device. ADSP is
ignored if CE1 is HIGH.
CE2[2]
97
-
B3
InputChip Enable 2 Input, active HIGH. Sampled on
Synchronous the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
CE3 [2]
92
-
A6
InputChip Enable 3 Input, active LOW. Sampled on the
Synchronous rising edge of CLK. Used in conjunction with CE1
and CE2 to select/deselect the device. Not available
for AJ package version.Not connected for BGA.
Where referenced, CE3 is assumed active
throughout this document for BGA.
OE
86
F4
B8
InputOutput Enable, asynchronous input, active
Asynchronous LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected
state.
ADV
83
G4
A9
InputAdvance Input signal, sampled on the rising
Synchronous edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
CE1
Document #: 38-05237 Rev. *D
fBGA
I/O
Description
InputAddress Inputs used to select one of the 512K
R6,P6,A2,
Synchronous address locations. Sampled at the rising edge of
A10,A11,
the CLK if ADSP or ADSC is active LOW, and CE1,
B2,B10,P3,P4,
N6,P8,P9,
CE2, and CE3 are sampled active. A1: A0 are fed
P10,P11,
to the two-bit counter..
R3,R4,R8,R9,
R10,
R11
InputClock
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a
burst operation.
Page 9 of 36
CY7C1380C
CY7C1382C
CY7C1382C:Pin Definitions (continued)
Name
TQFP
BGA
fBGA
84
A4
B9
InputAddress Strobe from Processor, sampled on
Synchronous the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device
are captured in the address registers. A1: A0 are
also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ASDP is ignored when CE1 is deasserted HIGH.
ADSC
85
P4
A8
InputAddress Strobe from Controller, sampled on the
Synchronous rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are
captured in the address registers. A1: A0 are also
loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ
64
T7
H11
InputZZ “sleep” Input, active HIGH. When asserted
Asynchronous HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
ADSP
I/O
Description
DQs,
DQPs
58,59,62,
63,68,69,
72,73,8,9,
12,13,18,
19,22,23,
74,24
I/OBidirectional Data I/O lines. As inputs, they feed
J10,K10,
P7,K7,
Synchronous into an on-chip data register that is triggered by the
L10,M10,
G7,E7,
rising edge of CLK. As outputs, they deliver the data
D11,E11,
F6,H6,L6,N6,
contained in the memory location specified by the
F11,G11,J1,K1
D1,
addresses presented during the previous clock rise
,L1,M1,D2,E2,
H1,L1,
F2,
N1,E2,
of the read cycle. The direction of the pins is
G2,C11,N1
G2,K2,
controlled by OE. When OE is asserted LOW, the
M2,D6,
pins behave as outputs. When HIGH, DQs and
P2
DQPX are placed in a tri-state condition.
VDD
15,41,65,
91
C4,J2,J4,J6,
R4
VSS
17,40,67,
90
H2,C4,C5,C6,
D3,D5,
E5,E3,F3,F5, C7,C8,D5,D6,
D7,E5,E6,E7,
G5,
F5,F6,F7,
H3,H5,
G5,G6,G7,
K3,K5,L3,M3,
H5,H6,H7,J5,J
M5,
6,J7,
N3,N5,
K5,K6,K7,
P3,P5
L5,L6,L7,
M5,M6,M7,N4,
N8
VSSQ
5,10,21,26,55,
60,71,
76
Document #: 38-05237 Rev. *D
-
D4,D8,E4,E8, Power Supply Power supply inputs to the core of the device.
F4,F8,
G4,G8,H4,
H8,J4,J8,
K4,K8,L4,
L8,M4,M8
-
Ground
I/O Ground
Ground for the core of the device.
Ground for the I/O circuitry.
Page 10 of 36
CY7C1380C
CY7C1382C
CY7C1382C:Pin Definitions (continued)
Name
VDDQ
MODE
TQFP
BGA
4,11,20,27,54, A1,A7,F1,F7,
61,70,
J1,J7,M1,M7,
77
U1,U7
fBGA
I/O
Description
C3,C9,D3,D9, I/O Power Sup- Power supply for the I/O circuitry.
ply
E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,N3,
N9
31
R3
R1
TDO
-
U5
P7
TDI
-
U3
P5
JTAG serial Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
input
Synchronous utilized, this pin can be left floating or connected to
VDD through a pull up resistor. This pin is not available on TQFP packages.
TMS
-
U2
R5
JTAG serial Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
input
Synchronous utilized, this pin can be disconnected or connected
to VDD. This pin is not available on TQFP packages.
TCK
-
U4
R7
JTAG-Clock
Clock input to the JTAG circuitry. If the JTAG
feature is not being utilized, this pin must be
connected to VSS. This pin is not available on TQFP
packages.
NC
1,2,3,6,7,
14,16,25,
28,29,30,
38,39,
51,52,53,
56,57,66,
75,78,79,
95,96
B1,B7,
C1,C7,
D2,D4,
D7,E1,
E6,H2,
F2,G1,
G6,H7,
J3,J5,K1,
K6,L4,L2,L7,
M6,
N2,L7,P1,P6,
R1,
R5,R7,
T1,T4,U6
A5,B1,B4,
C1,C2,C10,D1
,D10,
E1,E10,F1,
F10,G1,
G10,H1,H3,H9
,H10,J2,J11,
K2,
K11,L2,L1,M2,
M11,
N2,N10,N5,N7
N11,P1,A1,
B11,
P2,R2
-
No Connects. Not internally connected to the die.
Document #: 38-05237 Rev. *D
InputStatic
JTAG serial
output
Synchronous
Selects Burst Order. When tied to GND selects
linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is
a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.
Serial data-out to the JTAG circuit. Delivers data
on the negative edge of TCK. If the JTAG feature is
not being utilized, this pin should be left unconnected. This pin is not available on TQFP
packages.
Page 11 of 36
CY7C1380C
CY7C1382C
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 3.0ns
(200-MHz device).
The CY7C1380C supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.0 ns (200-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
Document #: 38-05237 Rev. *D
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BWX) and
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BWX
signals. The CY7C1380C provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BWX) input, will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Because the CY7C1380C is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and
(4) the appropriate combination of the Write inputs (GW, BWE,
and BWX) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into
the address register and the address advancement logic while
being delivered to the memory array. The ADV input is ignored
during this cycle. If a global Write is conducted, the data
presented to the DQs is written into the corresponding address
location in the memory core. If a Byte Write is conducted, only
the selected bytes are written. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
Because the CY7C1380C is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1380C provides a two-bit wraparound counter, fed
by A1: A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Page 12 of 36
CY7C1380C
CY7C1382C
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Snooze mode standby current
ZZ > VDD – 0.2V
60mA
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ Active to snooze current
This parameter is sampled
tRZZI
ZZ Inactive to exit snooze current
This parameter is sampled
2tCYC
ns
2tCYC
ns
0
ns
Truth Table[ 3, 4, 5, 6, 7, 8]
Operation
Add. Used
CE2
CE3
X
X
ZZ
L
ADSP
X
ADSC
L
ADV
X
WRITE OE CLK
DQ
X
X L-H Tri-State
Deselect Cycle,Power Down
None
CE1
H
Deselect Cycle,Power Down
None
L
L
X
L
L
X
X
X
X
L-H Tri-State
Deselect Cycle,Power Down
None
L
X
H
L
L
X
X
X
X
L-H Tri-State
Deselect Cycle,Power Down
None
L
L
X
L
H
L
X
X
X
L-H Tri-State
Deselect Cycle,Power Down
None
L
X
H
L
H
L
X
X
X
L-H Tri-State
None
X
X
X
H
X
X
X
X
X
X
Tri-State
External
L
H
L
L
L
X
X
X
L
L-H
Q
Snooze Mode,Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H Tri-State
WRITE Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H Tri-State
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H Tri-State
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Document #: 38-05237 Rev. *D
Q
Q
Page 13 of 36
CY7C1380C
CY7C1382C
Truth Table[ 3, 4, 5, 6, 7, 8]
Operation
Add. Used
CE2
CE3
X
X
ZZ
L
ADSP
X
ADSC
H
ADV
L
X
X
L
H
H
L
READ Cycle, Continue Burst
Next
CE1
H
WRITE Cycle, Continue Burst
Next
X
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
READ Cycle, Suspend Burst
Current
H
X
X
L
X
READ Cycle, Suspend Burst
Current
H
X
X
L
WRITE Cycle,Suspend Burst
Current
X
X
X
L
WRITE Cycle,Suspend Burst
Current
H
X
X
L
X
WRITE OE CLK
DQ
H
H L-H Tri-State
L
X
L-H
D
L
L
X
L-H
D
H
H
L
L-H
Q
H
H
H
L-H Tri-State
H
H
H
L
L-H
X
H
H
H
H
L-H Tri-State
H
H
H
L
X
L-H
D
H
H
L
X
L-H
D
Q
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Truth Table for Read/Write[5]
Function (CY7C1380C)
Read
Read
Write Byte A – ( DQA and DQPA )
Write Byte B – ( DQB and DQPB )
Write Bytes B, A
Write Byte C – ( DQC and DQPC )
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – ( DQD and DQPD )
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
Write All Bytes
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
BWD
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BWC
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
BWB
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
BWA
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
Truth Table for Read/Write[5]
Function (CY7C1382C)
Read
Read
Write Byte A – ( DQA and DQPA )
Write Byte B – ( DQB and DQPB )
Write Bytes B, A
Write All Bytes
Write All Bytes
Document #: 38-05237 Rev. *D
GW
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
X
BWB
X
H
H
L
L
L
X
BWA
X
H
L
H
L
L
X
Page 14 of 36
CY7C1380C
CY7C1382C
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test MODE SELECT (TMS)
The CY7C1380C incorporates a serial boundary scan test
access port (TAP). This port operates in accordance with IEEE
Standard 1149.1-1990 but does not have the set of functions
required for full 1149.1 compliance. These functions from the
IEEE specification are excluded because their inclusion
places an added delay in the critical speed path of the SRAM.
Note that the TAP controller functions in a manner that does
not conflict with the operation of other devices using 1149.1
fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
The CY7C1380C contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID
register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
1
0
Bypass Register
TEST-LOGIC
RESET
2 1 0
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
CAPTURE-DR
0
x . . . . . 2 1 0
SHIFT-IR
1
EXIT1-IR
0
0
Boundary Scan Register
1
TCK
0
PAUSE-DR
0
PAUSE-IR
1
0
TMS
TAP CONTROLLER
1
EXIT2-DR
0
EXIT2-IR
1
Performing a TAP Reset
1
UPDATE-DR
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05237 Rev. *D
TDO
1
EXIT1-DR
Instruction Register
Selection
Circuitry
Identification Register
CAPTURE-IR
1
Instruction Register
31 30 29 . . . 2 1 0
0
SHIFT-DR
1
TDI
Selection
Circuitry
0
0
0
1
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Page 15 of 36
CY7C1380C
CY7C1382C
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The SRAM has a 75-bit-long
register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Identification (ID) Register
SAMPLE/PRELOAD
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
TAP Instruction Set
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
Document #: 38-05237 Rev. *D
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (tCS plus tCH).
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Page 16 of 36
CY7C1380C
CY7C1382C
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
BYPASS
Reserved
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
Test Clock
(TCK)
3
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the operating Range[9, 10]
Parameter
Symbol
Min
100
Max
Units
10
MHz
Clock
TCK Clock Cycle Time
tTCYC
TCK Clock Frequency
tTF
TCK Clock HIGH time
tTH
40
ns
TCK Clock LOW time
tTL
40
ns
ns
Output Times
TCK Clock LOW to TDO Valid
tTDOV
TCK Clock LOW to TDO Invalid
tTDOX
0
ns
TMS Set-Up to TCK Clock Rise
tTMSS
10
ns
TDI Set-Up to TCK Clock Rise
tTDIS
10
ns
tCS
10
TMS hold after TCK Clock Rise
tTMSH
10
ns
TDI Hold after Clock Rise
tTDIH
10
ns
tCH
10
ns
20
ns
Setup Times
Capture Set-Up to TCK Rise
Hold Times
Capture Hold after Clock Rise
Notes:
9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1ns.
Document #: 38-05237 Rev. *D
Page 17 of 36
CY7C1380C
CY7C1382C
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ........ ........................................VSS to 3.3V
Input pulse levels...............................................VSS to 2.5V
Input rise and fall times ...................... ..............................1ns
Input rise and fall time ......................................................1ns
Input timing reference levels ...........................................1.5V
Input timing reference levels................... ......................1.25V
Output reference levels...................................................1.5V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage...............................1.5V
Test load termination supply voltage .................... ........1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; Vdd = 3.3V ±0.165V unless otherwise noted)[11]
PARAMETER
DESCRIPTION
VOH1
Output HIGH Voltage IOH = -4.0 mA,VDDQ = 3.3V
2.4
V
IOH = -1.0 mA,VDDQ = 2.5V
2.0
V
VDDQ = 3.3V
2.9
V
VDDQ = 2.5V
2.1
V
VOH2
VOL1
VOL2
VIH
VIL
IX
TEST CONDITIONS
Output HIGH Voltage IOH = -100 µA
Output LOW Voltage
Output LOW Voltage
IOL = 8.0 mA
IOL = 100 µA
Input HIGH Voltage
Input LOW Voltage
Input Load Current
GND < VIN < VDDQ
MIN
MAX
UNITS
VDDQ = 3.3V
0.4
V
VDDQ = 2.5V
0.4
V
VDDQ = 3.3V
0.2
V
VDDQ = 2.5V
0.2
V
VDDQ = 3.3V
2.0
VDD + 0.3
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 3.3V
-0.3
0.8
V
VDDQ = 2.5V
-0.3
0.7
V
-5
5
µA
Note:
11. All voltages referenced to VSS (GND).
Document #: 38-05237 Rev. *D
Page 18 of 36
CY7C1380C
CY7C1382C
Identification Register Definitions
CY7C1380C
(512KX36)
CY7C1382C
(1MX18)
010
0100
Describes the version number.
Device Depth (28:24)
01010
1010
Reserved for Internal Use
Device Width (23:18)
000000
000000
Defines memory type and architecture
Cypress Device ID (17:12)
100101
010101
Defines width and density
00000110100
00000110100
1
1
INSTRUCTION FIELD
Revision Number (31:29)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
DESCRIPTION
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
REGISTER NAME
BIT SIZE(X36)
BIT SIZE(X18)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order
72
72
Identification Codes
INSTRUCTION
CODE
DESCRIPTION
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operations.
Document #: 38-05237 Rev. *D
Page 19 of 36
CY7C1380C
CY7C1382C
119-Ball BGA Boundary Scan Order
CY7C1380C (512K x 36)
BIT#
BALL ID
BIT#
BALL ID
1
K4
37
B2
2
H4
38
P4
3
M4
39
N4
4
F4
40
R6
5
B4
41
T5
6
A4
42
T3
7
G4
43
R2
8
C6
44
R3
9
A6
45
P2
10
D6
46
P1
11
D7
47
N2
12
E6
48
L2
13
G6
49
K1
14
H7
50
N1
15
E7
51
M2
16
F6
52
L1
17
G7
53
K2
18
H6
54
Not Bonded (Preset to 1)
19
T7
55
H1
20
K7
56
G2
21
L6
57
E2
22
N6
58
D1
23
P7
59
H2
24
K6
60
G1
25
L7
61
F2
26
M6
62
E1
27
N7
63
D2
28
P6
64
A5
29
B5
65
A3
30
B3
66
E4
31
C5
67
Internal
32
C3
68
L3
33
C2
69
G3
34
A2
70
G5
35
T4
71
L5
36
B6
72
Internal
Document #: 38-05237 Rev. *D
Page 20 of 36
CY7C1380C
CY7C1382C
119-Ball BGA Boundary Scan Order
CY7C1382C (1M x 18)
BIT#
BALL ID
BIT#
BALL ID
1
K4
37
B2
2
H4
38
P4
3
M4
39
N4
4
F4
40
R6
5
B4
41
T5
6
A4
42
T3
7
G4
43
R2
8
C6
44
R3
9
A6
45
Not Bonded (Preset to 0)
10
T6
46
Not Bonded (Preset to 0)
11
Not Bonded (Preset to 0)
47
Not Bonded (Preset to 0)
12
Not Bonded (Preset to 0)
48
Not Bonded (Preset to 0)
13
Not Bonded (Preset to 0)
49
P2
14
D6
50
N1
15
E7
51
M2
16
F6
52
L1
17
G7
53
K2
18
H6
54
Not Bonded (Preset to 1)
19
T7
55
H1
20
K7
56
G2
21
L6
57
E2
22
N6
58
D1
23
P7
59
Not Bonded (Preset to 0)
24
Not Bonded (Preset to 0)
60
Not Bonded (Preset to 0)
25
Not Bonded (Preset to 0)
61
Not Bonded (Preset to 0)
26
Not Bonded (Preset to 0)
62
Not Bonded (Preset to 0)
27
Not Bonded (Preset to 0)
63
Not Bonded (Preset to 0)
28
Not Bonded (Preset to 0)
64
A5
29
B5
65
A3
30
B3
66
E4
31
C5
67
Internal
32
C3
68
Not Bonded (Preset to 0)
33
C2
69
Internal
34
A2
70
G3
35
T2
71
L5
36
B6
72
Internal
Document #: 38-05237 Rev. *D
Page 21 of 36
CY7C1380C
CY7C1382C
165-Ball fBGA Boundary Scan Order
CY7C1380C (512K x 36)
BIT#
BALL ID
BIT#
BALL ID
1
B6
37
N6
2
B7
38
R6
3
A7
39
P6
4
B8
40
R4
5
A8
41
R3
6
B9
42
P4
7
A9
43
P3
8
B10
44
R1
9
A10
45
N1
10
C11
46
L2
11
E10
47
K2
12
F10
48
J2
13
G10
49
M2
14
D10
50
M1
15
D11
51
L1
16
E11
52
K1
17
F11
53
J1
18
G11
54
Internal
19
H11
55
G2
20
J10
56
F2
21
K10
57
E2
22
L10
58
D2
23
M10
59
G1
24
J11
60
F1
25
K11
61
E1
26
L11
62
D1
27
M11
63
C1
28
N11
64
A2
29
R11
65
B2
30
R10
66
A3
31
R9
67
B3
32
R8
68
B4
33
P10
69
A4
34
P9
70
A5
35
P8
71
B5
36
P11
72
A6
Document #: 38-05237 Rev. *D
Page 22 of 36
CY7C1380C
CY7C1382C
165-Ball fBGA Boundary Scan Order
CY7C1382C (1M x 18)
BIT#
BALL ID
BIT#
BALL ID
0
B6
36
N6
1
B7
37
R6
2
A7
38
P6
3
B8
39
R4
4
A8
40
R3
5
B9
41
P4
6
A9
42
P3
7
B10
43
R1
8
A10
44
Not Bonded (Preset to 0)
9
A11
45
Not Bonded (Preset to 0)
10
Not Bonded (Preset to 0)
46
Not Bonded (Preset to 0)
11
Not Bonded (Preset to 0)
47
Not Bonded (Preset to 0)
12
Not Bonded (Preset to 0)
48
N1
13
C11
49
M1
14
D11
50
L1
15
E11
51
K1
16
F11
52
J1
17
G11
53
Internal
18
H11
54
G2
19
J10
55
F2
20
K10
56
E2
21
L10
57
D2
22
M10
58
Not Bonded (Preset to 0)
23
Not Bonded (Preset to 0)
59
Not Bonded (Preset to 0)
24
Not Bonded (Preset to 0)
60
Not Bonded (Preset to 0)
25
Not Bonded (Preset to 0)
61
Not Bonded (Preset to 0)
26
Not Bonded (Preset to 0)
62
Not Bonded (Preset to 0)
27
Not Bonded (Preset to 0)
63
A2
28
R11
64
B2
29
R10
65
A3
30
R9
66
B3
31
R8
67
Not Bonded (Preset to 0)
32
P10
68
Not Bonded (Preset to 0)
33
P9
69
A4
34
P8
70
B5
35
P11
71
A6
Document #: 38-05237 Rev. *D
Page 23 of 36
CY7C1380C
CY7C1382C
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Ambient
Range
Temperature
VDD
VDDQ
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
to VDD
Industrial
-40°C to +85°C
Electrical Characteristics Over the Operating Range[12, 13]
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH
Input LOW
Voltage[12]
Voltage[12]
Input Load Current except ZZ and MODE
Test Conditions
Min.
Max.
Unit
3.135
3.6
V
VDDQ = 3.3V
3.135
VDD
V
VDDQ = 2.5V
2.375
2.625
V
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
2.4
V
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
2.0
V
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
0.4
V
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
0.4
V
VDDQ = 3.3V
2.0
VDD + 0.3V
V
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
GND ≤ VI ≤ VDDQ
Input Current of MODE Input = VSS
Input Current of ZZ
5
Input = VSS
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
ISB1
ISB2
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
Automatic CE
VDD = Max, Device Deselected,
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
Document #: 38-05237 Rev. *D
µA
µA
–30
Input = VDD
IOZ
µA
–30
Input = VDD
5
µA
5
µA
4.0-ns cycle, 250 MHz
350
mA
4.4-ns cycle, 225 MHz
325
mA
5.0-ns cycle, 200 MHz
300
mA
6.0-ns cycle, 167 MHz
275
mA
7.5-ns cycle, 133 MHz
245
mA
–5
4.0-ns cycle, 250 MHz
120
mA
4.4-ns cycle, 225 MHz
110
mA
5.0-ns cycle, 200 MHz
100
mA
6.0-ns cycle, 167 MHz
90
mA
7.5-ns cycle, 133 MHz
85
mA
All speeds
70
mA
Page 24 of 36
CY7C1380C
CY7C1382C
Electrical Characteristics Over the Operating Range[12, 13]
Parameter
ISB3
Description
(continued)
Test Conditions
Min.
Max.
Unit
105
mA
100
mA
95
mA
Automatic CE
VDD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V 4.4-ns cycle, 225 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
5.0-ns cycle, 200 MHz
ISB4
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
6.0-ns cycle, 167 MHz
85
mA
7.5-ns cycle, 133 MHz
80
mA
All speeds
80
mA
Shaded areas contain advance information.
Notes:
12. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).
13. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD\
Thermal Resistance[14]
Parameter
ΘJA
ΘJC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard
test methods and procedures
for measuring thermal
impedence, per EIA / JESD51.
TQFP
Package
BGA
Package
fBGA
Package
Unit
31
45
46
°C/W
6
7
3
°C/W
Capacitance[14]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 2.5V
TQFP
Package
BGA
Package
fBGA
Package
Unit
5
8
9
pF
5
8
9
pF
5
8
9
pF
Notes:
14. Tested initially and after any design or process change that may affect these parameters
Document #: 38-05237 Rev. *D
Page 25 of 36
CY7C1380C
CY7C1382C
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
VDD
OUTPUT
RL = 50Ω
Z0 = 50Ω
10%
90%
10%
90%
GND
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
VL = 1.5V
INCLUDING
JIG AND
SCOPE
(a)
(c)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
Z0 = 50Ω
10%
R =1538Ω
VL = 1.25V
Document #: 38-05237 Rev. *D
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
(a)
ALL INPUT PULSES
VDD
OUTPUT
RL = 50Ω
(b)
≤ 1ns
≤ 1ns
(c)
Page 26 of 36
CY7C1380C
CY7C1382C
Switching Characteristics Over the Operating Range[19, 20]
250 MHz
Parameter
tPOWER
Description
225 MHz
200 MHz
Min. Max
[15]
VDD(Typical) to the first Access
167 MHz
133 MHz
Min. Max Min. Max
1
1
1
Unit
1
1
ms
Clock
tCYC
Clock Cycle Time
4.0
4.4
5
6
7.5
ns
tCH
Clock HIGH
1.7
2.0
2.0
2.2
2.5
ns
tCL
Clock LOW
1.7
2.0
2.0
2.2
2.5
ns
Output Times
tCO
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
1.0
tCLZ
Clock to
Low-Z[16, 17, 18]
1.0
tCHZ
Clock to High-Z[16, 17, 18]
tOEV
OE LOW to Output Valid
OE LOW to Output Low-Z[16, 17, 18]
tOELZ
tOEHZ
2.6
2.8
1.0
1.0
2.6
[16, 17, 18]
2.6
OE HIGH to Output High-Z
2.8
3.4
0
3.0
ns
3.4
ns
4.2
ns
0
3.4
ns
ns
1.3
3.4
3.0
0
4.2
1.3
1.3
3.0
2.8
0
3.4
1.3
1.3
2.8
2.6
0
3.0
1.3
ns
4.0
ns
Setup Times
tAS
Address Set-up Before CLK Rise
1.2
1.4
1.4
1.5
1.5
ns
tADS
ADSC, ADSP Set-up Before CLK
Rise
1.2
1.4
1.4
1.5
1.5
ns
tADVS
1.2
1.4
1.4
1.5
1.5
ns
tWES
ADV Set-up Before CLK Rise
GW, BWE, BWX Set-up Before CLK
Rise
1.2
1.4
1.4
1.5
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.2
1.4
1.4
1.5
1.5
ns
tCES
Chip Enable Set-Up Before CLK Rise 1.2
1.4
1.4
1.5
1.5
ns
tAH
Address Hold After CLK Rise
0.3
0.4
0.4
0.5
0.5
ns
tADH
0.3
0.4
0.4
0.5
0.5
ns
0.3
0.4
0.4
0.5
0.5
ns
tWEH
ADSP , ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW,BWE, BWX Hold After CLK Rise
0.3
0.4
0.4
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.3
0.4
0.4
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.3
0.4
0.4
0.5
0.5
ns
Hold Times
tADVH
Shaded areas contain advance information.
Notes:
15. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD( minimum) initially before a read or write operation
can be initiated.
16. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
17. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
18. This parameter is sampled and not 100% tested.
19. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05237 Rev. *D
Page 27 of 36
CY7C1380C
CY7C1382C
Switching Waveforms
Read Cycle Timing[21]
t CYC
CLK
t
CH
t
ADS
t
CL
t
ADH
ADSP
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
tWES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
tCES
Deselect
cycle
tCEH
CE
tADVS tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
Q(A1)
High-Z
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Notes:
21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document #: 38-05237 Rev. *D
Page 28 of 36
CY7C1380C
CY7C1382C
Switching Waveforms (continued)
Write Cycle Timing[21, 22]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BWX
tWES tWEH
GW
tCES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
tDS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Document #: 38-05237 Rev. *D
Extended BURST WRITE
UNDEFINED
Page 29 of 36
CY7C1380C
CY7C1382C
Switching Waveforms (continued)
Read/Write Cycle Timing[21, 23, 24]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE,
BWX
tCES
tCEH
CE
ADV
OE
tDS
tCO
tDH
tOELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Note:
23. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
24. GW is HIGH.
Document #: 38-05237 Rev. *D
Page 30 of 36
CY7C1380C
CY7C1382C
Switching Waveforms (continued)
ZZ Mode Timing [25, 26]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
26. DQs are in high-Z when exiting ZZ sleep mode
Document #: 38-05237 Rev. *D
Page 31 of 36
CY7C1380C
CY7C1382C
Ordering Information
Speed
(MHz)
250
225
Ordering Code
CY7C1380C-250AC
CY7C1382C-250AC
Package
Name
A101
Part and Package Type
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
CY7C1380C-250BGC
CY7C1382C-250BGC
BG119
119 PBGA
CY7C1380C-250BZC
CY7C1382C-250BZC
BB165A
165 fBGA
CY7C1380C-225AC
A101
Operating
Range
Commercial
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
CY7C1382C-225AC
200
CY7C1380C-225BGC
CY7C1382C-225BGC
BG119
119 PBGA
CY7C1380C-225BZC
CY7C1382C-225BZC
BB165A
165 fBGA
CY7C1380C-200AC
CY7C1382C-200AC
CY7C1380C-200BGC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
BG119
119 PBGA
BB165A
165 fBGA
CY7C1382C-200BGC
CY7C1380C-200BZC
CY7C1382C-200BZC
167
CY7C1380C-167AC
CY7C1382C-167AC
CY7C1380C-167BGC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
BG119
119 PBGA
BB165A
165 fBGA
CY7C1382C-167BGC
CY7C1380C-167BZC
CY7C1382C-167BZC
133
CY7C1380C-133AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
167
CY7C1380C-167AI
CY7C1382C-167AI
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
CY7C1380C-167BGI
CY7C1382C-167BGI
BG119
119 PBGA
CY7C1380C-167BZI
BB165A
165 fBGA
Industrial
CY7C1382C-167BZI
Shaded areas contain advance information.
Please contact your local sales representative for availability of these parts.
Document #: 38-05237 Rev. *D
Page 32 of 36
CY7C1380C
CY7C1382C
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
1.60 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
0.10
R 0.08 MIN.
0.20 MAX.
SEATING PLANE
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
0.60±0.15
0.20 MIN.
1.00 REF.
DETAIL
Document #: 38-05237 Rev. *D
A
51-85050-*A
Page 33 of 36
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1380C
CY7C1382C
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05237 Rev. *D
Page 34 of 36
CY7C1380C
CY7C1382C
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05237 Rev. *D
Page 35 of 36
CY7C1380C
CY7C1382C
Document History Page
Document Title: CY7C1380C/CY7C1382C 18-Mb (512K x 36/1M x 18) Pipelined SRAM
Document Number: 38-05237
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
116277
08/27/02
SKX
New Data Sheet
*A
121540
11/21/02
DSG
Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122
(BB165A) to rev. *C
*B
121797
11/21/02
CJM
Added 7C1380C-133 spec
Updated Ordering Information
*C
128904
09/11/03
DPM
Changed ordering of notes
Updated JTAG Boundary Scan order
Removed Pipelined Read/Write Timing diagram
Added tPOWER specification in Switching Characteristics table
*D
206081
02/13/04
RKF
Final Datasheet
Document #: 38-05237 Rev. *D
Page 36 of 36
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