Cypress CY7C1399L-20ZC 32k x 8 3.3v static ram Datasheet

CY7C1399
32K x 8 3.3V Static RAM
Features
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed
— 12/15 ns
• Low active power
— 255 mW (max.)
• Low CMOS standby power (L)
— 180 µW (max.), f=fMAX
• 2.0V data retention (L)
— 40 µW
• Low-power alpha immune 6T cell
• Plastic SOJ and TSOP packaging
Functional Description
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. The device
has an automatic power-down feature, reducing the power
consumption by more than 95% when deselected.
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O0
through I/O7) is written into the memory location addressed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399 is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
The CY7C1399 is a high-performance 3.3V CMOS Static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
Logic Block Diagram
Pin Configurations
SOJ
Top View
I/O0
INPUT BUFFER
I/O1
ROW DECODER
I/O2
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
32K x 8
ARRAY
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
I/O4
C1399–2
I/O5
CE
WE
I/O6
POWER
DOWN
COLUMN
DECODER
I/O7
A 14
A 12
A 13
A 11
A 10
OE
C1399–1
Selection Guide
7C1399–12
7C1399–15
7C1399–20
7C1399–25
7C1399–35
Maximum Access Time (ns)
12
15
20
25
35
Maximum Operating Current (mA)
60
55
50
45
40
Maximum CMOS Standby Current (µA)
500
500
500
500
500
Maximum CMOS Standby Current (µA) L
50
50
50
50
50
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 25, 1999
CY7C1399
Pin Configuration
TSOP
Top View
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A10
A11
21
22
23
20
19
18
17
16
15
14
13
12
11
10
9
8
24
25
26
27
28
1
2
3
4
5
6
7
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A14
A13
A12
C1399–3
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
Range
Ambient
Temperature
VCC
DC Voltage Applied to Outputs
in High Z State[1] ....................................–0.5V to VCC + 0.5V
Commercial
0°C to +70°C
3.3V ±300 mV
–40°C to +85°C
3.3V ±300 mV
Industrial
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range[1]
Parameter
Description
Test Conditions
7C1399–12
7C1399–15
7C1399–20
Min.
Min.
Min.
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = –2.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 4.0 mA
VIH
Input HIGH Voltage
2.2
VCC
+0.3V
2.2
VCC
+0.3V
VIL
Input LOW Voltage
–0.3
0.8
–0.3
IIX
Input Load Current
–1
+1
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC,
Output Disabled
–5
+5
IOS
Output Short
Circuit Current[2]
VCC = Max., VOUT = GND
–300
ICC
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
ISB1
Automatic CE Power-Down Max. VCC, CE ≥ VIH,
Current — TTL Inputs
VIN ≥ VIH, or VIN ≤ VIL,f = fMAX
ISB2
2.4
Max.
2.4
0.4
L
Automatic CE Power-Down Max. VCC, CE ≥ VCC – 0.3V, VIN ≥
Current — CMOS Inputs[3] VCC – 0.3V, or VIN ≤ 0.3V,
L
WE ≥VCC – 0.3V or WE ≤0.3V,
f=fMAX
2.4
0.4
Unit
V
0.4
V
2.2
VCC
+0.3V
V
0.8
–0.3
0.8
V
–1
+1
–1
+1
µA
–5
+5
–5
+5
µA
–300
–300
mA
60
55
50
mA
mA
5
5
5
3
3
3
500
500
500
50
50
50
Notes:
1. Minimum voltage is equal to – 2.0V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Device draws low standby current regardless of switching on the addresses.
2
Max.
µA
CY7C1399
Electrical Characteristics Over the Operating Range(continued)
7C1399–25
Parameter
Description
Test Conditions
Min.
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = –2.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 4.0 mA
VIH
Input HIGH Voltage
2.2
VCC
+0.3V
VIL
Input LOW Voltage
–0.3
IIX
Input Load Current
IOZ
Output Leakage Current
GND ≤ VI ≤ VCC,
Output Disabled
IOS
Output Short Circuit
Current[2]
VCC = Max., VOUT = GND
ICC
VCC Operating
Supply Current
ISB1
ISB2
7C1399–35
Min.
2.4
Max.
Unit
2.4
V
0.4
0.4
V
2.2
VCC
+0.3V
V
0.8
–0.3
0.8
V
–1
+1
–1
+1
µA
–5
+5
–5
+5
µA
–300
–300
mA
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
45
40
mA
Automatic CE Power-Down
Current — TTL Inputs
Max. V CC, CE ≥ VIH,
VIN ≥ VIH, or VIN ≤ VIL,
f = fMAX
5
5
mA
3
3
mA
Automatic CE Power-Down
Current — CMOS Inputs[3]
Max. VCC, CE ≥ VCC–0.3V, VIN ≥
VCC – 0.3V, or VIN ≤ 0.3V,
WE≥VCC–0.3V or WE≤ 0.3V,
f=fMAX
500
500
µA
50
50
µA
L
L
Capacitance[4]
Parameter
Description
CIN: Addresses
Input Capacitance
Test Conditions
Max.
Unit
TA = 25°C, f = 1 MHz, VCC = 3.3V
5
pF
6
pF
6
pF
CIN: Controls
COUT
Output Capacitance
AC Test Loads and Waveforms
R1 317Ω
3.3V
ALL INPUT PULSES
OUTPUT
3.0V
10%
R2
351Ω
CL
GND
≤ 3 ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
90%
10%
≤ 3 ns
C1399–4
THÉVENIN EQUIVALENT
167Ω
OUTPUT
90%
1.73V
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
3
CY7C1399
Switching Characteristics Over the Operating Range[5]
Parameter
Description
7C1399–12
7C1399–15
7C1399–20
7C1399–25
7C1399–35
Min.
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
12
15
20
25
35
ns
tDOE
OE LOW to Data Valid
5
6
7
8
10
ns
tLZOE
OE LOW to Low Z
12
12
[6]
OE HIGH to High Z
tLZCE
CE LOW to Low Z[6]
3
0
5
tHZCE
CE HIGH to High Z
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
20
6
0
0
12
25
6
0
15
35
7
ns
ns
7
ns
3
8
0
20
ns
0
3
7
ns
3
0
3
7
35
3
0
3
6
25
3
0
3
[6, 7]
20
15
3
[6, 7]
tHZOE
15
ns
8
ns
0
25
ns
35
ns
WRITE CYCLE[8, 9]
tWC
Write Cycle Time
12
15
20
25
35
ns
tSCE
CE LOW to Write End
8
10
12
15
20
ns
tAW
Address Set-Up to Write End
8
10
12
15
20
ns
tHA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tPWE
WE Pulse Width
8
10
12
15
20
ns
tSD
Data Set-Up to Write End
7
8
10
11
12
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
tHZWE
WE LOW to High Z
tLZWE
[8]
WE HIGH to Low Z
7
[6]
7
3
3
7
3
7
3
7
ns
3
ns
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[4]
Chip Deselect to Data
Retention Time
tR[4]
Operation Recovery Time
Conditions
Min.
Max.
2.0
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
L
VIN > VCC – 0.3V or
VIN < 0.3V
Unit
V
200
µA
20
µA
0
ns
tRC
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I OL/IOH and capacitance CL = 30 pF.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD .
4
CY7C1399
Data Retention Waveform
DATA RETENTION MODE
VDR ≥ 2V
3.0V
VCC
3.0V
tR
tCDR
CE
C1399–5
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
C1399–6
Read Cycle No. 2 [11, 12]
tRC
CE
tACE
OE
tHZOE
tHZCE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
C1399–7
Notes:
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
5
CY7C1399
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[8, 13, 14]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
OE
tSD
DATA I/O
NOTE 15
tHD
DATAIN VALID
tHZOE
C1399–8
Write Cycle No. 2 (CE Controlled)[8, 13, 14]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
tHD
DATAIN VALID
C1399–9
Write Cycle No. 3 (WE Controlled, OE LOW)[9, 14]
tWC
ADDRESS
CE
tAW
WE
tHA
tSA
tSD
DATA I/O
tHD
DATA IN VALID
NOTE 15
tLZWE
tHZWE
C1399–10
Notes:
13. Data I/O is high impedance if OE = VIH.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
15. During this period, the I/Os are in the output state and input signals shold not be applied.
6
CY7C1399
Truth Table
CE
WE
OE
Input/Output
Mode
Power
H
X
X
High Z
Deselect/Power-Down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High Z
Deselect, Output Disabled
Active (ICC)
Ordering Information
Speed
(ns)
12
15
20
25
35
Ordering Code
Package
Name
Package Type
CY7C1399–12VC
V21
28-Lead Molded SOJ
CY7C1399L–12VC
V21
28-Lead Molded SOJ
CY7C1399–12ZC
Z28
28-Lead Thin Small Outline Package
CY7C1399L–12ZC
Z28
28-Lead Thin Small Outline Package
CY7C1399–12VI
V21
28-Lead Molded SOJ
Operating
Range
Commercial
Industrial
CY7C1399–12ZI
Z28
28-Lead Thin Small Outline Package
CY7C1399–15VC
V21
28-Lead Molded SOJ
CY7C1399L–15VC
V21
28-Lead Molded SOJ
CY7C1399–15ZC
Z28
28-Lead Thin Small Outline Package
CY7C1399L–15ZC
Z28
28-Lead Thin Small Outline Package
CY7C1399–15VI
V21
28-Lead Molded SOJ
CY7C1399–15ZI
Z28
28-Lead Thin Small Outline Package
CY7C1399L–15ZI
Z28
28-Lead Thin Small Outline Package
CY7C1399–20VC
V21
28-Lead Molded SOJ
CY7C1399L–20VC
V21
28-Lead Molded SOJ
CY7C1399–20ZC
Z28
28-Lead Thin Small Outline Package
CY7C1399L–20ZC
Z28
28-Lead Thin Small Outline Package
CY7C1399–20VI
V21
28-Lead Molded SOJ
Industrial
CY7C1399–25VC
V21
28-Lead Molded SOJ
Commercial
CY7C1399L–25VC
V21
28-Lead Molded SOJ
CY7C1399–25ZC
Z28
28-Lead Thin Small Outline Package
CY7C1399L–25ZC
Z28
28-Lead Thin Small Outline Package
CY7C1399–35VC
V21
28-Lead Molded SOJ
CY7C1399L–35VC
V21
28-Lead Molded SOJ
CY7C1399–35ZC
Z28
28-Lead Thin Small Outline Package
CY7C1399L–35ZC
Z28
28-Lead Thin Small Outline Package
Document #: 38–00222–G
7
Commercial
Industrial
Commercial
Commercial
CY7C1399
Package Diagrams
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
28-Lead Thin Small Outline Package Z28
51-85071-E
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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