CY7C1471V25 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture Features Functional Description ■ No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states ■ Data is transferred on every clock ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 2.5 V I/O supply (VDDQ) ■ Fast clock-to-output times ❐ 6.5 ns (for 133-MHz device) ■ Clock enable (CEN) pin to enable clock and suspend operation ■ Synchronous self timed writes ■ Asynchronous output enable (OE) ■ CY7C1471V25 available in JEDEC-standard Pb-free 100-pin TQFP ■ Three chip enables (CE1, CE2, CE3) for simple depth expansion. ■ Automatic power-down feature available using ZZ mode or CE deselect. ■ Burst capability – linear or interleaved burst order ■ Low standby power The CY7C1471V25 are 2.5 V, 2 M × 36 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471V25 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by two or four byte write select (BWX) and a write enable (WE) input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) provide easy bank selection and output tristate control. To avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence. Selection Guide Description 133 MHz Unit Maximum access time 6.5 ns Maximum operating current 305 mA Maximum CMOS standby current 120 mA Errata: For information on silicon errata, see "Errata" on page 19. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation Document Number: 38-05287 Rev. *P • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 24, 2013 CY7C1471V25 Logic Block Diagram – CY7C1471V25 ADDRESS REGISTER A0, A1, A A1 D1 A0 D0 MODE CLK CEN C CE ADV/LD C BURST LOGIC Q1 A1' A0' Q0 WRITE ADDRESS REGISTER ADV/LD BW A BW B BW C WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S BW D WE OE CE1 CE2 CE3 ZZ Document Number: 38-05287 Rev. *P INPUT REGISTER D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQP A DQP B DQP C DQP D E E READ LOGIC SLEEP CONTROL Page 2 of 23 CY7C1471V25 Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Single Read Accesses ................................................ 6 Burst Read Accesses .................................................. 6 Single Write Accesses ................................................. 6 Burst Write Accesses .................................................. 6 Sleep Mode ................................................................. 6 Interleaved Burst Address Table ................................. 7 Linear Burst Address Table ......................................... 7 ZZ Mode Electrical Characteristics .............................. 7 Truth Table ........................................................................ 8 Truth Table for Read/Write .............................................. 9 Maximum Ratings ........................................................... 10 Operating Range ............................................................. 10 Electrical Characteristics ............................................... 10 Capacitance .................................................................... 11 Thermal Resistance ........................................................ 11 AC Test Loads and Waveforms ..................................... 11 Switching Characteristics .............................................. 12 Document Number: 38-05287 Rev. *P Switching Waveforms .................................................... 13 Ordering Information ...................................................... 16 Ordering Code Definitions ......................................... 16 Package Diagrams .......................................................... 17 Acronyms ........................................................................ 18 Document Conventions ................................................. 18 Units of Measure ....................................................... 18 Errata ............................................................................... 19 Part Numbers Affected .............................................. 19 Product Status ........................................................... 19 Ram9 Sync/NoBL ZZ Pin Issues Errata Summary .... 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 23 Worldwide Sales and Design Support ....................... 23 Products .................................................................... 23 PSoC® Solutions ...................................................... 23 Cypress Developer Community ................................. 23 Technical Support ..................................................... 23 Page 3 of 23 CY7C1471V25 Pin Configurations Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout[1] A 81 A 82 A 83 A 84 ADV/LD 85 OE 86 CEN 90 87 VSS 91 WE VDD 92 88 CE3 93 CLK BWA 94 89 BWC 96 BWB BWD 97 95 CE2 98 A CE1 41 42 43 44 45 46 47 48 49 50 A A A A A A A A A A0 VDD 37 A1 40 36 A VSS 35 39 34 A NC/144M 33 A 38 32 A NC/288M 31 BYTE D 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE BYTE C DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 99 100 A CY7C1471V25 DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA BYTE B BYTE A Note 1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 19. Document Number: 38-05287 Rev. *P Page 4 of 23 CY7C1471V25 Pin Definitions Name A0, A1, A I/O Description InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK. synchronous A[1:0] are fed to the two-bit burst counter. BWA, BWB, InputByte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising BWC, BWD synchronous edge of CLK. WE InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal synchronous must be asserted LOW to initiate a write sequence. ADV/LD InputAdvance/load input. Used to advance the on-chip address counter or load a new address. When HIGH synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a new address. CLK Inputclock Clock input. Captures all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 synchronous and CE3 to select or deselect the device. CE2 InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE3 to select or deselect the device. CE3 InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE2 to select or deselect the device. OE InputOutput enable, asynchronous input, active LOW. Combined with the synchronous logic block inside asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are enabled to behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. CEN InputClock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. synchronous When deasserted HIGH the clock signal is masked. Because deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. ZZ[2] InputZZ “sleep” input. This active HIGH input places the device in a non-time-critical “sleep” condition with asynchronous data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write synchronous sequences, DQPX is controlled by BWX correspondingly. MODE Input strap pin Mode input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. VDD Power supply Power supply inputs to the core of the device. VDDQ I/O power supply VSS Ground NC – Power supply for the I/O circuitry. Ground for the device. No connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Note 2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 19. Document Number: 38-05287 Rev. *P Page 5 of 23 CY7C1471V25 Functional Overview The CY7C1471V25 are synchronous flow through burst SRAMs designed specifically to eliminate wait states during write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the clock enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses are initiated by asserting all three chip enables (CE1, CE2, CE3) active at the rising edge of the clock. If CEN is active LOW and ADV/LD is asserted LOW, the address presented to the device is latched. The access can either be a read or write operation, depending on the status of the write enable (WE). Byte write select (BWX) can be used to conduct byte write operations. Write operations are qualified by the WE. All writes are simplified with on-chip synchronous self timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) simplify depth expansion. All operations (reads, writes, and deselects) are pipelined. ADV/LD must be driven LOW after the device is deselected to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are all asserted active, (3) WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the address register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW to drive out the requested data. On the subsequent clock, another operation (read/write/deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, the output is tristated immediately. Burst Read Accesses The CY7C1471V25 has an on-chip burst counter that enables the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW to load a new address into the SRAM, as described in the Single Read Accesses section. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and wraps around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (read or write) is maintained throughout the burst sequence. Document Number: 38-05287 Rev. *P Single Write Accesses Write accesses are initiated when these conditions are satisfied at clock rise: ■ CEN is asserted LOW ■ CE1, CE2, and CE3 are all asserted active ■ WE is asserted LOW. The address presented to the address bus is loaded into the address register. The write signals are latched into the control logic block. The data lines are automatically tristated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQPX. On the next clock rise the data presented to DQs and DQPX (or a subset for byte write operations, see "Truth Table for Read/Write" on page 9 for details) inputs is latched into the device and the write is complete. Additional accesses (read/write/deselect) can be initiated on this cycle. The data written during the write operation is controlled by BWX signals. The CY7C1471V25 provide byte write capability that is described in the "Truth Table for Read/Write" on page 9. The input WE with the selected BWx input selectively writes to only the desired bytes. Bytes not selected during a byte write operation remain unaltered. A synchronous self timed write mechanism is provided to simplify the write operations. Byte write capability is included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. Because the CY7C1471V25 are common I/O devices, data must not be driven into the device while the outputs are active. The OE can be deasserted HIGH before presenting data to the DQs and DQPX inputs. This tristates the output drivers. As a safety precaution, DQs and DQPX are automatically tristated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1471V25 have an on-chip burst counter that enables the user to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in the Single Write Accesses section. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWX inputs must be driven in each cycle of the burst write, to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Page 6 of 23 CY7C1471V25 Interleaved Burst Address Table Linear Burst Address Table (MODE = Floating or VDD) (MODE = GND) First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 00 01 10 11 01 00 11 10 01 10 11 00 10 11 00 01 10 11 00 01 11 10 01 00 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 120 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC – ns tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 – ns Document Number: 38-05287 Rev. *P Page 7 of 23 CY7C1471V25 Truth Table The truth table for CY7C1471V25 follows. [3, 4, 5, 6, 7, 8, 9] Operation Deselect cycle Deselect cycle Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK None H X X L L X X X L L->H None X X H L L X X X L L->H DQ Tristate Tristate Deselect cycle None X L X L L X X X L L->H Tristate Continue deselect cycle None X X X L H X X X L L->H Tristate Read cycle (begin burst) External L H L L L H X L L L->H Data out (Q) Next X X X L H X X L L L->H Data out (Q) External L H L L L H X H L L->H Tristate Next X X X L H X X H L L->H Tristate Read cycle (continue burst) NOP/dummy read (begin burst) Dummy read (continue burst) Write cycle (begin burst) External L H L L L L L X L L->H Data in (D) Write cycle (continue burst) Next X X X L H X L X L L->H Data in (D) NOP/write abort (begin burst) None L H L L L L H X L L->H Tristate Write abort (continue burst) Next X X X L H X H X L L->H Tristate Ignore clock edge (stall) Sleep mode Current X X X L X X X X H L->H – None X X X H X X X X X X Tristate Notes 3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one byte write select is active, BWX = valid signifies that the desired byte write selects are asserted, see "Truth Table for Read/Write" on page 9 for details. 4. Write is defined by BWX, and WE. See "Truth Table for Read/Write" on page 9. 5. When a write cycle is detected, all I/Os are tristated, even during byte writes. 6. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 7. CEN = H, inserts wait states. 8. Device powers up deselected with the I/Os in a tristate condition, regardless of OE. 9. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tristate when OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active. Document Number: 38-05287 Rev. *P Page 8 of 23 CY7C1471V25 Truth Table for Read/Write The read-write truth table for CY7C1471V25 follows. [10, 11, 12] Function WE BWA BWB BWC BWD Read H X X X X Write no bytes written L H H H H Write byte A – (DQA and DQPA) L L H H H Write byte B – (DQB and DQPB) L H L H H Write byte C – (DQC and DQPC) L H H L H Write byte D – (DQD and DQPD) L H H H L Write all bytes L L L L L Notes 10. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one byte write select is active, BWX = valid signifies that the desired byte write selects are asserted, see "Truth Table for Read/Write" on page 9 for details. 11. Write is defined by BWX, and WE. See "Truth Table for Read/Write" on page 9. 12. Table lists only a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is based on which byte write is active. Document Number: 38-05287 Rev. *P Page 9 of 23 CY7C1471V25 Maximum Ratings DC input voltage ................................. –0.5 V to VDD + 0.5 V Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied .......................................... –55 C to +125 C Supply voltage on VDD relative to GND .......–0.5 V to +3.6 V Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (MIL-STD-883, method 3015) ................................. > 2001 V Latch up current ..................................................... > 200 mA Operating Range Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD Range DC voltage applied to outputs in tristate ...........................................–0.5 V to VDDQ + 0.5 V Ambient Temperature Commercial 0 °C to +70 °C VDD VDDQ 2.5 V – 5% / 2.5 V – 5% to + 5% VDD Electrical Characteristics Over the Operating Range Parameter [13, 14] Description Test Conditions VDD Power supply voltage VDDQ I/O supply voltage VOH Output HIGH voltage For 2.5 V I/O, IOH =–1.0 mA VOL Output LOW voltage For 2.5 V I/O, IOL=1.0 mA For 2.5 V I/O Min Max Unit 2.375 2.625 V 2.375 VDD V 2.0 – V – 0.4 V VIH Input HIGH voltage [13] For 2.5 V I/O 1.7 VDD + 0.3 V VIL Input LOW voltage [13] For 2.5 V I/O –0.3 0.7 V IX Input leakage current except ZZ GND VI VDDQ and MODE –5 5 A Input current of MODE Input = VSS –30 Input = VDD – Input = VSS Input = VDD Input current of ZZ A 5 A –5 – A – 30 A IOZ Output leakage current GND VI VDDQ, output disabled –5 5 A IDD VDD operating supply current VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 6.5 ns cycle, 133 MHz – 305 mA ISB1 Automatic CE power-down current – TTL inputs VDD = Max, device deselected, VIN VIH or VIN VIL, f = fMAX, inputs switching 6.5 ns cycle, 133 MHz – 170 mA ISB2 Automatic CE power-down current – CMOS inputs VDD = Max, device deselected, 6.5 ns cycle, VIN 0.3 V or VIN > VDD – 0.3 V, 133 MHz f = 0, inputs static – 120 mA ISB3 Automatic CE power-down current – CMOS inputs VDD = Max, device deselected, 6.5 ns cycle, VIN 0.3 V or VIN > VDDQ – 0.3 V, 133 MHz f = fMAX, inputs switching – 170 mA ISB4 Automatic CE power-down current – TTL inputs VDD = Max, device deselected, 6.5 ns cycle, VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz f = 0, inputs static – 135 mA Notes 13. Overshoot: VIH(AC) < VDD +1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2). 14. TPower-up: assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 38-05287 Rev. *P Page 10 of 23 CY7C1471V25 Capacitance Parameter [15] Description Test Conditions 100-pin TQFP Max Unit 6 pF TA = 25 C, f = 1 MHz, VDD = 2.5 V, VDDQ = 2.5 V CADDRESS Address input capacitance CDATA Data input capacitance 5 pF CCTRL Control input capacitance 8 pF CCLK Clock input capacitance 6 pF CIO Input-output capacitance 5 pF 100-pin TQFP Package Unit 24.63 C/W 2.28 C/W Thermal Resistance Parameter [15] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, according to EIA/JESD51. AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms 2.5 V I/O Test Load R = 1667 2.5 V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 1538 VL = 1.25 V (a) ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE (b) 10% 90% 10% 90% 1 ns 1 ns (c) Note 15. Tested initially and after any design or process change that may affect these parameters. Document Number: 38-05287 Rev. *P Page 11 of 23 CY7C1471V25 Switching Characteristics Over the Operating Range Parameter [16, 17] tPOWER Description VDD(typical) to the first access [18] 133 MHz Unit Min Max 1 – ms Clock tCYC Clock cycle time 7.5 – ns tCH Clock HIGH 2.5 – ns tCL Clock LOW 2.5 – ns Output Times tCDV Data output valid after CLK rise – 6.5 ns tDOH Data output hold after CLK rise 2.5 – ns 3.0 – ns – 3.8 ns – 3.0 ns 0 – ns – 3.0 ns [19, 20, 21] tCLZ Clock to low Z tCHZ Clock to high Z [19, 20, 21] tOEV OE LOW to output valid tOELZ tOEHZ OE LOW to output low Z [19, 20, 21] OE HIGH to Output high Z [19, 20, 21] Setup Times tAS Address setup before CLK rise 1.5 – ns tALS ADV/LD setup before CLK rise 1.5 – ns tWES WE, BWX setup before CLK rise 1.5 – ns tCENS CEN setup before CLK rise 1.5 – ns tDS Data input setup before CLK rise 1.5 – ns tCES Chip enable setup before CLK rise 1.5 – ns tAH Address hold after CLK rise 0.5 – ns tALH ADV/LD hold after CLK rise 0.5 – ns tWEH WE, BWX hold after CLK rise 0.5 – ns Hold Times tCENH CEN hold after CLK rise 0.5 – ns tDH Data input hold after CLK rise 0.5 – ns tCEH Chip enable hold after CLK rise 0.5 – ns Notes 16. Timing reference level is 1.25 V when VDDQ = 2.5 V 17. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted. 18. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 19. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 11. Transition is measured ±200 mV from steady-state voltage. 20. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z before low Z under the same system conditions. 21. This parameter is sampled and not 100% tested. Document Number: 38-05287 Rev. *P Page 12 of 23 CY7C1471V25 Switching Waveforms Figure 3. Read/Write Timing [22, 23, 24] 1 2 3 t CYC 4 5 6 7 8 9 A5 A6 A7 10 CLK t CENS t CENH t CES t CEH t CH t CL CEN CE ADV/LD WE BW X A1 ADDRESS t AS A2 A4 A3 t CDV t AH t DOH t CLZ DQ D(A1) t DS D(A2) Q(A3) D(A2+1) t OEV Q(A4+1) Q(A4) t OELZ W RITE D(A1) W RITE D(A2) D(A5) Q(A6) D(A7) W RITE D(A7) DESELECT t OEHZ t DH OE COM M AND t CHZ BURST W RITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) t DOH W RITE D(A5) READ Q(A6) UNDEFINED Notes 22. For this waveform ZZ is tied LOW. 23. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH. 24. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. Document Number: 38-05287 Rev. *P Page 13 of 23 CY7C1471V25 Switching Waveforms (continued) Figure 4. NOP, STALL and DESELECT Cycles [25, 26, 27] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BW [A:D] ADDRESS A5 t CHZ D(A1) DQ Q(A2) Q(A3) D(A4) Q(A5) t DOH COMMAND WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) DON’T CARE STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED Notes 25. For this waveform ZZ is tied LOW. 26. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH. 27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. Document Number: 38-05287 Rev. *P Page 14 of 23 CY7C1471V25 Switching Waveforms (continued) Figure 5. ZZ Mode Timing [28, 29] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 28. Device must be deselected when entering ZZ mode. See "Truth Table" on page 8 for all possible signal conditions to deselect the device. 29. DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05287 Rev. *P Page 15 of 23 CY7C1471V25 Ordering Information Cypress offers other versions of this type of product in different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products, or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) 133 Package Diagram Ordering Code CY7C1471V25-133AXC Part and Package Type 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Operating Range Commercial Ordering Code Definitions CY 7 C 1471 V25 - 133 A X C Temperature Range: C = Commercial Pb-free Package Type: A = 100-pin TQFP Speed Grade: 133 MHz V25 = 2.5 V VDD Part Identifier: 1471 = FT, 2 Mb × 36 (72 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05287 Rev. *P Page 16 of 23 CY7C1471V25 Package Diagrams Figure 6. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 51-85050 *D Document Number: 38-05287 Rev. *P Page 17 of 23 CY7C1471V25 Acronyms Acronym Document Conventions Description Units of Measure CMOS Complementary Metal Oxide Semiconductor CE Chip Enable °C degree Celsius CEN Clock Enable MHz megahertz I/O Input/Output µA microampere JEDEC Joint Electron Devices Engineering Council mA milliampere NoBL No Bus Latency mm millimeter OE Output Enable ms millisecond SRAM Static Random Access Memory mV millivolt TQFP Thin Quad Flat Pack ns nanosecond TTL Transistor-Transistor Logic ohm WE Write Enable % percent pF picofarad V volt W watt Document Number: 38-05287 Rev. *P Symbol Unit of Measure Page 18 of 23 CY7C1471V25 Errata This section describes the Ram9 Sync/NoBL ZZ pin, JTAG and Chip Enable issues. Details include trigger conditions, the devices affected, proposed workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions. Part Numbers Affected Density & Revision Package Type Operating Range 72Mb-Ram9 NoBL SRAMs: CY7C147*, CY7C147*V25 All packages Commercial/ Industrial Product Status All of the devices in the Ram9 72Mb Sync/NoBL family are qualified and available in production quantities. Ram9 Sync/NoBL ZZ Pin Issues Errata Summary The following table defines the errata applicable to available Ram9 72Mb Sync/NoBL family devices. Item 1. Issues ZZ Pin Description Device Fix Status When asserted HIGH, the ZZ pin places device in a “sleep” condition with data integrity preserved.The ZZ pin currently does not have an internal pull-down resistor and hence cannot be left floating externally by the user during normal mode of operation. 72M-Ram9 (90nm) For the 72M Ram9 (90 nm) devices, this issue was fixed in the new revision. Please contact your local sales rep for availability. 1. ZZ Pin Issue ■ PROBLEM DEFINITION The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the SRAM. ■ TRIGGER CONDITIONS Device operated with ZZ pin left floating. ■ SCOPE OF IMPACT When the ZZ pin is left floating, the device delivers incorrect data. ■ WORKAROUND Tie the ZZ pin externally to ground. ■ FIX STATUS Fix was done for the 72Mb RAM9 Synchronous SRAMs and 72M RAM9 NoBL SRAMs devices. Fixed devices have a new revision. The following table lists the devices affected and the new revision after the fix. Table 1. List of Affected Devices and the new revision Revision before the Fix New Revision after the Fix CY7C147* CY7C147*B CY7C147*V25 CY7C147*BV25 Document Number: 38-05287 Rev. *P Page 19 of 23 CY7C1471V25 Document History Page Document Title: CY7C1471V25, 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05287 Rev. ECN No. Issue Date Orig. of Change Description of Change ** 114674 08/06/02 PKS New data sheet. *A 121522 01/27/03 CJM Changed status from Advanced Information to Preliminary. Updated Features (for package offering). Updated Ordering Information (Updated part numbers). *B 223721 See ECN NJY Updated Features (Removed 150 MHz frequency related information). Updated Functional Description (Removed 150 MHz frequency related information). Updated Logic Block Diagram (Splitted Logic Block Diagram into three Logic Block Diagrams). Updated Selection Guide (Removed 150 MHz frequency related information). Updated Functional Overview (Removed 150 MHz frequency related information). Updated Boundary Scan Exit Order (Replaced TBD with values for all packages). Updated Electrical Characteristics (Removed 150 MHz frequency related information, replaced TBD with values for maximum values of IDD, ISB1, ISB2, ISB3, ISB4 parameters). Updated Capacitance (Replaced TBD with values for all packages). Updated Thermal Resistance (Replaced TBD with values for all packages). Updated Switching Characteristics (Removed 150 MHz frequency related information). Updated Switching Waveforms. Updated Ordering Information (Updated part numbers). Updated Package Diagrams (spec 51-85165 (Changed revision from ** to *A), removed spec 51-85143 and included spec 51-85167 for 209-Ball BGA package, removed spec 51-85115 (corresponding to 119-BGA package)). *C 235012 See ECN RYQ Minor Change (To match on the spec system and external web). *D 243572 See ECN NJY Updated Pin Configurations (Updated Figure “165-Ball FBGA (15 × 17 × 1.40 mm) pinout (3 Chip Enable with JTAG)” (Changed ball H2 from VDD to NC), updated Figure “209-ball BGA (14 × 22 × 1.76 mm) pinout” (Changed ball R11 from DQPa to DQPe)). Updated Capacitance (Splitted CIN parameter into CADDRESS, CDATA, CCLK parameters and also updated the values). *E 299511 See ECN SYT Updated Features (Removed 117 MHz frequency related information). Updated Selection Guide (Removed 117 MHz frequency related information). Updated Electrical Characteristics (Removed 117 MHz frequency related information). Updated Thermal Resistance (Changed value of JA from 16.8 C/W to 24.63 C/W, changed value of JC from 3.3 C/W to 2.28 C/W for 100-pin TQFP package). Updated Switching Characteristics (Removed 117 MHz frequency related information). Updated Ordering Information (Updated part numbers (Removed 117 MHz frequency related information, added Pb-free information for 100-pin TQFP, 165-ball FBGA and 209-ball BGA Packages), added comment of “Pb-free BG packages availability” below the Ordering Information). Document Number: 38-05287 Rev. *P Page 20 of 23 CY7C1471V25 Document History Page (continued) Document Title: CY7C1471V25, 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05287 Rev. ECN No. Issue Date Orig. of Change Description of Change *F 323039 See ECN PCI Updated Pin Configurations (Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard, changed package name from 209-Ball PBGA to 209-Ball FBGA on page# 7). Updated Pin Definitions (Added Address Expansion pins in the Pin Definitions Table). Updated Operating Range (Added Industrial Temperature Range). Updated Electrical Characteristics (Updated Test Conditions of VOL, VOH parameters). Updated Ordering Information (Updated part numbers (Added Pb-free information in the ordering information table), removed comment of “Pb-free BG packages availability” below the Ordering Information). *G 416221 See ECN NXR Changed status from Preliminary to Final. Changed address of Cypress Semiconductor Corporation from “3901 North First Street” to “198 Champion Court”. Updated Electrical Characteristics (Updated Note 14 (Changed VIH < VDD to VIH < VDD), changed description of IX parameter from Input Load Current except ZZ and MODE to Input Leakage Current except ZZ and MODE, changed minimum value of IX parameter (corresponding to Input Current of MODE (Input = VSS)) from –5 A to –30 A, changed maximum value of IX parameter (corresponding to Input Current of MODE (Input = VDD)) from 30 A to 5 A, changed minimum value of IX parameter (corresponding to Input Current of ZZ (Input = VSS)) from –30 A to –5 A, changed maximum value of IX parameter (corresponding to Input Current of ZZ (Input = VDD)) from 5 A to 30 A). Updated Ordering Information (Updated part numbers, replaced Package Name column with Package Diagram in the Ordering Information table). *H 472335 See ECN VKN Updated Pin Configurations (Updated Figure “209-ball FBGA (14 × 22 × 1.76 mm) pinout” (Corrected the ball name for H9 to VSS from VSSQ)). Updated TAP AC Switching Characteristics (Changed minimum value of tTH, tTL parameters from 25 ns to 20 ns, changed maximum value of tTDOV parameters from 5 ns to 10 ns). Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND). Updated Ordering Information (Updated part numbers). *I 1274732 See ECN VKN / AESA *J 2897278 03/22/2010 NJY Updated Ordering Information (Removed obsolete part numbers from Ordering Information table). Updated Package Diagrams. *K 3034798 09/21/2010 NJY Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits and updated in new template. *L 3353119 08/24/2011 PRIT Updated Functional Description (Updated Note as “For best practice recommendations, refer to SRAM System Guidelines.”). Updated Package Diagrams (spec 51-85050 (Changed revision from *C to *D), spec 51-85165 (Changed revision from *B to *C)). Document Number: 38-05287 Rev. *P Updated Switching Waveforms (Updated Figure 4 (Corrected typo)). Page 21 of 23 CY7C1471V25 Document History Page (continued) Document Title: CY7C1471V25, 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05287 Rev. ECN No. Issue Date Orig. of Change Description of Change *M 3633894 06/01/2012 PRIT Updated Features (Removed CY7C1473V25, CY7C1475V25 related information, removed 165-ball FBGA package, 209-ball FBGA package related information). Updated Functional Description (Removed CY7C1473V25, CY7C1475V25 related information, removed the Note “For best practice recommendations, refer to SRAM System Guidelines.” and its reference). Updated Selection Guide (Removed 100 MHz frequency related information). Removed Logic Block Diagram – CY7C1473V25. Removed Logic Block Diagram – CY7C1475V25. Updated Pin Configurations (Removed CY7C1473V25, CY7C1475V25 related information, removed 165-ball FBGA package, 209-ball FBGA package related information). Updated Pin Definitions (Removed JTAG related information). Updated Functional Overview (Removed CY7C1473V25, CY7C1475V25 related information). Updated Truth Table (Removed CY7C1473V25, CY7C1475V25 related information). Removed Truth Table for Read/Write (Corresponding to CY7C1473V25, CY7C1475V25). Removed IEEE 1149.1 Serial Boundary Scan (JTAG). Removed TAP Controller State Diagram. Removed TAP Controller Block Diagram. Removed TAP Timing. Removed TAP AC Switching Characteristics. Removed 1.8 V TAP AC Test Conditions. Removed 1.8 V TAP AC Output Load Equivalent. Removed 2.5 V TAP AC Test Conditions. Removed 2.5 V TAP AC Output Load Equivalent. Removed TAP DC Electrical Characteristics and Operating Conditions. Removed Identification Register Definitions. Removed Scan Register Sizes. Removed Identification Codes. Removed Boundary Scan Exit Order (Corresponding to CY7C1471V25, CY7C1473V25, CY7C1475V25). Updated Operating Range (Removed Industrial Temperature Range). Updated Electrical Characteristics (Removed 100 MHz frequency related information). Updated Capacitance (Removed 165-ball FBGA package, 209-ball FBGA package related information). Updated Thermal Resistance (Removed 165-ball FBGA package, 209-ball FBGA package related information). Updated Switching Characteristics (Removed 100 MHz frequency related information). Updated Package Diagrams (Removed 165-ball FBGA package (spec 51-85165), 209-ball FBGA package related information (spec 51-85167)). *N 3749841 09/20/2012 PRIT No technical updates. Completing sunset review. *O 3970182 04/18/2013 PRIT Updated Features (Removed 1.8 V related information). Updated Electrical Characteristics (Removed 1.8 V related information). Updated AC Test Loads and Waveforms (Removed 1.8 V related information in Figure 2). Updated Switching Characteristics (Removed 1.8 V related information in Note 16). Added Errata. *P 4038218 06/24/2013 PRIT Added Errata Footnotes. Updated in new template. Document Number: 38-05287 Rev. *P Page 22 of 23 CY7C1471V25 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2002-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05287 Rev. *P Revised June 24, 2013 Page 23 of 23 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders.