Cypress CY7C164-35VC 16k x 4 static ram Datasheet

66
CY7C164
CY7C166
16K x 4 Static RAM
Features
three-state drivers. The CY7C166 has an active LOW Output
Enable (OE) feature. Both devices have an automatic powerdown feature, reducing the power consumption by 65% when
deselected.
• High speed
— 15 ns
• Output enable (OE) feature (CY7C166)
• CMOS for optimum speed/power
• Low active power
— 633 mW
• Low standby power
— 110 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW (and the
Output Enable (OE) is LOW for the CY7C166). Data on the
four input/output pins (I/O0 through I/O3) is written into the
memory location specified on the address pins (A0 through
A13).
Functional Description
Reading the device is accomplished by taking Chip Enable
(CE) LOW (and OE LOW for CY7C166), while Write Enable
(WE) remains HIGH. Under these conditions the contents of
the memory location specified on the address pins will appear
on the four data I/O pins.
The CY7C164 and CY7C166 are high-performance CMOS
static RAMs organized as 16,384 by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and
The I/O pins stay in a high-impedance state when Chip Enable
(CE) is HIGH (or Output Enable (OE) is HIGH for CY7C166).
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
SOJ
Top View
DIP
Top View
A5
A6
A7
A8
A9
A10
A11
A12
A13
CE
GND
INPUT BUFFER
1
2
3
4
5
6 7C164
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
VCC
A4
A3
A2
A1
A0
I/O3
I/O2
I/O1
I/O0
WE
A5
A6
A7
A8
A9
A10
A11
A12
A13
CE
NC
GND
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A4
A3
A2
A1
A0
NC
I/O3
I/O2
I/O1
I/O0
WE
C164–2
256 x 64 x 4
ARRAY
DIP/SOJ
Top View
I/O2
A5
A6
A7
A8
A9
A10
A11
A12
A13
CE
OE
GND
I/O1
I/O0
POWER
DOWN
CE
WE
(OE)
(7C166 ONLY)
A13
COLUMN
DECODER
A0
A9
A10
A11
A12
I/O3
SENSE AMPS
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
C164–3
1
2
3
4
5
6 7C164
7
8
9
10
11
12
VCC
A4
A3
A2
A1
A0
NC
I/O3
I/O2
I/O1
I/O0
WE
1
24
2
23
3
22
4
21
5
20
6 7C166 19
7
18
17
8
9
16
10
15
11
14
13
12
C166–1
C164–4
]
Selection Guide
7C164-15
7C166-15
7C164-20
7C166-20
7C164-25
7C166-25
7C164-35
7C166-35
Maximum Access Time (ns)
15
20
25
35
Maximum Operating Current (mA)
115
115
105
105
Maximum Standby Current (mA)
20
20
20
20
Cypress Semiconductor Corporation
Document #: 38-05025 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 24, 2001
CY7C164
CY7C166
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Latch-Up Current.................................................... >200 mA
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Operating Range
DC Voltage Applied to Outputs
in High Z State[1] ............................................ –0.5V to +7.0V
DC Input Voltage
[1]
........................................ –0.5V to +7.0V
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
7C164-15
7C166-15
Parameter
Description
Test Conditions
Min.
Max.
2.4
7C164-20
7C166-20
Min.
7C164-25, 35
7C166-25, 35
Max.
VOH
Output HIGH
Voltage
VCC = Min.,
IOH = –4.0 mA
2.4
VOL
Output LOW
Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
2.2
VCC
2.2
VCC
VIL
Input LOW
Voltage[1]
–0.5
0.8
–0.5
0.8
IIX
Input Load Current
GND < VI < VCC
–5
+5
–5
+5
IOZ
Output Leakage
Current
GND < VO < VCC,
Output Disabled
–5
+5
–5
+5
IOS
Output Short
Circuit Current[2]
VCC = Max.,
VOUT = GND
ICC
VCC Operating
Supply Current
ISB1
ISB2
0.4
Min.
Max.
2.4
0.4
Unit
V
0.4
V
2.2
VCC
V
–0.5
0.8
V
–5
+5
µA
–5
+5
µA
–350
–350
–350
mA
VCC = Max.,
IOUT = 0 mA
115
115
105
mA
Automatic CE
Power-Down Current[3]
Max. VCC, CE > VIH,
Min. Duty Cycle = 100%
40
40
20
mA
Automatic CE
Power-Down Current[3]
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V
or VIN < 0.3V
20
20
20
mA
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
10
pF
10
pF
Notes:
1. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.
2. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05025 Rev. **
Page 2 of 9
CY7C164
CY7C166
AC Test Loads and Waveforms
R1 481Ω
5V
R1 481Ω
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
R2
255Ω
30 pF
3.0V
R2
255 Ω
5 pF
INCLUDING
JIG AND
SCOPE (a)
INCLUDING
JIG AND
SCOPE (b)
90%
10%
90%
10%
GND
< 5 ns
< 5 ns
C164–6
C164–5
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Switching Characteristics Over the Operating Range[5]
7C164-15
7C166-15
Parameter
Description
Min.
Max.
7C164-20
7C166-20
Min.
Max.
7C164-25
7C166-25
Min.
Max.
7C164-35
7C166-35
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
tAA
Address to Data Valid
tOHA
Output Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
7C166
tLZOE
OE LOW to Low Z
7C166
tHZOE
OE HIGH to High Z
7C166
[6]
tLZCE
CE LOW to Low Z
tHZCE
CE HIGH to High Z[6, 7]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
WRITE CYCLE
20
15
3
25
20
5
15
8
5
8
0
5
0
ns
15
ns
ns
5
0
20
35
12
10
ns
ns
15
0
20
ns
ns
3
10
8
15
35
12
3
8
ns
5
25
10
3
3
25
5
20
10
3
35
ns
ns
20
ns
[8]
tWC
Write Cycle Time
15
20
20
25
ns
tSCE
CE LOW to Write End
12
15
20
25
ns
tAW
Address Set-Up to Write End
12
15
20
25
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
12
15
15
20
ns
tSD
Data Set-Up to Write End
10
10
10
15
ns
tHD
Data Hold from Write End
0
0
0
0
ns
[6]
tLZWE
WE HIGH to Low Z
tHZWE
WE LOW to High Z[6, 7]
5
5
7
5
7
5
7
ns
10
ns
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. These parameters are guaranteed by design and not 100% tested.
7. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05025 Rev. **
Page 3 of 9
CY7C164
CY7C166
Switching Waveforms
Read Cycle No.1
[9, 10]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
C164–7
Read Cycle No. 2 [9, 11]
tRC
CE
tACE
OE
7C166
tHZOE
tHZCE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
V CC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
C164–8
Write Cycle No. 1 (WE Controlled) [8, 12]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATAINVALID
DATA IN
tHZWE
DATA I/O
tHD
tLZWE
HIGH IMPEDANCE
DATA UNDEFINED
C164–9
Notes:
9. WE is HIGH for read cycle.
10. Device is continuously selected, CE = VIL. (CY7C166: OE = VIL also).
11. Address valid prior to or coincident with CE transition LOW.
12. CY7C166 only: Data I/O will be high-impedance if OE = VIH.
Document #: 38-05025 Rev. **
Page 4 of 9
CY7C164
CY7C166
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled) [8, 12, 13]
tWC
ADDRESS
tSA
tSCE
CE
tHA
tAW
tPWE
WE
tSD
DATA IN
tHD
DATAIN VALID
DATA I/O
HIGH IMPEDANCE
C164–10
Note:
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05025 Rev. **
Page 5 of 9
CY7C164
CY7C166
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SB
1.2
1.2
I CC
0.8
0.6
0.4
4.5
5.0
0.8
0.6
0.4
V CC = 5.0V
V IN = 5.0V
5.5
6.0
I SB
0.0
–55
25
1.6
1.3
NORMALIZED tAA
NORMALIZED t AA
1.4
1.2
1.1
TA = 25°C
1.0
1.4
1.2
1.0
VCC =5.0V
0.8
0.9
5.0
5.5
0.6
–55
6.0
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
2.5
25.0
DELTA tAA (ns)
30.0
2.0
1.5
1.0
0.5
25
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
Document #: 38-05025 Rev. **
40
20
0
0.0
1.0
5.0
3.0
4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
VCC = 5.0V
TA =25°C
80
60
40
20
0
0.0
125
20.0
15.0
10.0
0.0
2.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NORMALIZED I CC vs. CYCLE TIME
1.25
VCC = 4.5V
TA = 25°C
5.0
1.0
V CC = 5.0V
TA = 25°C
60
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
0.0
0.0
80
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED I PO
125
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
4.5
100
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
0.8
4.0
120
OUTPUT SINK CURRENT (mA)
0.0
4.0
I CC
0.2
I SB
0.2
1.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0
200
400
600
800 1000
CAPACITANCE (pF)
NORMALIZED I CC
1.0
NORMALIZED I,CC
I
NORMALIZED I,CC
I
SB
1.4
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
VCC = 5.0V
TA = 25°C
VIN = 0.5V
1.00
0.75
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Page 6 of 9
CY7C164
CY7C166
CY7C164 Truth Table
CE
WE
Address Designators
Input/Output
Mode
H
X
High Z
Deselect/Power-Down
L
H
Data Out
Read
L
L
Data In
Write
CY7C166 Truth Table
CE
WE
OE
Input/Output
Mode
H
X
X
High Z
Deselect/Power-Down
L
H
L
Data Out
Read
L
L
H
Data In
Write
L
H
H
High Z
Write
Address
Name
Address
Function
CY 7C164 Pin CY7C166 Pin
Number
Number
A5
X3
1
1
A6
X4
2
2
A7
X5
3
3
A8
X6
4
4
A9
X7
5
5
A10
Y5
6
6
A11
Y4
7
7
A12
Y0
8
8
A13
Y1
9
9
A0
Y2
17
19
A1
Y3
18
20
A2
X0
19
21
A3
X1
20
22
A4
X2
21
23
Ordering Information
Speed
(ns)
15
20
25
35
Speed
(ns)
15
20
25
35
Ordering Code
Package
Name
Package Type
CY7C164-15PC
P9
22-Lead (300-Mil) Molded DIP
CY7C164-15VC
V13
24-Lead Molded SOJ
CY7C164-20PC
P9
22-Lead (300-Mil) Molded DIP
CY7C164-20VC
V13
24-Lead Molded SOJ
CY7C164-25PC
P9
22-Lead (300-Mil) Molded DIP
CY7C164-25VC
V13
24-Lead Molded SOJ
CY7C164-35PC
P9
22-Lead (300-Mil) Molded DIP
CY7C164-35VC
V13
24-Lead Molded SOJ
Ordering Code
Package
Name
Package Type
CY7C166-15PC
P13
24-Lead (300-Mil) Molded DIP
CY7C166-15VC
V13
24-Lead Molded SOJ
CY7C166-20PC
P13
24-Lead (300-Mil) Molded DIP
CY7C166-20VC
V13
24-Lead Molded SOJ
CY7C166-25PC
P13
24-Lead (300-Mil) Molded DIP
CY7C166-25VC
V13
24-Lead Molded SOJ
CY7C166-35PC
P13
24-Lead (300-Mil) Molded DIP
CY7C166-35VC
V13
24-Lead Molded SOJ
Document #: 38-05025 Rev. **
Operating
Range
Commercial
Commercial
Commercial
Commercial
Operating
Range
Commercial
Commercial
Commercial
Commercial
Page 7 of 9
CY7C164
CY7C166
Package Diagrams
22-Lead (300-Mil) Molded DIP P9
51-85012-A
24-Lead (300-Mil) Molded DIP P13/P13A
51-85013-A
24-Lead (300-Mil) Molded SOJ V13
51-85030-A
Document #: 38-05025 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C164
CY7C166
Document Title: CY7C164, CY7C166 16K x 4 Static RAM
Document Number: 38-05025
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
106811
09/10/01
SZV
Change from Spec number: 38-00032 to 38-05025
Document #: 38-05025 Rev. **
Page 9 of 9
Similar pages