Cypress CY7C472-15JI 8k x 9 fifo, 16k x 9 fifo 32k x 9 fifo with programmable flag Datasheet

1CY 7C47 4
CY7C470
CY7C472
CY7C474
8K x 9 FIFO, 16K x 9 FIFO
32K x 9 FIFO with Programmable Flags
Features
offered in 600-mil DIP, PLCC, and LCC packages. Each FIFO
memory is organized such that the data is read in the same
sequential order that it was written. Three status pins—Empty/Full (E/F), Programmable Almost Full/Empty (PAFE), and
Half Full (HF)—are provided to the user. These pins are decoded to determine one of six states: Empty, Almost Empty,
Less than Half Full, Greater than Half Full, Almost Full, and
Full.
• 8K x 9, 16K x 9, and 32K x 9 FIFO buffer memory
• Asynchronous read/write
• High-speed 33.3-MHz read/write independent of
depth/width
• Low operating power
— ICC (max.) = 70 mA
• Programmable Almost Full/Empty flag
• Empty, Almost Empty, Half Full, Almost Full, and Full
status flags
• Programmable retransmit
• Expandable in width
• 5V ± 10% supply
• TTL compatible
• Three-state outputs
• Proprietary 0.8-micron CMOS technology
The read and write operations may be asynchronous; each
can occur at a rate of 33.3 MHz. The write operation occurs
when the write (W) signal goes LOW. Read occurs when read
(R) goes LOW. The nine data outputs go into a high-impedance state when R is HIGH.
The user can store the value of the read pointer for retransmit
by using the MARK pin. A LOW on the retransmit (RT) input
causes the FIFO to resend data by resetting the read pointer
to the value stored in the mark pointer.
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFO to resend the
data. With the mark feature, retransmit can start from any word
in the FIFO.
Functional Description
The CYC47X FIFO series consists of high-speed, low-power,
first-in first-out (FIFO) memories with programmable flags and
retransmit mark. The CY7C470, CY7C472, and CY7C474 are
8K, 16K, and 32K words by 9 bits wide, respectively. They are
Logic Block Diagram
The CYC47X series is fabricated using a proprietary 0.8-micron N-well CMOS technology. Input ESD protection is greater
than 2001V and latch-up is prevented by the use of reliable
layout techniques, guard rings, and a substrate bias generator.
Pin Configurations
DATAINPUTS
(D0 –D8 )
4
W
WRITE
POINTER
D3
3
26
D5
D2
4
25
D6
D1
5
24
D7
D0
6
23
RT
22
MR
7
27
26
RT
25
MR
MARK
7
24
E/F
PAFE
8
21
E/F
11
23
Q0
9
20
HF
R
NC
12
22
HF
Q7
Q1
10
19
Q7
RT
MARK
Q2
13
21
14 15 16 17 18 19 20
Q6
Q2
11
18
Q6
Q3
12
17
Q5
Q8
13
16
Q4
GND
14
15
R
HF
PAFE
E/F
PAFE
READ
POINTER
D4
D6
D7
NC
D0
FLAG
LOGIC
Vcc
27
28
MARK
Q0
Q1
8
1
28
2
6
D1
2
1
32 31 30
29
D2
3
W
D8
5
PROGRAMMABLE
FLAG REGISTER
RAM ARRAY
8K x 9
16K x 9
32K x 9
DIP
Top View
PLCC/LCC
Top View
7C470
7C472
7C474
9
10
7C470–2
MARK
POINTER
7C470
7C472
7C474
7C470–3
THREE–
STATE
BUFFERS
DATAOUTPUTS
(Q0 –Q8 )
RESET
LOGIC
MR
7C470–1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
December 1990 – Revised April 1995
CY7C470
CY7C472
CY7C474
Selection Guide
Frequency (MHz)
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
7C470–15
7C472–15
7C474–15
7C470–20
7C472–20
7C474–20
7C470–25
7C472–25
7C474–25
7C470–40
7C472–40
7C474–40
33.3
33.3
28.5
20
15
20
25
40
105
Military/Industrial
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-Up Current ..................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
Power Dissipation ..........................................................1.0W
Output Current, into Outputs (LOW) ............................ 20 mA
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
Industrial
–40°C to +85°C
5V ± 10%
Military[1]
–55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Range[2]
7C470–15
7C472–15
7C474–15
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –2.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Com’l
Min.
Max.
2.4
7C470–20
7C472–20
7C474–20
7C470–25
7C472–25
7C474–25
Min.
Min.
Max.
2.4
0.4
Max.
2.4
0.4
2.2
V
0.4
2.2
Mil/Ind
2.2
0.8
Unit
V
V
2.2
VIL
Input LOW Voltage
0.8
V
IIX
Input Leakage Current
GND ≤ VI ≤ VCC
–10
+10
–10
+10
–10
+10
µA
IOZ
Output Leakage Current
–10
+10
–10
+10
–10
+10
µA
ICC
Operating Current
R ≥ VIH, GND ≤ VO ≤ VCC
VCC = Max.,
Com’l
IOUT = 0 mA
Mil/Ind
90
mA
ISB1
Standby Current
All Inputs =
VIH Min.
Com’l
Com’l
0.8
105
110
25
Mil/Ind
ISB2
Power-Down Current
All Inputs =
VCC –0.2V
IOS[3]
Output Short Circuit Current
VCC = Max., VOUT = GND
20
–90
Notes:
1. TA is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second.
2
25
30
Mil/Ind
95
mA
30
20
25
25
–90
–90
mA
mA
CY7C470
CY7C472
CY7C474
Electrical Characteristics Over the Operating Range[2] (continued)
7C470–40
7C472–40
7C474–40
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –2.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
IIX
Input Leakage Current
GND ≤ VI ≤ VCC
IOZ
Output Leakage Current
R ≥ VIH, GND ≤ VO ≤ VCC
ICC
Operating Current
VCC = Max., IOUT = 0 mA
All Inputs = VIH Min.
ISB2
Power-Down Current
All Inputs = VCC –0.2V
IOS[3]
Output Short Circuit Current
Unit
V
0.4
Input LOW Voltage
Standby Current
Max.
2.4
VIL
ISB1
Min.
Com’l
2.2
Mil/Ind
2.2
V
V
0.8
V
–10
+10
µA
–10
+10
µA
Com’l
70
mA
Mil/Ind
75
Com’l
25
Mil/Ind
30
Com’l
20
Mil/Ind
25
VCC = Max., VOUT = GND
mA
mA
–90
mA
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 4.5V
Max.
Unit
10
pF
12
pF
AC Test Loads and Waveforms
R1 500Ω
5V
R1 500Ω
5V
OUTPUT
ALL INPUT PULSES
3.0V
OUTPUT
R2
333Ω
30 pF
INCLUDING
JIGAND
SCOPE
7C470–4
(a)
R2
333Ω
5 pF
INCLUDING
JIG AND
SCOPE
GND
10%
≤ 5 ns
90%
90%
10%
≤ 5 ns
7C470–6
7C470–5
(b)
Equivalent to:
THÉVENIN EQUIVALENT
200Ω
OUTPUT
2V
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
3
CY7C470
CY7C472
CY7C474
Switching Characteristics Over the Operating Range[5, 6]
7C470–15
7C472–15
7C474–15
Parameter
Description
Min.
Max.
30
7C470–20
7C472–20
7C474–20
Min.
Max.
30
7C470–25
7C472–25
7C474–25
Min.
Max.
Min.
Max.
Cycle Time
tA
Access Time
tRV
Recovery Time
15
10
10
10
ns
tPW
Pulse Width
15
20
25
40
ns
tLZR
Read LOW to Low Z
3
3
3
3
ns
tDV[7]
tHZ[7]
Valid Data from Read HIGH
3
3
3
3
ns
tHWZ
Write HIGH to Low Z
5
5
5
5
ns
tSD
Data Set-Up Time
11
12
15
20
ns
tHD
Data Hold Time
0
0
0
0
ns
tEFD
E/F Delay
15
20
25
40
ns
tEFL
MR to E/F LOW
25
30
35
50
ns
tHFD
HF Delay
25
30
35
50
ns
tAFED
PAFE Delay
25
30
35
50
ns
tRAE
Effective Read from
Write HIGH
15
20
25
40
ns
tWAF
Effective Write from
Read HIGH
15
20
25
40
ns
Read HIGH to High Z
20
15
50
Unit
tCY
15
35
7C470–40
7C472–40
7C474–40
25
15
ns
40
18
25
ns
ns
Notes:
5. Test conditions assume signal transmission time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30-pF load
capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified.
6. See the last page of this specification for Group A subgroup testing information.
7. tHZR and tDVR use capacitance loading as in part (b) of AC Test Loads. tHZR transition is measured at +500 mV from VOL and –500 mV from VOH. tDVR transition is measured
at the 1.5V level. tHWZ and tLZR transition is measured at ±100 mV from the steady state.
4
CY7C470
CY7C472
CY7C474
Switching Waveforms
Asynchronous Read and Write
tA
tCY
tPW
tA
tRV
R
tLZR
tDVR
tHZR
DATA VALID
Q0–Q 8
tCY
tPW
DATA VALID
tRV
tPW
W
tSD
tHD
tSD
DATA VALID
D0–D 8
tHD
DATA VALID
7C470–7
MasterReset (No Write to Programmable Flag Register)
tCY
tRV
tPW
MR
tRV
R, W
tHFD
HF
E/F
tEFL
PAFE
tAFED
7C470–8
Master Reset (Write to Programmable Flag
tCY
tPW
Register)[8,9]
tCY
tRV
tRV
MR
tPW
tRV
tRV
W(R)
tCY
D0–D8
(Q0–Q8)
tHD
VALID
7C470–9
Notes:
8. Waveform labels in parentheses pertain to writing the programmable flag register from the output port (Q0 – Q8).
9. Master Reset (MR) must be pulsed LOW once prior to programming.
5
CY7C470
CY7C472
CY7C474
Switching Waveforms (Continued)
E/F Flag (Last Write to First Read Full Flag)
W
FULL–1
FULL
FULL–1
R
tEFD
tEFD
E/F
HF
LOW
7C470–10
E/F Flag (Last Read to First Write Empty Flag)
R
EMPTY+1
EMPTY
EMPTY+1
W
tEFD
tEFD
E/F
HF
HIGH
7C470–11
Half Full Flag
W
HALF–FULL
HALF–FULL +1
HALF–FULL
R
tHFD
tHFD
HF
7C470–12
6
CY7C470
CY7C472
CY7C474
Switching Waveforms (Continued)
PAFE Flag (Almost Full)
W
R
tAFED
tAFED
PAFE
HF
LOW
7C470–13
PAFE Flag (Almost Empty)
R
W
tAFED
tAFED
PAFE
HF
HIGH
7C470–14
Retransmit[10]
tCY
tCY
W, R
RT
tA
tRV
tPW
tRV
tLZR
tCY
Q 0–Q 8
DATA VALID
FLAGS[10]
FLAGS VALID
7C470–15
Note:
10. The flags may change state during retransmit, but they will be valid a tCY later, except for the CY7C47X–20 (Military), whose flags will be valid after tCY + 10 ns.
7
CY7C470
CY7C472
CY7C474
Switching Waveforms (Continued)
Mark
tCY
tCY
W, R
MARK
tRV
tPW
tRV
7C470–16
Empty Flag and Read Data Flow-Through Mode
DATA IN
W
tRAE
R
tPW
tEFD
E/F
tA
tEFD
tHWZ
DATA OUT
DATA VALID
7C470–17
8
CY7C470
CY7C472
CY7C474
Switching Waveforms (Continued)
Full Flag and Write Data Flow-Through Mode
R
tWAF
tPW
W
tEFD
tEFD
E/F
tSD
DATA IN
tHD
DATA VALID
tA
DATA OUT
DATA VALID
7C470–18
Architecture
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and resent if necessary. Retransmission can start
from anywhere in the FIFO and be repeated without limitation.
The CY7C470, CY7C472, and CY7C474 FIFOs consist of an
array of 8,192, 16,384, and 32,768 words of 9 bits each, respectively. The control consists of a read pointer, a write pointer, a retransmit pointer, control signals (i.e., write, read, mark,
retransmit, and master reset), and flags (i.e., Empty/Full, Half
Full, and Programmable Almost Full/Empty).
The retransmit methodology is as follows: mark the current
value of the read pointer, after an error in subsequent read
operations return to that location and resume reading. This
effectively resends all of the data from the mark point. When
MARK is LOW, the current value of the read pointer is stored. This
operation marks the beginning of the packet to be resent. When RT
is LOW, the read pointer is updated with the mark location. During
each subsequent read cycle, data is read and the read pointer incremented.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition signified by the Empty flag (E/F) and Almost Full/Empty flag (PAFE) being
LOW, and Half Full flag (HF) being HIGH. The read pointer, write
pointer, and retransmit pointer are reset to zero. For a valid reset,
Read (R) and Write (W) must be HIGH tRPW/tWPW before the falling
edge and tRMR after the rising edge of MR.
Care must be taken when using the retransmit feature. Use the
mark function such that the write pointer does not pass the
mark pointer, because further write operations will overwrite
data.
Writing Data to the FIFO
Data can be written to the FIFO when it is not FULL[11]. A falling
edge of W initiates a write cycle. Data appearing at the inputs (D0–D8)
tSD before and tHD after the rising edge of W will be stored sequentially in the FIFO.
Programmable Almost Full/Empty Flag
The CY7C470/2/4 offer a variable offset for the Almost Empty
and the Almost Full condition. The offset is loaded into the
programmable flag register (PFR) during a master reset cycle.
While MR is LOW, the PFR can be loaded from Q8–Q0 by pulsing
R LOW or from D8–D0 by pulsing W LOW. The offset options are
listed in Table 2. See Table 1 for a description of the six FIFO states.
If the PFR is not loaded during master reset (R and W HIGH) the
default offset will be 256 words from Full and Empty.
Reading Data from the FIFO
Data can be read from the FIFO when it is not empty[12]. A
falling edge of R initiates a read cycle. Data outputs (Q0–Q8) are in a
high-impedance condition when the FIFO is empty and between read
operations (R HIGH). The falling edge of R during the last read cycle
before the empty condition triggers a high-to-low transition of E/F, prohibiting any further read operations until tRFF after a valid write.
Notes:
11. When the FIFO is less than half full, the flags make a LOW-to-HIGH transition on the rising edge of W and make the HIGH-to-LOW transition on the falling edge
of R. If the FIFO is more than half full, the flags make the LOW-to-HIGH transition on the rising edge of R and HIGH-to-LOW transition on the falling edge of W.
12. Full and empty states can be decoded from the Half-Full (HF) and Empty/Full (E/F) flags.
9
CY7C470
CY7C472
CY7C474
Table 1. Flag Truth Table[13]
CY77C470
(8K x 9)
Number of Words
in FIFO
HF
E/F
PAFE
State
1
0
0
Empty
1
1
0
Almost Empty
1
1
1
Less than Half Full
0
1
1
Greater than Half Full
0
1
0
Almost Full
0
0
0
Full
CY77C472
(16K x 9)
Number of Words in
FIFO
CY77C474
(32K x 9)
Number of Words in
FIFO
0
0
0
1 ⇒(P – 1)
1 ⇒ (P – 1)
1 ⇒ (P – 1)
P ⇒ 4096
P ⇒ 8192
P ⇒ 16384
4097 ⇒ (8192 – P)
8193 ⇒ (16384 – P)
16385 ⇒ (32768 – P)
(8192 – P+1) ⇒ 8191
(16384 – P+1) ⇒ 16383
(32768 – P+1) ⇒ 32767
8192
16384
32768
Table 2. Programmable Almost Full/Empty Options[14]
D3
D2
D1
D0
0
0
0
0
256 or less locations from Empty/Full (default)
256
0
0
0
1
16 or less locations from Empty/Full
16
0
0
1
0
32 or less locations from Empty/Full
32
0
0
1
1
64 or less locations from Empty/Full
64
0
1
0
0
128 or less locations from Empty/Full
128
0
1
0
1
256 or less locations from Empty/Full (default)
256
0
1
1
0
512 or less locations from Empty/Full
512
0
1
1
1
1024 or less locations from Empty/Full
1024
1
0
0
0
2048 or less locations from Empty/Full
2048
1
0
0
1
4098 or less locations from Empty/Full[15]
4098
0
Empty/Full[16]
8192
1
0
1
PAFE Active when:
P
8192 or less locations from
Notes:
13. See Table 2 for P values.
14. Almost flags default to 256 locations from Empty/Full.
15. Only for CY7C472 and CY7C474.
16. Only for CY7C470.
10
CY7C470
CY7C472
CY7C474
Typical AC and DC Characteristics
NORMALIZED tA vs. AMBIENT
TEMPERATURE
NORMALIZED tA vs.SUPPLY
VOLTAGE
TYPICAL tA CHANGE vs.
OUTPUT LOADING
1.60
1.20
20.00
1.40
1.10
15.00
1.20
1.00
10.00
1.00
0.90
0.80
4.00
TA =25°C
4.50
5.00
5.50
0.60
–55.00
6.00
5.00
65.00
125.00
VCC =5.0V
TA =25°C
0.00
0.00
CAPACITANCE (pF)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs.FREQUENCY
1.40
1.20
1.20
1.10
1.00
1.00
1.10
1.00
0.90
VIN =3.0V
TA =25°C
f = 33 MHz
0.80
0.60
4.00
4.50
5.00
0.80
–55.00
6.00
SUPPLY VOLTAGE (V)
5.00
0.70
65.00
100.00
40.00
80.00
30.00
60.00
20.00
40.00
VCC =5.0V
TA =25°C
1.00
0.60
15.00
3.00
25.00
0.00
0.00
4.00
OUTPUT VOLTAGE (V)
VCC =5.0V
TA =25°C
1.00
2.00
3.00
OUTPUT VOLTAGE (V)
11
30.00
FREQUENCY (MHz)
20.00
2.00
20.00
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
50.00
0.00
0.00
125.00
AMBIENT TEMPERATURE (°C)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
10.00
VCC =5.0V
TA =25°C
VIN =3.0V
0.80
VIN =3.0V
TA =25°C
f = 33 MHz
0.90
5.50
1000.00
500.00
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE(V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
5.00
VCC =5.0V
0.80
4.00
35.00
CY7C470
CY7C472
CY7C474
Ordering Information
Speed
(ns)
15
20
25
40
Speed
(ns)
15
20
25
40
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C470–15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C470–15PC
P15
28-Lead (600-Mil) Molded DIP
CY7C470–15JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C470–20DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C470–20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C470–25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C470–25PC
P15
28-Lead (600-Mil) Molded DIP
CY7C470–25JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C470–25DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C470–25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C470–40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C470–40PC
P15
28-Lead (600-Mil) Molded DIP
CY7C470–40JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C470–40DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C470–40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Package
Name
Package Type
Ordering Code
Commercial
Commercial
Commercial
Operating
Range
CY7C472–15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C472–15PC
P15
28-Lead (600-Mil) Molded DIP
CY7C472–15JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C472–20DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C472–20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C472–25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C472–25PC
P15
28-Lead (600-Mil) Molded DIP
CY7C472–25JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C472–25DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C472–25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C472–40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C472–40PC
P15
28-Lead (600-Mil) Molded DIP
CY7C472–40JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C472–40DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C472–40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
12
Commercial
Commercial
Commercial
CY7C470
CY7C472
CY7C474
Ordering Information (continued)
Speed
(ns)
Ordering Code
15
20
25
40
Package
Name
Operating
Range
Package Type
CY7C474–15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C474–15PC
P15
28-Lead (600-Mil) Molded DIP
Commercial
CY7C474–15JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C474–20DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C474–20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C474–25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C474–25PC
P15
28-Lead (600-Mil) Molded DIP
CY7C474–25JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C474–25DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C474–25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C474–40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C474–40PC
P15
28-Lead (600-Mil) Molded DIP
CY7C474–40JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C474–40DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C474–40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Commercial
Commercial
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
1, 2, 3
tCY
9, 10, 11
VOL
1, 2, 3
tA
9, 10, 11
VIH
1, 2, 3
tRV
9, 10, 11
VIL Max.
1, 2, 3
tPW
9, 10, 11
IIX
1, 2, 3
tLZR
9, 10, 11
IOS
1, 2, 3
tDVR
9, 10, 11
ICC
1, 2, 3
tHZR
9, 10, 11
tHWZ
9, 10, 11
tSD
9, 10, 11
tHD
9, 10, 11
tEFD
9, 10, 11
tHFD
9, 10, 11
tAFED
9, 10, 11
tRAE
9, 10, 11
tWAF
9, 10, 11
Document #: 38–00142–H
13
CY7C470
CY7C472
CY7C474
Package Diagrams
28-Lead (600-Mil) Sidebraze DIP D43
32-Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
32-Lead Plastic Leaded Chip Carrier
14
CY7C470
CY7C472
CY7C474
Package Diagrams
28-Lead (600-Mil) Molded DIP P15
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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