Cypress CYNSE70064A-66BGC Search engine Datasheet

CYNSE70064A
CYNSE70064A Network
Search Engine
Cypress Semiconductor Corporation
Document #: 38-02041 Rev. *E
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3901 North First Street
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San Jose, CA 95134
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408-943-2600
Revised May 6, 2003
CYNSE70064A
TABLE OF CONTENTS
1.0 FEATURES ...................................................................................................................................... 9
2.0 FUNCTIONAL OVERVIEW .............................................................................................................. 9
3.0 PRODUCT SUMMARY .................................................................................................................. 10
3.1 Logic Block Diagram ................................................................................................................. 10
4.0 FUNCTIONAL DESCRIPTION ....................................................................................................... 10
4.1 CMD Bus and DQ Bus .............................................................................................................. 10
4.2 Database Entry (Data Array and Mask Array) .......................................................................... 10
4.3 Arbitration Logic ........................................................................................................................ 10
4.4 Pipeline and SRAM Control ...................................................................................................... 11
4.5 Full Logic ................................................................................................................................... 11
5.0 SIGNAL DESCRIPTIONS .............................................................................................................. 11
6.0 CLOCKS ......................................................................................................................................... 13
7.0 REGISTERS ................................................................................................................................... 13
7.1 Comparand Registers ............................................................................................................... 13
7.2 Mask Registers ......................................................................................................................... 14
7.3 Search Successful Registers (SSR[0:7]) .................................................................................. 14
7.4 Command Register ................................................................................................................... 14
7.5 Information Register .................................................................................................................. 15
7.6 Read Burst Address Register ................................................................................................... 16
7.7 Write Burst Address Register Description ................................................................................. 16
7.8 NFA Register ............................................................................................................................ 16
8.0 NSE ARCHITECTURE AND OPERATION OVERVIEW ............................................................... 17
9.0 DATA AND MASK ADDRESSING ................................................................................................ 18
10.0 COMMANDS ................................................................................................................................ 18
10.1 Command Codes .................................................................................................................... 18
10.2 Commands and Command Parameters ................................................................................. 18
10.3 Read Command ...................................................................................................................... 19
10.4 Write Command ...................................................................................................................... 21
10.5 Search Command ................................................................................................................... 23
10.6 68-bit Search on Tables Configured as ×68 using a Single CYNSE70064A Device .............. 23
10.7 68-bit Search on Tables Configured as ×68 Using up to Eight CYNSE70064A Devices ....... 25
10.8 68-bit Search on Tables Configured as ×68 Using up to 31 CYNSE70064A Devices ........... 32
10.9 136-bit Search on Tables Configured as ×136 Using a Single CYNSE70064A Device ......... 47
10.10 136-bit Search on Tables Configured as ×136 Using up to Eight CYNSE70064A Devices . 49
10.11 136-bit Search on Tables Configured as ×136 Using up to 31 CYNSE70064A Devices ..... 55
10.12 272-bit Search on Tables Configured as û272 Using a Single CYNSE70064A Device ....... 70
10.13 272-bit Search on Tables x272-configured Using up to Eight CYNSE70064A Devices ....... 72
10.14 272-bit Search on Tables Configured as ×272 Using up to 31 CYNSE70064A Devices ..... 77
10.15 Mixed-Sized Searches on Tables Configured with Different Widths Using a
CYNSE70064A Device ................................................................................................................... 92
10.16 LRAM and LDEV Description ................................................................................................ 93
10.17 Learn Command ................................................................................................................... 94
11.0 DEPTH-CASCADING ................................................................................................................... 98
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CYNSE70064A
TABLE OF CONTENTS (continued)
11.1 Depth-Cascading up to Eight Devices (One Block) ................................................................ 98
11.2 Depth-Cascading up to 31 Devices (Four Blocks) .................................................................. 99
11.3 Depth-Cascading for a FULL Signal ....................................................................................... 99
12.0 SRAM ADDRESSING ................................................................................................................ 100
12.1 Generating an SRAM BUS Address .....................................................................................101
12.2 SRAM PIO Access ................................................................................................................ 101
12.3 SRAM Read with a Table of One Device .............................................................................. 101
12.4 SRAM Read with a Table of up to Eight Devices .................................................................. 102
12.5 SRAM Read with a Table of up to 31 Devices ...................................................................... 105
12.6 SRAM Write with a Table of One Device .............................................................................. 108
12.7 SRAM Write with a Table of up to Eight Devices .................................................................. 109
12.8 SRAM Write with Table(s) of up to 31 Devices ..................................................................... 112
13.0 POWER ...................................................................................................................................... 116
13.1 The Proper Power-up Sequence .......................................................................................... 116
14.0 APPLICATION ........................................................................................................................... 116
15.0 JTAG (1149.1) TESTING ........................................................................................................... 117
16.0 ELECTRICAL SPECIFICATIONS ..............................................................................................118
17.0 AC TIMING WAVEFORMS ........................................................................................................ 119
18.0 PINOUT DESCRIPTIONS AND PACKAGE DIAGRAMS .......................................................... 121
19.0 ORDERING INFORMATION ...................................................................................................... 125
20.0 PACKAGE DIAGRAM ................................................................................................................ 126
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CYNSE70064A
LIST OF FIGURES
Figure 6-1. CYNSE70064A Clocks (CLK2X and PHS_L) ..................................................................... 13
Figure 7-1. Comparand-Register Selection During Search and Learn Instructions .............................. 13
Figure 7-2. Addressing the Global Masks Register Array ..................................................................... 14
Figure 8-1. CYNSE70064A Database WIDTH Configuration ............................................................... 17
Figure 8-2. Multiwidth Database Configurations Example .................................................................... 17
Figure 9-1. Addressing of the CYNSE70064A Data and Mask Arrays ................................................. 18
Figure 10-1. Single-Location Read Cycle Timing ................................................................................. 19
Figure 10-2. Burst Read of the Data and Mask Arrays (BLEN = 4) ...................................................... 20
Figure 10-3. Single Write Cycle Timing ................................................................................................ 21
Figure 10-4. Burst Write of the Data and Mask Arrays (BLEN = 4) ...................................................... 22
Figure 10-5. Timing Diagram for 68-bit Search in x68 Table (One Device) .......................................... 24
Figure 10-6. Hardware Diagram for 68-bit Search in x68 Table (One Device) ..................................... 24
Figure 10-7. ×68 Table with One Device .............................................................................................. 25
Figure 10-8. Hardware Diagram for a Table With Eight Devices .......................................................... 27
Figure 10-9. Timing Diagram for 68-bit Search Device Number 0 ........................................................ 28
Figure 10-10. Timing Diagram for 68-bit Search Device Number 1 ...................................................... 29
Figure 10-11. Timing Diagram for 68-bit Search Device Number 7 (Last Device) ............................... 30
Figure 10-12. x68 Table with Eight Devices ......................................................................................... 31
Figure 10-13. Hardware Diagram for a Table with 31 Devices ............................................................. 33
Figure 10-14. Hardware Diagram for a Block of up to Eight Devices ................................................... 34
Figure 10-15. Timing Diagram for Each Device In Block Number 0 (Miss on Each Device) ................ 35
Figure 10-16. Timing Diagram for Each Device Above the Winning Device in Block Number 1 .......... 36
Figure 10-17. Timing Diagram for Globally Winning Device in Block Number 1 .................................. 37
Figure 10-18. Timing Diagram for Devices Below the Winning Device in Block Number 1 .................. 38
Figure 10-19. Timing Diagram for Devices Above the Winning Device in Block Number 2 ................. 39
Figure 10-20. Timing Diagram for Globally Winning Device in Block Number 2 .................................. 40
Figure 10-21. Timing Diagram for Devices Below the Winning Device in Block Number 2 .................. 41
Figure 10-22. Timing Diagram for Devices Above the Winning Device in Block Number 3 ................. 42
Figure 10-23. Timing Diagram for Globally Winning Device in Block Number 3 .................................. 43
Figure 10-24. Timing Diagram for Devices Below the Winning Device in Block Number 3
(Except the Last Device [Device 30]) .................................................................................................... 44
Figure 10-25. Timing Diagram for Device Number 6 in Block Number 3
(Device 30 in Depth-Cascaded Table) .................................................................................................. 45
Figure 10-26. ×68 Table with 31 Devices ............................................................................................. 46
Figure 10-27. Timing Diagram for 136-bit Search (One Device) .......................................................... 47
Figure 10-28. Hardware Diagram for a Table with One Device ............................................................ 47
Figure 10-29. ×136 Table with One Device .......................................................................................... 48
Figure 10-30. Hardware Diagram for a Table with Eight Devices ......................................................... 50
Figure 10-31. Timing Diagram for 136-bit Search Device Number 0 .................................................... 51
Figure 10-32. Timing Diagram for 136-bit Search Device Number 1 .................................................... 52
Figure 10-33. Timing Diagram for 136-bit Search Device Number 7 (Last Device) ............................. 53
Figure 10-34. ×136 Table with Eight Devices ....................................................................................... 54
Figure 10-35. Hardware Diagram for a Table with 31 Devices ............................................................. 56
Figure 10-36. Hardware Diagram for a Block of Up to Eight Devices ................................................... 57
Figure 10-37. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) ................ 58
Figure 10-38. Timing Diagram for Each Device Above the Winning Device in Block Number 1 .......... 59
Figure 10-39. Timing Diagram for Globally Winning Device in Block Number 1 .................................. 60
Figure 10-40. Timing Diagram for Devices Below the Winning Device in Block Number 1 .................. 61
Figure 10-41. Timing Diagram for Devices Above the Winning Device in Block Number 2 ................. 62
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CYNSE70064A
LIST OF FIGURES (continued)
Figure 10-42. Timing Diagram for Globally Winning Device in Block Number 2 .................................. 63
Figure 10-43. Timing Diagram for Devices Below the Winning Device in Block Number 2 .................. 64
Figure 10-44. Timing Diagram for Devices Above the Winning Device in Block Number 3 ................. 65
Figure 10-45. Timing Diagram for Globally Winning Device in Block Number 3 .................................. 66
Figure 10-46. Timing Diagram for Devices Below the Winning Device in Block Number 3
Except Device 30 (the Last Device) ...................................................................................................... 67
Figure 10-47. Timing Diagram for Device Number 6 in Block Number 3
(Device 30 in Depth-Cascaded Table) .................................................................................................. 68
Figure 10-48. ×136 Table with 31 Devices ........................................................................................... 69
Figure 10-49. Timing Diagram for 272-bit Search (One Device) .......................................................... 70
Figure 10-50. Hardware Diagram for a Table with One Device ............................................................ 70
Figure 10-51. ×272 Table with One Device .......................................................................................... 71
Figure 10-52. Hardware Diagram for a Table with Eight Devices ......................................................... 73
Figure 10-53. Timing Diagram for 272-bit Search Device Number 0 .................................................... 74
Figure 10-54. Timing Diagram for 272-bit Search Device Number 1 .................................................... 75
Figure 10-55. Timing Diagram for 272-bit Search Device Number 7 (Last Device) ............................. 76
Figure 10-56. ×272 Table with Eight Devices ....................................................................................... 77
Figure 10-57. Hardware Diagram for a Table with 31 Devices ............................................................. 79
Figure 10-58. Hardware Diagram for A Block of up to Eight Devices ................................................... 80
Figure 10-59. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) ................ 81
Figure 10-60. Timing Diagram for Each Device Above the Winning Device in Block Number 1 .......... 82
Figure 10-61. Timing Diagram for Globally Winning Device in Block Number 1 .................................. 83
Figure 10-62. Timing Diagram for Devices Below the Winning Device in Block Number 1 .................. 84
Figure 10-63. Timing Diagram for Devices Above the Winning Device in Block Number 2 ................. 85
Figure 10-64. Timing Diagram for Globally Winning Device in Block Number 2 .................................. 86
Figure 10-65. Timing Diagram for Devices Below the Winning Device in Block Number 2 .................. 87
Figure 10-66. Timing Diagram for Devices Above the Winning Device in Block Number 3 ................. 88
Figure 10-67. Timing Diagram for Globally Winning Device in Block Number 3 .................................. 89
Figure 10-68. Timing Diagram for Devices Below the Winning Device in Block Number 3
Except Device 30 (the Last Device) ...................................................................................................... 90
Figure 10-69. Timing Diagram of the Last Device in Block Number 3 (Device 30 in the Table) ........... 91
Figure 10-70. ×272 Table with 31 Devices ........................................................................................... 92
Figure 10-71. Timing Diagram for Mixed Search (One Device) ............................................................ 93
Figure 10-72. Multiwidth Configurations Example ................................................................................ 93
Figure 10-73. Timing Diagram of Learn (TLSZ = 00) ............................................................................ 95
Figure 10-74. Timing Diagram of Learn (Except on the Last Device [TLSZ = 01]) ............................... 96
Figure 10-75. Timing Diagram of Learn on Device Number 7 (TLSZ = 01) .......................................... 97
Figure 11-1. Depth-Cascading to Form a Single Block ........................................................................ 98
Figure 11-2. Depth-Cascading Four Blocks .......................................................................................... 99
Figure 11-3. Full Generation in a Cascaded Table ............................................................................. 100
Figure 12-1. SRAM Read Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1) .......................... 102
Figure 12-2. Table of a Block of Eight Devices ................................................................................... 103
Figure 12-3. SRAM Read Through Device Number 0 in a Block of Eight Devices ............................. 104
Figure 12-4. SRAM Read Timing for Device Number 7 in a Block of Eight Devices .......................... 105
Figure 12-5. Table of 31 Devices Made of Four Blocks ...................................................................... 106
Figure 12-6. SRAM Read Through Device Number 0 in a Bank of 31 Devices
(Device Number 0 Timing) .................................................................................................................. 107
Figure 12-7. SRAM Read Through Device Number 0 in Bank of 31 Devices
(Device Number 30 Timing) ................................................................................................................ 108
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CYNSE70064A
LIST OF FIGURES (continued)
Figure 12-8. SRAM Write Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1) .......................... 109
Figure 12-9. Table of a Block of Eight Devices ................................................................................... 110
Figure 12-10. SRAM Write Through Device Number 0 in a Block of Eight Devices ........................... 111
Figure 12-11. SRAM Write Timing for Device Number 7 in Block of Eight Devices ........................... 112
Figure 12-12. Table of 31 Devices (Four Blocks) ............................................................................... 113
Figure 12-13. SRAM Write Through Device Number 0 in Bank
of 31 Devices (Device 0 Timing) ......................................................................................................... 114
Figure 12-14. SRAM Write Through Device Number 0 in Bank
of 31 CYNSE70064A Devices (Device Number 30 Timing) ............................................................... 115
Figure 13-1. Power-up Sequence ....................................................................................................... 116
Figure 14-1. Sample Switch/Router Using the CYNSE70064A Device .............................................. 117
Figure 17-1. Input Waveform for CYNSE70064A ............................................................................... 119
Figure 17-2. Output Load for CYNSE70064A ..................................................................................... 119
Figure 17-3. 2.5 I/O Output Load Equivalent for CYNSE70064A ....................................................... 120
Figure 17-4. AC Timing Wave Forms with CLK2X ............................................................................. 120
Figure 18-1. Pinout Diagram ............................................................................................................... 121
Figure 20-1. Package ......................................................................................................................... 126
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CYNSE70064A
LIST OF TABLES
Table 5-1. CYNSE70064A Signal Description ...................................................................................... 11
Table 7-1. Register Overview ............................................................................................................... 13
Table 7-2. Search Successful Register Description ............................................................................. 14
Table 7-3. Command Register Description ........................................................................................... 14
Table 7-4. Information Register Description ......................................................................................... 15
Table 7-5. Read Burst Register Description ......................................................................................... 16
Table 7-6. Write Burst Register Description ......................................................................................... 16
Table 7-7. NFA Register ....................................................................................................................... 16
Table 8-1. Bit Position Match ................................................................................................................ 17
Table 10-1. Command Codes ............................................................................................................... 18
Table 10-2. Command Parameters ...................................................................................................... 18
Table 10-3. Read Command Parameters ............................................................................................. 19
Table 10-4. Read Address Format for Data Array, Mask Array, or SRAM ........................................... 20
Table 10-5. Read Address Format for Internal Registers ..................................................................... 20
Table 10-6. Read Address Format for Data and Mask Arrays .............................................................. 21
Table 10-7. Write Address Format for Data Array, Mask Array, or SRAM (Single Write) ..................... 22
Table 10-8. Write Address Format for Internal Registers ..................................................................... 22
Table 10-9. Write Address Format for Data and Mask Array (Burst Write) .......................................... 23
Table 10-10. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 25
Table 10-11. Shift of SSF and SSV from SADR ................................................................................... 25
Table 10-12. Hit/Miss Assumption ........................................................................................................ 26
Table 10-13. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 31
Table 10-14. Shift of SSF and SSV from SADR ................................................................................... 31
Table 10-15. Hit/Miss Assumptions ...................................................................................................... 32
Table 10-16. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 46
Table 10-17. Shift of SSF and SSV from SADR ................................................................................... 46
Table 10-18. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 48
Table 10-19. Shift of SSF and SSV from SADR ................................................................................... 48
Table 10-20. Hit/Miss Assumption ........................................................................................................ 49
Table 10-21. Search Latency from Instruction to SRAM Access Cycle ................................................ 54
Table 10-22. Shift of SSF and SSV from SADR ................................................................................... 54
Table 10-23. Hit/Miss Assumption ........................................................................................................ 55
Table 10-24. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 69
Table 10-25. Shift of SSF and SSV from SADR ................................................................................... 69
Table 10-26. The Latency of Search from C and D Cycles to SRAM Access Cycle ............................ 71
Table 10-27. Shift of SSF and SSV from SADR ................................................................................... 71
Table 10-28. Hit/Miss Assumption ........................................................................................................ 72
Table 10-29. The Latency of Search from C and D cycles to SRAM Access Cycle ............................. 77
Table 10-30. Shift of SSF and SSV from SADR ................................................................................... 77
Table 10-31. Hit/Miss Assumption ........................................................................................................ 78
Table 10-32. The Latency of Search from C and D cycles to SRAM Access Cycle ............................. 92
Table 10-33. Shift of SSF and SSV from SADR ................................................................................... 92
Table 10-34. The Latency of SRAM Write Cycle from Second Cycle of Learn Instruction ................... 97
Table 12-1. SRAM Bus Address .........................................................................................................101
Table 15-1. Supported Operations ..................................................................................................... 117
Table 15-2. TAP Device ID Register ................................................................................................... 117
Table 16-1. DC Electrical Characteristics for CYNSE70064A ............................................................ 118
Table 16-2. Operating Conditions for CYNSE70064A ........................................................................118
Table 17-1. AC Timing Parameters with CLK2X ................................................................................ 119
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CYNSE70064A
LIST OF TABLES (continued)
Table 17-2. 2.5V AC Table for Test Condition of CYNSE70064A ...................................................... 119
Table 18-1. Pinout Descriptions for Pinout Diagram ........................................................................... 122
Table 19-1. Ordering Information ........................................................................................................ 125
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CYNSE70064A
1.0
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Features
64K 34-bit entries in a single device
32K entries in 68-bit mode, 16K entries in 136-bit mode, 8K entries in 272-bit mode
83 million transactions per second in 68- and 136-bit configurations
41.5 million transactions in 34- and 272-bit configurations
Searches any subfield in a single cycle
Synchronous pipelined operation
Up to 31 search engines can be cascaded
When cascaded, the database entries can range up to 1984K 34-bit entries
Multiple width tables in a single database bank
Glueless interface to industry-standard SRAMs and/or SSRAMs
Simple hardware instruction interface
IEEE 1149.1 test access port
1.8V core voltage supply
2.5/3.3V I/O voltage supply
272-pin BGA package.
2.0
Functional Overview
Cypress Semiconductor Corporation’s (Cypress’s) CYNSE70064A network search engine (NSE) incorporates patent-pending
Associative Processing Technology™ (APT) and is designed to be a high-performance, pipelined, synchronous, 32K-entry NSE.
The CYNSE70064A database entry size can be 68 bits, 136 bits, or 272 bits. In the 68-bit entry mode, the size of the database
is 32K entries. In the 136-bit mode, the size of the database is 16K entries, and in the 272-bit mode, the size of the database is
8K entries. The CYNSE70064A is configurable to support multiple databases with different entry sizes. The 34-bit entry table can
be implemented using the global mask registers (GMRs) building-database size of 64K entries with a single device.
The NSE can sustain 83 million transactions per second when the database is programmed or configured as 68 or 136 bits. When
the database is programmed to have an entry size of 34 or 272 bits, the NSE will perform at 41.5 million transactions per second.
The CYNSE70064A device can be used to accelerate network protocols such as longest-prefix match (CIDR), ARP, MPLS, and
other layer 2, 3, and 4 protocols.
This high-speed, high-capacity NSE can be deployed in a variety of networking and communications applications. The performance and features of the CYNSE70064A make it attractive in applications such as Enterprise LAN switches and routers and
broadband switching and/or routing equipment supporting multiple data rates at OC-48 and beyond. The NSE is designed to be
scalable in order to support network database sizes to 1984K entries specifically for environments that require large network
policy databases.
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CYNSE70064A
3.0
Product Summary
3.1
Logic Block Diagram
Comparand Register Pairs [15:0]
Global Mask Register Pairs [7:0]
Information and Command Register
Burst Read Register
Burst Write Register
Next-Free Address Register
Search Successful Index Registers [7:0]
[All registers are 68 bits wide.]
PHS_L
CLK2X
DQ[67:0]
Compare/PIO Data
RST_L
TAP
Controller
TAP
SADR[21:0]
ACK
EOT
Command
Decode
and PIO Access
Configurable as
32K × 68
16K × 136
8K × 272
Data Array
Configurable as
32K × 68
16K × 136
8K × 272
Mask Array
Pipeline
Priority Encode
Match Logic
CMD[8:0]
CMDV
Address Decode
CMDCompare/PIO Data
and
SRAM
Control
OE_L
WE_L
CE_L
ALE_L
ID[4:0]
LHI[6:0]
Arbitration
FULI[6:0]
BHI[2:0]
Full Logic
FULL
4.0
FULO[1:0]
Logic
LHO[1:0]
BHO[2:0]
SSF
SSV
Functional Description
The following subsections contain command (CMD) and DQ bus (command and databus), database entry, arbitration logic,
pipeline and SRAM control, and full logic descriptions.
4.1
CMD Bus and DQ Bus
CMD[8:0] carries the CMD and its associated parameter. DQ[67:0] is used for data transfer to and from the database entries,
which comprise a data and a mask field that are organized as data and mask arrays. The DQ bus carries the Search data (of the
data and mask arrays and internal registers) during the Search command as well as the address and data during Read and/or
Write operations. The DQ bus can also carry the address information for the flow-through accesses to the external SRAMs and/or
SSRAMs.
4.2
Database Entry (Data Array and Mask Array)
Each database entry comprises a data and a mask field. The resultant value of the entry is “1,” “0,” or “X (don’t care),” depending
on the value in the data and mask bits. The on-chip priority encoder selects the first matching entry in the database that is nearest
to location 0.
4.3
Arbitration Logic
When multiple search engines are cascaded to create large databases, the data being searched is presented to all search engines
simultaneously in the cascaded system. If multiple matches occur within the cascaded devices, arbitration logic on the search
engines will enable the winning device (with a matching entry that is closest to address 0 of the cascaded database) to drive the
SRAM bus.
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CYNSE70064A
4.4
Pipeline and SRAM Control
Pipeline latency is added to give enough time to a cascaded system’s arbitration logic to determine the device that will drive the
index of the matching entry on the SRAM bus. Pipeline logic adds latency to both the SRAM access cycles and the SSF and SSV
signals to align them to the host ASIC receiving the associated data.
4.5
Full Logic
Bit[0] in each of the 68-bit entries has a special purpose for the Learn command (0 = empty, 1 = full). When all the data entries
have bit[0] = 1, the database asserts the FULL flag, indicating that all the search engines in the depth-cascaded array are full.
5.0
Signal Descriptions
Table 5-1 lists and describes all CYNSE70064A signals.
Table 5-1. CYNSE70064A Signal Description
Type[1]
Description
CLK2X
I
Master Clock. CYNSE70064A samples all the data and control pins on the positive edge of
CLK2X. All signals are driven out of the device on the rising edge of CLK2X (when PHS_L is
LOW).
PHS_L
I
Phase. This signal runs at half the frequency of CLK2X and generates an internal CLK[2] from
CLK2X. See Section 6.0, “Clocks” on page 13.
RST_L
I
Reset. Driving RST_L LOW initializes the device to a known state.
CMD[8:0]
I
CMD Bus. [1:0] specifies the command and [8:2] contains the CMD parameters. The descriptions of individual commands explains the details of the parameters. The encoding of
commands based on the [1:0] field are:
00: PIO Read
01: PIO Write
10: Search
11: Learn.
CMDV
I
CMD Valid. This signal qualifies the CMD bus:
0: No command
1: Command.
DQ[67:0]
I/O
Address/Data Bus. This signal carries the Read and Write address and data during register,
data, and mask array operations. It carries the compare data during Search operations. It also
carries the SRAM address during SRAM PIO accesses.
ACK[3]
T
Read Acknowledge. This signal indicates that valid data is available on the DQ bus during
register, data, and mask array Read operations, or that the data is available on the SRAM
data bus during SRAM Read operations.
EOT[3]
T
End of Transfer. This signal indicates the end of burst transfer to the data or mask array
during Read or Write burst operations.
SSF
T
Search Successful Flag. When asserted, this signal indicates that the device is the global
winner in a Search operation.
SSV
T
Search Successful Flag Valid. When asserted, this signal qualifies the SSF signal.
SADR[21:0]
T
SRAM Address. This bus contains address lines to access off-chip SRAMs that contain
associative data. See Table 12-1 for the details of the generated SRAM address. In a
database of multiple CYNSE70064As, each corresponding bit of SADR from all cascaded
devices must be connected.
CE_L
T
SRAM Chip Enable. This is the chip-enable control for external SRAMs. In a database of
multiple CYNSE70064As, CE_L of all cascaded devices must be connected. This signal is
then driven by only one of the devices.
Symbol
Clocks and Reset
CMD and DQ Bus
SRAM Interface
Notes:
1. I = Input only, I/O = Input or Output, O = Output only, T = three-state output.
2. CLK” is an internal clock signal. Any reference to “CLK cycles” means one cycle of CLK.
3. ACK and EOT require a weak external pull-down such as 47KΩ or 100KΩ.
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CYNSE70064A
Table 5-1. CYNSE70064A Signal Description (continued)
Symbol
Type[1]
Description
WE_L
T
SRAM Write Enable. This is the Write-enable control for external SRAMs. In a database of
multiple CYNSE70064As, WE_L of all cascaded devices must be connected together. This
signal is then driven by only one of the devices.
OE_L
T
SRAM Output Enable. This is the output-enable control for external SRAMs. Only the last
device drives this signal (with the LRAM bit set).
ALE_L
T
Address Latch Enable. When this signal is LOW, the addresses are valid on the SRAM
address bus. In a database of multiple CYNSE70064As, the ALE_L of all cascaded devices
must be connected. This signal is then driven by only one of the devices.
LHI[6:0]
I
Local Hit In. These pins depth-cascade the device to form a larger table. One signal of this
bus is connected to the LHO[1] or LHO[0] of each of the upstream devices in a block. All
unused LHI pins are connected to a logic 0. (For more information, see Section 11.0,
“Depth-Cascading” on page 97.)
LHO[1:0]
O
Local Hit Out. LHO[1] and LHO[0] are the same logical signal. Either the LHO[1] or the LHO[0]
is connected to one input of the LHI bus of up to four downstream devices in a block of up to
eight. (For more information see Section 11.0, “Depth-Cascading” on page 97.)
BHI[2:0]
I
Block Hit In. Inputs from the previous block BHO[2:0] are tied to BHI[2:0] of the current device.
In a four-block system, the last block can contain only seven devices because the identification code 11111 is used for broadcast access.
BHO[2:0]
O
Block Hit Out. These outputs from the last device in a block are connected to the BHI[2:0]
inputs of the devices in the downstream blocks.
FULI[6:0]
I
Full In. Each signal in this bus is connected to FULO[0] or FULO[1] of an upstream device to
generate the FULL flag for the depth-cascaded block.
FULO[1:0]
O
Full Out. FULO[1] and FULO[0] are the same logical signal. One of these two signals must
be connected to the FULI of up to four downstream devices in a depth-cascaded table. Bit [0]
in the data array indicates whether the entry is full (1) or empty (0).This signal is asserted if
all bits in the data array are ones. (Refer to Section 11.0, “Depth-Cascading” on page 97, for
information on how to generate the FULL flag.)
FULL
O
Full Flag. When asserted, this signal indicates that the table of multiple depth-cascaded
devices is full.
I
Device Identification. The binary-encoded device identification for a depth-cascaded
system starts at 00000 and goes up to 11110. 11111 is reserved for a special broadcast
address that selects all cascaded search engines in the system. On a broadcast Read-only,
the device with the LDEV bit set to 1 responds.
Cascade Interface
Device Identification
ID[4:0]
Supplies
VDD
n/a
Chip Core Supply. 1.8V.
VDDQ
n/a
Chip I/O supply. 2.5V or 3.3V.
Test Access Port
TDI
I
Test access port’s test data in.
TCK
I
Test access port’s test clock.
TDO
T
Test access port’s test data out.
TMS
I
Test access port’s Test Mode Select.
TRST_L
I
Test access port’s Reset.
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CYNSE70064A
6.0
Clocks
CYNSE70064A receives the CLK2X and PHS_L signals. It uses the PHS_L signal to divide CLK2X and generate an internal
CLK, as shown in Figure 6-1. The CYNSE70064A uses CLK2X and CLK for internal operations.
CLK2X
PHS_L
CLK
Figure 6-1. CYNSE70064A Clocks (CLK2X and PHS_L)
7.0
Registers
All registers in the CYNSE70064A are 68 bits wide. The CYNSE70064A contains 16 pairs of comparand storage registers, eight
pairs of GMRs, eight search successful index registers and one each of CMD, information, burst Read, burst Write, and next-free
address registers. Table 7-1 provides an overview of all the CYNSE70064A registers. The registers are ordered in ascending
address order. Each register group is then described in the following subsections.
Table 7-1. Register Overview
7.1
Address
Abbreviation
Type
Name
0–31
COMP0–31
R
Sixteen pairs of comparand registers that store comparands from the
DQ bus for learning later.
32–47
MASKS
RW
48–55
SSR0–7
R
56
COMMAND
RW
Command register.
57
INFO
R
Information register.
Eight global mask register pairs.
Eight search successful index registers.
58
RBURREG
RW
Burst Read register.
59
WBURREG
RW
Burst Write register.
60
NFA
R
Next-free address register.
61–63
–
–
Reserved.
Comparand Registers
The device contains 32 68-bit comparand registers (16 pairs) dynamically selected in every Search operation to store the
comparand presented on the DQ bus. The Learn command will later use these registers when executed. The CYNSE70064A
stores the Search command’s cycle A comparand in the even-numbered register and the cycle B comparand in the odd-numbered
register, as shown in Figure 7-1.
Address 68
index
135
0
0
1
2
4
6
68
0
1
3
5
7
15
30
31
Figure 7-1. Comparand-Register Selection During Search and Learn Instructions
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CYNSE70064A
7.2
Mask Registers
The device contains 16 68-bit global mask registers (eight pairs) dynamically selected in every Search operation to select the
Search subfield. The addressing of these registers is explained in Figure 7-2. The three-bit GMR Index supplied on the command
(CMD) bus can apply eight pairs of global masks during the Search and Write operations, as shown below. Note. In 68-bit Search
and Write operations, the host ASIC must program both the even and odd mask registers with the same values.
68
68
Index
135
0
0
0
1
1
2
3
2
4
5
3
6
7
4
8
9
5
10
11
6
12
13
7
14
15
Search and Write Command Global Mask Selection
Figure 7-2. Addressing the Global Masks Register Array
Each mask bit in the GMRs is used during Search and Write operations. In Search operations, setting the mask bit to 1 enables
compares; setting the mask bit to 0 disables compares (forced match) at the corresponding bit position. In Write operations to
the data or mask array, setting the mask bit to 1 enables Writes; setting the mask bit to 0 disables Writes at the corresponding
bit position.
7.3
Search Successful Registers (SSR[0:7])
The device contains eight search successful registers (SSRs) to hold the index of the location where a successful Search
occurred. The format of each register is described in Table 7-2. The Search command specifies which SSR stores the index of
a specific Search command in cycle B of the Search instruction. Subsequently, the host ASIC can use this register to access that
data array, mask array, or external SRAM using the index as part of the indirect access address (see Table 10-4 and Table 10-7).
The device with a valid bit set performs a Read or Write operation. All other devices suppress the operation.
Table 7-2. Search Successful Register Description
Field
INDEX
Range
[14:0]
Initial Value
X
–
VALID
[30:15]
[31]
0
0
–
[67:32]
0
7.4
Description
Index. This is the address of the 68-bit entry where a successful Search occurs.
The device updates this field only when the Search is successful. If a hit occurs
in a 136-bit entry-size quadrant, the LSB is 0. If a hit occurs in a 272-bit entry-size
quadrant, the two LSBs are 00. This index updates if the device is either a local
or global winner in a Search operation.
Reserved.
Valid. During Search operation in a depth-cascaded configuration, the device
that is a global winner in a match sets this bit to 1. This bit updates only when
the device is a global winner in a Search operation.
Reserved.
Command Register
Table 7-3 describes the command register fields.
Table 7-3. Command Register Description
Field Range Initial Value
Description
SRST
[0]
0
Software Reset. If 1, this bit resets the device with the same effect as a hardware reset.
Internally, it generates a reset pulse lasting for eight CLK cycles. This bit automatically resets
to a 0 after the reset has completed.
DEVE
[1]
0
Device Enable. If 0, it keeps the SRAM bus (SADR, WE_L, CE_L, OE_L, and ALE_L), SSF,
and SSV signals in three-state condition and forces the cascade interface output signals
LHO[1:0] and BHO[2:0] to 0. It also keeps the DQ bus in input mode. The purpose of this bit is
to make sure that there are no bus contentions when the devices power up in the system.
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Page 14 of 127
CYNSE70064A
Table 7-3. Command Register Description (continued)
Field
TLSZ
Range Initial Value
Description
[3:2]
01
Table Size. The host ASIC must program this field to configure the chips into a table of a certain
size. This field affects the pipeline latency of the Search and Learn operations as well as the
Read and Write accesses to the SRAM (SADR[21:0], CE_L, OE_L, WE_L, ALE_L, SSV, SSF,
and ACK). Once programmed, the Search latency stays constant.
Latency in number of CLK cycles
00: One device
4
01: Up to eight devices
5
10: Up to 31 devices
6
11: Reserved.
HLAT
[6:4]
000
Latency of Hit Signals. This field further adds latency to the SSF and SSV signals during
Search, and ACK signal during SRAM Read access by the following number of CLK cycles.
000: 0 100: 4
001: 1 101: 5
010: 2 110: 6
011: 3 111: 7
LDEV
[7]
0
Last Device in the Cascade. When set, this is the last device in the depth-cascaded table and
is the default driver for the SSF and SSV signals. In the event of a Search failure, the device
with this bit set drives the hit signals as follows: SSF = 0, SSV = 1.
During nonSearch cycles, the device with this bit set drives the signals as follows: SSF = 0,
SSV = 0.
LRAM
[8]
0
Last Device on the SRAM Bus. When set, this device is the last device on the SRAM bus in
the depth-cascaded table and is the default driver for the SADR, CE_L, WE_L, and ALE_L
signals. In cycles where no CYNSE70064A device in a depth-cascaded table drives these
signals, this devices drives the signals as follows: SADR = 22’h3FFFFF, CE_L = 1, WE_L = 1,
and ALE_L = 1. OE_L is always driven by the device for which this bit is set.
CFG [16:9]
00000000 Database Configuration. The device is divided internally into four partitions of 8K × 68, each
of which can be configured as 8K × 68, 4K × 136, or 2K × 272, as follows.
00: 8K × 68
01: 4K × 136
10: 2K × 272
11: Reserved
Bits [10:9] apply to configuring the first partition in the address space.
Bits [12:11] apply to configuring the second partition in the address space.
Bits [14:13] apply to configuring the third partition in the address space.
Bits [16:15] apply to configuring the fourth partition in the address space.
[67:17]
0
Reserved.
7.5
Information Register
Table 7-4 describes the information register fields.
Table 7-4. Information Register Description
Field
Range
Initial Value
Revision
[3:0]
000[4]
Implementation
[6:4]
000 or 001
Reserved
[7]
0
Device ID
[11:8]
0001 or 0010
Device ID
[12]
0 or 1
Device ID
[15:13]
000
MFID
[31:16]
Reserved
[67:32]
Description
Revision Number. This is the current device revision number. Numbers
start at one and increment by one for each revision of the device.
This is the CYNSE70064A implementation number.
Reserved.
This is the device identification number.
Reserved.
These are the three MSBs of the device identification number.
1101_1100_0111_1111 Manufacturer ID. This field is the same as the manufacturer identification
number and continuation bits in the TAP controller.
Reserved.
Note:
4. This field may change in future versions.
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CYNSE70064A
7.6
Read Burst Address Register
Table 7-5 shows the Read burst address register (RBURREG) fields which must be programmed before a burst Read.
Table 7-5. Read Burst Register Description
Field
ADR
Range
[14:0]
Initial Value
0
BLEN
[18:15]
[27:19]
0
[67:28]
7.7
Description
Address. This is the starting address of the data or mask array during a burst
Read operation. It automatically increments by one for each successive
Read of the data or mask array. Once the operation is complete, the contents
of this field must be reinitialized for the next operation.
Reserved.
Length of Burst Access. The device provides the capability to read from
4–511 locations in a single burst. The BLEN decrements automatically. Once
the operation is complete, the contents of this field must be reinitialized for
the next operation.
Reserved.
Write Burst Address Register Description
Table 7-6 describes the Write burst address register (WBURREG) fields which must be programmed before a burst Write.
Table 7-6. Write Burst Register Description
Field
ADR
Range
[14:0]
Initial Value
0
BLEN
[18:15]
[27:19]
0
[67:28]
7.8
Description
Address. This is the starting address of the data or mask array during a burst Write
operation. It automatically increments by one for each successive Write of the data or
mask array. Once the operation is complete, the contents of this field must be reinitialized for the next operation.
Reserved.
Length of Burst Access. The device provides the capability to Write from 4–511
locations in a single burst. The BLEN decrements automatically. Once the operation is
complete, the contents of this field must be reinitialized for the next operation.
Reserved.
NFA Register
Bit [0] of each 68-bit data entry is specially designated for use in the operation of the Learn command. For 68-bit-configured
quadrants, this bit indicates whether a location is full (bit set to 1) or empty (bit set to 0). Every Write and/or Learn command loads
the address of the first 68-bit location that contains a 0 in the entry’s bit[0]. This is stored in the NFA register (see Table 7-7). If
all the bits[0] in a device are set to 1, the CYNSE70064A asserts FULO[1:0] to 1.
For 136-bit-configured quadrants, the LSB of the NFA register is always set to 0. The host ASIC must set both bit[0] and bit[68]
in a 136-bit word to either 0 or 1 to indicate full or empty status. Both bit[0] and bit[68] must be set to either 0 or 1, (that is, the 10
or 01 settings are invalid).
Table 7-7. NFA Register
Address
60
Document #: 38-02041 Rev. *E
67–15
Reserved
14–0
Index
Page 16 of 127
CYNSE70064A
8.0
NSE Architecture and Operation Overview
32K
Masks
Data
The CYNSE70064A consists of 32K × 68-bit storage cells referred to as data bits. There is a mask cell corresponding to each
data cell. Figure 8-1 shows the three organizations of the device based on the value of the CFG bits in the command register.
68
136
272
8K
16 K
Masks
Data
Masks
CFG = 10101010
Data
CFG = 01010101
CFG = 00000000
Figure 8-1. CYNSE70064A Database WIDTH Configuration
During a Search operation, the Search data bit (S), data array bit (D), mask array bit (M) and the global mask bit (G) are used in
the following manner to generate a match at that bit position (see Table 8-1). The entry with a match on every bit position results
in a successful Search during a Search operation.
Table 8-1. Bit Position Match
G
0
1
1
1
1
1
M
X
0
1
1
1
1
D
X
X
0
1
0
1
S
X
X
0
0
1
1
Match
1
1
1
0
0
1
In order for a successful Search within a device to make the device the local winner in the Search operation, all 68-bit positions
must generate a match for a 68-bit entry in 68-bit configured quadrants, or all 136-bit positions must generate a match for two
consecutive even and odd 68-bit entries in quadrants configured as 136 bits, or all 272-bit positions must generate a match for
four consecutive entries aligned to four entry-page boundaries of 68-bit entries in quadrants configured as 272 bits.
An arbitration mechanism using a cascade bus determines the global winning device among the local winning devices in a Search
cycle. The global winning device drives the SRAM bus, SSV, and the SSF signals. In case of a Search failure, the device(s) with
the LDEV and LRAM bits set drives the SRAM bus, SSF, and SSV signals.
The CYNSE70064A device can be configured to contain tables of different widths, even within the same chip. Figure 8-2 shows
a sample configuration of different widths.
68
8K
68
8K
4K
2K
136
272
CFG = 10010000
Figure 8-2. Multiwidth Database Configurations Example
Document #: 38-02041 Rev. *E
Page 17 of 127
CYNSE70064A
9.0
Data and Mask Addressing
Figure 9-1 shows CYNSE70064A data and mask array addressing.
68
68
67
0
0
1
2
3
68
68
68
68
1
5
2
6
3
7
283
8K
0
0
2
4
6
0
0
4
68
135
1
3
5
7
64K
32K
32764
32765
32766
32767
CFG = 10101010
(272-bit configuration)
32767
CFG = 00000000
(68-bit configuration)
32766 32767
CFG = 01010101
(136-bit configuration)
Figure 9-1. Addressing of the CYNSE70064A Data and Mask Arrays
10.0
Commands
A master device such as an ASIC controller issues commands to the CYNSE70064A device using the command valid (CMDV)
signal and the CMD bus. The following subsections describe the operation of the commands.
10.1
Command Codes
The CYNSE70064A implements four basic commands, shown in Table 10-1. The command code must be presented to CMD[1:0]
while keeping the CMDV signal HIGH for two CLK2X cycles (designated as cycles A and B). The controller ASIC must align the
instructions using the PHS_L signal. The CMD[8:2] field passes the parameters of the command in cycles A and B.
Table 10-1. Command Codes
Command Code
00
01
10
Command
Read
Write
Search
11
Learn
10.2
Description
Reads one of the following: data array, mask array, device registers, or external SRAM.
Writes one of the following: data array, mask array, device registers, or external SRAM.
Searches the data array for a desired pattern using the specified register from the GMR
array and local mask associated with each data cell.
The device has internal storage for up to 16 comparands that it can learn. The device
controller can insert these entries at the next-free address (as specified by the NFA
register) using the Learn instruction.
Commands and Command Parameters
Table 10-2 lists the CMD bus fields that contain the CYNSE70064A command parameters and their respective cycles. Each
command is described separately in the subsections that follow.
Table 10-2. Command Parameters
CMD
CYC
8
7
6
5
4
3
2
1
0
Read
A
SADR[21]
SADR[20]
x
0
0
0
0 = Single
1 = Burst
0
0
B
0
0
0
0
0
0
0 = Single
1 = Burst
0
0
A
SADR[21]
SADR[20]
x
GMR Index [2:0]
0 = Single
1 = Burst
0
1
B
0
0
0
GMR Index [2:0]
0 = Single
1 = Burst
0
1
Write
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CYNSE70064A
Table 10-2. Command Parameters (continued)
CMD
CYC
8
7
6
Search
A
SADR[21]
SADR[20]
x
B
Learn
10.3
[5]
5
4
3
2
1
0
68-bit or 136-bit: 0
272-bit:
1 in first cycle
0 in second cycle
1
0
Comparand Register Index
1
0
GMR Index 2:0]
SSRI[2:0]
A
SADR[21]
SADR[20]
x
Comparand Register Index
1
1
B
0
0
Mode
0: 68-bit
1: 136-bit
Comparand Register Index
1
1
Read Command
The Read can be a single Read of a data array, a mask array, an SRAM, or a register location (CMD[2] = 0). It can be a burst
Read of the data (CMD[2] = 1) or mask array locations using an internal auto-incrementing address register (RBURADR).
A description of each type is provided in Table 10-3. A single-location Read operation lasts six cycles, as shown in Figure 10-1.
The burst Read adds two cycles for each successive Read. The SADR[21:20] bits supplied in the Read instruction cycle A drives
SADR[21:20] signals during the Read of an SRAM location.
Table 10-3. Read Command Parameters
CMD Parameter CMD[2]
0
Read Command
Single Read
1
Burst Read
Description
Reads a single location of the data array, mask array, external SRAM, or
device registers. All access information is applied on the DQ bus.
Reads a block of locations from the data array, or mask array as a burst.
The internal register (RBURADR) specifies the starting address and the
length of the data transfer from the data or mask array, and it auto-increments the address for each access. All other access information is
applied on the DQ bus. Note. The device registers and external SRAM
can only be read in single-Read mode.
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
CLK2X
PHS_L
CMDV
CMD[1:0]
CMD[8:2]
DQ
Read
A
B
Address
FF
Data
ACK
Figure 10-1. Single-Location Read Cycle Timing
The single Read operation takes six clock cycles, in the following sequence.
• Cycle 1: The host ASIC applies the Read instruction on the CMD[1:0] (CMD[2] = 0) using CMDV = 1 and the DQ bus supplies
the address, as shown in Table 10-4 and Table 10-5. The host ASIC selects the CYNSE70064A for which ID[4:0] matches the
DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70064A with the LDEV bit set. The host ASIC
also supplies SADR[21:20] on CMD[8:7] in cycle A of the Read instruction if the Read is directed to the external SRAM.
• Cycle 2: The host ASIC floats DQ[67:0] to three-state condition.
Note:
5. The 272-bit-configured devices or 272-bit-configured quadrants within devices do not support the Learn instruction.
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Page 19 of 127
CYNSE70064A
• Cycle 3: The host ASIC keeps DQ[67:0] in three-state condition.
• Cycle 4: The selected device starts to drive the DQ[67:0] bus, and drives the ACK signal from Z to LOW.
• Cycle 5: The selected device drives the Read data from the addressed location on the DQ[67:0] bus, and drives the ACK
signal HIGH.
• Cycle 6: The selected device floats the DQ[67:0] to three-state condition and drives the ACK signal LOW.
At the termination of cycle 6, the selected device releases the ACK line to three-state condition. The Read instruction is complete,
and a new operation can begin. Note that the latency of the SRAM Read will be different than the one described above (see
Subsection 12.2, “SRAM PIO Access” on page 101). Table 10-4 lists and describes the format of the Read address for a data
array, mask array, or SRAM.
Table 10-4. Read Address Format for Data Array, Mask Array, or SRAM
DQ[67:30] DQ[29]
DQ[25:21] DQ[20:19] DQ[18:15]
DQ[28:26]
DQ[14:0]
Reserved 0: Direct SSRI (applicable
1: Indirect
if DQ[29] is
indirect)
ID
00: Data Reserved If DQ[29] is 0, this field carries the address of the data
Array
array location. If DQ[29] is 1, the SSRI specified on
DQ[28:26] is used to generate the address of the data
array location: {SSR[14:2], SSR[1] | DQ[1], SSR[0] |
DQ[0]}.[6]
Reserved 0: Direct SSRI (applicable
1: Indirect
if DQ[29] is
indirect)
ID
01: Mask Reserved If DQ[29] is 0, this field carries the address of the mask
Array
array location. If DQ[29] is 1, the SSRI specified on
DQ[28:26] is used to generate the address of the mask
array location: {SSR[14:2], SSR[1] | DQ[1], SSR[0] |
DQ[0]}.[6]
Reserved 0: Direct SSRI (applicable
1: Indirect
if DQ[29] is
indirect)
ID
10:
Reserved If DQ[29] is 0, this field carries the address of the SRAM
External
location. If DQ[29] is 1, the SSRI specified on DQ[28:26]
SRAM
is used to generate the address of the SRAM location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}[6]
Table 10-5 describes the Read address format for the internal registers. Figure 10-2 illustrates the timing diagram for the burst
Read of the data or mask array.
Table 10-5. Read Address Format for Internal Registers
DQ[67:26]
Reserved
DQ[25:21]
ID
DQ[20:19]
11: Register
DQ[18:6]
Reserved
DQ[5:0]
Register Address
cycle cyclecycle cyclecyclecycle cycle cyclecyclecycle cyclecycle
1
2
3
4
5
6
7
8
9 10 11 12
CLK2X
PHS_L
CMDV
CMD[1:0]
Read
CMD[8:2]
A B
DQ
Address
FF Data0 FF Data1 FF Data2 FF Data3
ACK
EOT
Figure 10-2. Burst Read of the Data and Mask Arrays (BLEN = 4)
The Read operation lasts 4 + 2n CLK cycles (where n is the number of accesses in the burst specified by the BLEN field of the
RBURREG) in the sequence shown below. This operation assumes that the host ASIC has programmed the RBURREG with the
starting address (ADR) and the length of the transfer (BLEN) before initiating the burst Read command.
Note:
6. “ | ” stands for logical OR operation. “{}” stands for concatenation operator.
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Page 20 of 127
CYNSE70064A
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1 and the address supplied
on the DQ bus, as shown in Table 10-6. The host ASIC selects the CYNSE70064A where ID[4:0] matches the DQ[25:21] lines.
If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70064A with the LDEV bit set.
• Cycle 2: The host ASIC floats DQ[67:0] to the three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in the three-state condition.
• Cycle 4: The selected device starts to drive the DQ[67:0] bus and drives ACK and EOT from Z to LOW.
• Cycle 5: The selected device drives the Read data from the addressed location on the DQ[67:0] bus, and drives the ACK
signal HIGH.
Cycles 4 and 5 repeat for each additional access until all the accesses specified in the burst length (BLEN) field of RBURREG
are complete. On the last transfer, the CYNSE70064A drives the EOT signal HIGH.
• Cycle (4 + 2n): The selected device drives the DQ[67:0] to the three-state condition, and drives the ACK and EOT signals LOW.
At the termination of cycle (4 + 2n), the selected device floats the ACK line to the three-state condition. The burst Read instruction
is complete, and a new operation can begin. Table 10-6 describes the Read address format for data and mask arrays for burst
Read operations.
Table 10-6. Read Address Format for Data and Mask Arrays
DQ[67:26]
Reserved
DQ[25:21]
ID
DQ[20:19]
00: Data Array
DQ[18:15]
Reserved
Reserved
ID
01: Mask Array
Reserved
10.4
DQ[14:0]
Do not care. These 15 bits come from the internal
register (RBURADR) which increments for each
access.
Do not care. These 15 bits come from the internal
register (RBURADR) which increments for each
access.
Write Command
The Write can be a single Write of a data array, mask array, register, or external SRAM location (CMD[2] = 0). It can be a burst
Write (CMD[2] = 1) using an internal auto-incrementing address register (WBURADR) of the data or mask array locations.
A single-location Write is a 3-cycle operation, as shown in Figure 10-3. The burst Write adds one extra cycle for each successive
location Write.
cycle 0
cycle 1
cycle 2
cycle 3
cycle 4
CLK2X
PHS_L
CMDV
CMD[1:0]
CMD[8:2]
DQ
Write
A
B
Address
Data
X
Figure 10-3. Single Write Cycle Timing
The following is the Write operation sequence, and Table 10-7 shows the Write address format for the data array, the mask array,
or single-Write SRAM. Table 10-8 shows the Write address format for the internal registers.
• Cycle 1A: The host ASIC applies the Write instruction to the CMD[1:0] (CMD[2] = 0), using CMDV = 1 and the address supplied
on the DQ bus. The host ASIC also supplies the GMR Index to mask the Write to the data or mask array location on CMD[5:3].
For SRAM Writes, the host ASIC must supply the SADR[21:20] on CMD[8:7].
• Cycle 1B:The host ASIC continues to apply the Write instruction to the CMD[1:0] (CMD[2] = 0), using CMDV = 1 and the
address supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask
array locations in CMD[5:3].The host ASIC selects the device where ID[4:0] matches the DQ[25:21] lines, or it selects all the
devices when DQ[25:21] = 11111.
• Cycle 2: The host ASIC drives the DQ[67:0] with the data to be written to the data array, mask array, or register location of
the selected device.
• Cycle 3: Idle cycle.
At the termination of cycle 3, another operation can begin.
Note. The latency of the SRAM Write will be different than the one described above (see Subsection 12.2, “SRAM PIO Access”
on page 101).
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CYNSE70064A
Table 10-7. Write Address Format for Data Array, Mask Array, or SRAM (Single Write)
DQ
[67:30]
DQ[29]
DQ[28:26]
DQ
[25:21]
DQ[20:19]
DQ
[18:15]
DQ[14:0]
Reserved 0: Direct
SSR (appli1: Indirect cable if DQ[29]
is indirect)
ID
00: Data Array Reserved If DQ[29] is 0, this field carries the address of the data
array location.
If DQ[29] is 1, the SSR specified on DQ[28:26] is used
to generate the address of data array location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.[6]
Reserved 0: Direct
SSR (appli1: Indirect cable if DQ[29]
is indirect)
ID
01: Mask Array Reserved If DQ[29] is 0, this field carries the address of the mask
array location.
If DQ[29] is 1, the SSR specified on DQ[28:26] is used
to generate the address of the mask array location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.[6]
Reserved 0: Direct
SSR (appli1: Indirect cable if DQ[29]
is indirect)
ID
10: External
SRAM
Reserved If DQ[29] is 0, this field carries the address of the
SRAM location.
If DQ[29] is 1, the SSR specified on DQ[28:26] is used
to generate the address of SRAM location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.[6]
Table 10-8. Write Address Format for Internal Registers
DQ[67:26]
Reserved
DQ[25:21]
ID
DQ[20:19]
11: Register
DQ[18:6]
Reserved
DQ[5:0]
Register address
Figure 10-4 shows the timing diagram of a burst Write operation of the data or mask array.
cycle cycle cycle cycle cycle cycle
2
3
4
5
6
1
CLK2X
PHS_L
CMDV
CMD[1:0]
Write
CMD[8:2]
A
B
Address Data0 Data1 Data2 Data3
DQ
X
EOT
Figure 10-4. Burst Write of the Data and Mask Arrays (BLEN = 4)
The burst Write operation lasts for (n + 2) CLK cycles. n signifies the number of accesses in the burst as specified in the BLEN
field of the WBURREG register. The following is the block Write operation sequence. This operation assumes that the host ASIC
has programmed the WBURREG with the starting address (ADR) and the length of transfer (BLEN) before initiating a burst Write
command.
• Cycle 1A: The host ASIC applies the Write instruction to the CMD[1:0] (CMD[2] = 1), using CMDV = 1 and the address supplied
on the DQ bus, as shown in Table 10-9. The host ASIC also supplies the GMR Index to mask the Write to the data or mask
array locations in CMD[5:3].
• Cycle 1B: The host ASIC continues to apply the Write instruction on the CMD[1:0] (CMD[2] = 1), using CMDV = 1 and the
address supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask
array locations in CMD[5:3]. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21] lines. It selects all the
devices when DQ[25:21] = 11111.
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CYNSE70064A
• Cycle 2: The host ASIC drives the DQ[67:0] with the data to be written to the data or mask array location of the selected device.
The CYNSE70064A writes the data from the DQ[67:0] bus only to the subfield that has the corresponding mask bit set to 1 in
the GMR specified by the index CMD[5:3] supplied in cycle 1.
• Cycles 3 to n + 1: The host ASIC drives the DQ[67:0] with the data to be written to the next data or mask array location
(addressed by the auto-increment ADR field of the WBURREG register) of the selected device.
The CYNSE70064A writes the data on the DQ[67:0] bus only to the subfield that has the corresponding mask bit set to 1 in the
GMR specified by the index CMD[5:3] supplied in cycle 1. The CYNSE70064A drives the EOT signal LOW from cycle 3 to cycle
n; the CYNSE70064A drives the EOT signal HIGH in cycle n + 1 (n is specified in the BLEN field of the WBURREG).
• Cycle n + 2: TheCYNSE70064A drives the EOT signal LOW.
At the termination of cycle n + 2, the CYNSE70064A floats the EOT signal to a three-state operation, and a new instruction can
begin.
Table 10-9. Write Address Format for Data and Mask Array (Burst Write)
DQ[67:26]
Reserved
DQ[25:21]
ID
DQ[20:19]
00: Data array
DQ[18:15]
Reserved
Reserved
ID
01: Mask array
Reserved
10.5
DQ[14:0]
Do not care. These 15 bits come from the internal
register (WBURADR), which increments with each
access.
Do not care. These 15 bits come from the internal
register (WBURADR), which increments with each
access.
Search Command
This subsection describes the following:
• 68-bit Search on tables configured as ×68 using one device
• 68-bit Search on tables configured as ×68 using up to eight devices
• 68-bit Search on tables configured as ×68 using up to 31 devices
• 136-bit Search on tables configured as ×136 using one device
• 136-bit Search on tables configured as ×136 using up to eight devices
• 136-bit Search on tables configured as ×136 using up to 31 devices
• 272-bit Search on tables configured as ×272 using one device
• 272-bit Search on tables configured as ×272 using up to eight devices
• 272-bit Search on tables configured as ×272 using up to 31 devices
• Mixed-size searches on tables configured with different widths using an CYNSE70064A.
10.6
68-bit Search on Tables Configured as ×68 using a Single CYNSE70064A Device
Figure 10-5 shows the timing diagram for a Search command in the 68-bit-configured table (CFG = 00000000) consisting of
a single device for one set of parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1. The hardware diagram for this
Search subsystem is shown in Figure 10-6.
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Page 23 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search3
Search1
01
CMD[1:0]
CMD[8:2]
01
01
01
Search2
Search4
A B A B A B A B
D1
DQ
D2
D3
D4
SADR[21:0]
A1
A3
1
0
1
0
1
ALE_L
1
0
1
0
1
WE_L
1
1
1
1
1
OE_L
0
0
0
0
0
SSV
0
SSF
0
CE_L
1
1
0
1
0
0
Search1 Search3
Search2 Search4
Hit Miss Hit Miss
CFG = 00000000, HLAT = 000, TLSZ = 00, LRAM = 1, LDEV = 1.
Figure 10-5. Timing Diagram for 68-bit Search in x68 Table (One Device)
6
BHI[2:0]
DQ[67:0]
5
CMDV, CMD8:0]
4
3
LHI
2
1
0
SRAM
CYNSE70064A
SSF, SSV
BHI[2:0]
LHO[1]
LHO[0]
Figure 10-6. Hardware Diagram for 68-bit Search in x68 Table (One Device)
The following is the sequence of operation for a single 68-bit Search command (also refer to Command and Command Parameters, Subsection 10.2 on page 18).
• Cycle A: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:7] signals must be driven with
the same bits that will be driven on SADR[21:20] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data to
be compared. The CMD[2] signal must be driven to logic 0.
• Cycle B: The host ASIC continues to drive the CMDV HIGH and to apply Search command (10) on CMD[1:0]. CMD[5:2] must
be driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles A
and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching
entry and the hit flag (see page 14 for information on SSR[0:7]). The DQ[67:0] continues to carry the 68-bit data to be compared.
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Page 24 of 127
CYNSE70064A
Note. For 68-bit searches, the host ASIC must supply the same 68-bit data on DQ[67:0] during both cycles A and B. The even
and odd pair of GMRs selected for the compare must be programmed with the same value.
The logical 68-bit Search operation is shown in Figure 10-7. The entire table consisting of 68-bit entries is compared to a 68-bit
word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The effective
GMR is the 68-bit word specified by the identical value in both even and odd GMR pairs selected by the GMR Index in the
command’s cycle A. The 68-bit word K (presented on the DQ bus in both cycles A and B of the command) is also stored in both
even and odd comparand register pairs selected by the Comparand Register Index in the command’s cycle B. In a ×68 configuration, only the even comparand register can be subsequently used by the Learn command. The word K (presented on the DQ
bus in both cycles A and B of the command) is compared with each entry in the table starting at location 0. The first matching
entry’s location address L is the winning address that is driven as part of the SRAM address on the SADR[21:0] lines (See “SRAM
Addressing” on page 100.).
0
67
GMR
K
Location 67
address
Comparand Register (even)
0
K
1
2
Comparand Register (odd)
3
K
67
0
0
L
(First matching entry)
32767
CFG = 00000000
(68-bit configuration)
Figure 10-7. ×68 Table with One Device
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 68-bit
searches in ×68-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command
cycle (two CLK2X cycles) is shown in Table 10-10.
Table 10-10. The Latency of Search from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
32K × 68 bits
256K × 68 bits
992K × 68 bits
Latency in CLK Cycles
4
5
6
The latency of a Search from command to SRAM access cycle is 4 for a single device in the table and TLSZ = 00. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-11.
Table 10-11. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
10.7
Number of CLK Cycles
0
1
2
3
4
5
6
7
68-bit Search on Tables Configured as ×68 Using up to Eight CYNSE70064A Devices
The hardware diagram of the Search subsystem of eight devices is shown in Figure 10-8. The following are the parameters
programmed into the eight devices.
• First seven devices (devices 0–6): CFG = 00000000, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0.
• Eighth device (device 7): CFG = 00000000, TLSZ = 01, HLAT = 010, LRAM = 1, and LDEV = 1.
Document #: 38-02041 Rev. *E
Page 25 of 127
CYNSE70064A
Note. All eight devices must be programmed with the same values for TLSZ and HLAT. Only the last device in the table (device
number 7 in this case) must be programmed with LRAM = 1 and LDEV = 1. All other upstream devices (devices 0 through 6 in
this case) must be programmed with LRAM = 0 and LDEV = 0.
Figure 10-9 shows the timing diagram for a Search command in the 68-bit-configured table of eight devices for device number 0.
Figure 10-10 shows the timing diagram for a Search command in the 68-bit-configured table of eight devices for device number 1.
Figure 10-11 shows the timing diagram for a Search command in the 68-bit-configured table of eight devices for device number 7
(the last device in this specific table). For these timing diagrams four 68-bit searches are performed sequentially. Hit/Miss assumptions were made as shown below in Table 10-12.
Table 10-12. Hit/Miss Assumption
Search Number
Device 0
Device 1
Devices 2–6
Device 7
Document #: 38-02041 Rev. *E
1
Hit
Miss
Miss
Miss
2
Miss
Hit
Miss
Miss
3
Hit
Hit
Miss
Hit
4
Miss
Miss
Miss
Hit
Page 26 of 127
CYNSE70064A
SRAM
6
BHI[2:0]
LHO[1]
SSF, SSV
BHI[2:0]
LHO[1]
DQ[67:0]
CMDV
CMD[8:0]
3
LHI
CYNSE70064A #0
6
BHI[2:0]
5
5
4
4
LHO[1]
BHI[2:0]
2
6 5 4 3
LHI
CYNSE70064A #2
2
1
0
LHO[0]
1
0
6 5 4 3
2
LHI
CYNSE70064A #3
LHO[0]
1
0
6 5 4
3
CYNSE70064A #4
LHI
LHO[0]
1
0
BHI[2:0] 3
2 1
LHI
0
BHI[2:0] 3
2
1
LHI
0
6
5
4
LHI
CYNSE70064A #6
LHO[0]
1
LHI
0
LHO[0]
BHI[2:0]
2
1
LHO[0]
3
LHI
CYNSE70064A #1
LHO[1]
BHI[2:0]3
2
0
2
6 5
4
CYNSE70064ALHI
#5
LHO[0]
6
5 4
LHI
CYNSE70064A #7
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 10-8. Hardware Diagram for a Table With Eight Devices
Document #: 38-02041 Rev. *E
Page 27 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
CMD[8:2]
Search3
01
01
01
Search2
Search4
A B A B A B A B
D1
DQ
|(LHI[6:0])
D2
D3
D4
0
LHO[1:0]
SADR[21:0]
z
z
CE_L
z
ALE_L
z
WE_L
A1
0
0
1
z
z
z
z
A3
0
0
z
z
z
1
z
OE_L
z
SSV
z
1
z
1
z
SSF
z
1
z
1
z
CFG = 00000000, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(This
device
is the
global
winner.)
Search3
(This
device
is the
global
winner.)
Search2
(Miss
on this
device.)
Search4
(Miss
on this
device.)
Figure 10-9. Timing Diagram for 68-bit Search Device Number 0
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Page 28 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
CMD[8:2]
Search3
01
01
01
Search2
Search4
A B A B A B A B
D1
DQ
D2
D3
D4
|(LHI[6:0])
LHO[1:0]
SADR[21:0]
z
CE_L
z
ALE_L
z
WE_L
z
OE_L
z
SSV
z
1
z
SSF
z
1
z
A2
z
0
z
0
z
1
Search1
(Miss
on this
device.)
CFG = 00000000, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
Search3
(Local
winner
but not
global
winner.)
Search2 Search4
(Miss
(This
device is on this
device.)
global
winner.)
Figure 10-10. Timing Diagram for 68-bit Search Device Number 1
Document #: 38-02041 Rev. *E
Page 29 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
CMD[8:2]
Search3
01
01
01
Search2
Search4
A B A B A B A B
D1
DQ
D2
D3
D4
|(LHI[6:0])
LHO[1:0]
z
SADR[21:0]
CE_L
0
ALE_L
0
WE_L
1
OE_L
0
SSV
0
SSF
A4
z
0
z
0
1
z
0
z
1
0
z
1
0
Search1
(Miss
on this
device.)
Search3
(Local
CFG = 00000000, HLAT = 010, TLSZ = 01, LRAM = 1, LDEV = 1.
winner
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
but not
global
Note: Each bit in LHO[1:0] is the same logical signal.
winner.)
Search2 Search4
(Miss
(Global
on this
winner.)
device.)
Figure 10-11. Timing Diagram for 68-bit Search Device Number 7 (Last Device)
The following is the sequence of operation for a single 68-bit Search command (also refer to “Command and Command Parameters,” Subsection 10.2 on page 18).
• Cycle A: The host ASIC drives the CMDV HIGH and applies Search command code (10) to CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:7] signals must be driven with
the same bits that will be driven on SADR[21:20] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data to
be compared. The CMD[2] signal must be driven to logic 0.
• Cycle B: The host ASIC continues to drive the CMDV HIGH and to apply Search command (10) on CMD[1:0]. CMD[5:2] must
be driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles A
and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching
entry and hit flag (see page 14 for a description of SSR[0:7]). The DQ[67:0] continues to carry the 68-bit data to be compared.
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CYNSE70064A
Note. For 68-bit searches, the host ASIC must supply the same 68-bit data on DQ[67:0] during both cycles A and B, and the even
and odd pairs of GMRs selected for the comparison must be programmed with the same value.
The logical 68-bit Search operation is shown in Figure 10-12. The entire table with eight devices of 68-bit entries is compared to
a 68-bit word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The
effective GMR is the 68-bit word specified by the identical value in both even and odd GMR pairs in each of the eight devices and
selected by the GMR Index in the command’s cycle A. The 68-bit word K (presented on the DQ bus in both cycles A and B of the
command) is also stored in both even and odd comparand register pairs (selected by the Comparand Register Index in command
cycle B) in each of the eight devices. In the ×68 configuration, only the even comparand register can subsequently be used by
the Learn command in one of the devices (only the first non-full device). The word K (presented on the DQ bus in both cycles A
and B of the command) is compared with each entry in the table starting at location 0. The first matching entry’s location address
L is the winning address that is driven as part of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on
page 100). The global winning device will drive the bus in a specific cycle. On a global miss cycle the device with LRAM = 1
(default driving device for the SRAM bus) and LDEV = 1 (default driving device for SSF and SSV signals) will be the default driver
for such missed cycles.
0
67
GMR
K
Must be same in each of the eight
devices
Location 67
address
0
67
0
1
Comparand Register (Even)
2
K
3
Comparand Register (Odd)
K
L
0
(First matching entry)
262143
CFG = 00000000
(68-bit configuration)
Figure 10-12. x68 Table with Eight Devices
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 68-bit
searches in ×68-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command
cycle (two CLK2X cycles) is shown in Table 10-13.
Table 10-13. The Latency of Search from Instruction to SRAM Access Cycle
Will be same in each of the eight
devices
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
32K × 68 bits
256K × 68 bits
992K × 68 bits
Latency in CLK Cycles
4
5
6
The latency of the Search from command to SRAM access cycle is 5 for up to eight devices in the table (TLSZ = 01). SSV and
SSF also shift further to the right for different values of HLAT, as specified in Table 10-14.
Table 10-14. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
Document #: 38-02041 Rev. *E
Number of CLK Cycles
0
1
2
3
4
5
6
7
Page 31 of 127
CYNSE70064A
10.8
68-bit Search on Tables Configured as ×68 Using up to 31 CYNSE70064A Devices
The hardware diagram of the Search subsystem of 31 devices is shown in Figure 10-13. Each of the four blocks in the diagram
represents eight CYNSE70064A devices (except the last, which has seven devices). The diagram for a block of eight devices is
shown in Figure 10-14. The following are the parameters programmed into the 31 devices.
• First thirty devices (devices 0–29): CFG = 00000000, TLSZ = 10, HLAT = 001, LRAM = 0, and LDEV = 0.
• Thirty-first device (device 30): CFG = 00000000, TLSZ = 10, HLAT = 001, LRAM = 1, and LDEV = 1.
Note. All 31 devices must be programmed with the same values for TLSZ and HLAT. Only the last device in the table must be
programmed with LRAM = 1 and LDEV = 1 (device number 30 in this case). All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (devices 0 through 29 in this case).
The timing diagrams referred to in this paragraph reference the Hit/Miss assumptions defined in Table 10-15. For the purpose of
illustrating the timings, it is further assumed that the there is only one device with a matching entry in each of the blocks.
Figure 10-15 shows the timing diagram for a Search command in the 68-bit-configured table of 31 devices for each of the eight
devices in block 0. Figure 10-16 shows a timing diagram for a Search command in the 68-bit-configured table of 31 devices for
the all the devices in block number 1 (above the winning device in that block). Figure 10-17 shows the timing diagram for the
globally winning device (defined as the final winner within its own and all blocks) in block number 1. Figure 10-18 shows the timing
diagram for all the devices below the globally winning device in block number 1. Figure 10-19, Figure 10-20, and Figure 10-21
show the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below
the globally winning device, respectively, for block number 2. Figure 10-22, Figure 10-23, Figure 10-24, and Figure 10-25 show
the timing diagrams of the devices above globally winning device, the globally winning device, and the devices below the globally
winning device except the last device (device 30), respectively, for block number 3.
The 68-bit Search operation is pipelined and executes as follows. Four cycles from the Search command, each of the devices
knows the outcome internal to it for that operation. In the fifth cycle after the Search command, the devices in a block arbitrate
for a winner amongst them (a “block” being defined as less than or equal to eight devices resolving the winner within them using
the LHI[6:0] and LHO[1:0] signalling mechanism). In the sixth cycle after the Search command, the blocks (of devices) resolve
the winning block through the BHI[2:0] and BHO[2:0] signalling mechanism. The winning device within the winning block is the
global winning device for a Search operation.
Table 10-15. Hit/Miss Assumptions
Search Number
Block 0
Block 1
Block 2
Block 3
Document #: 38-02041 Rev. *E
1
Miss
Miss
Miss
Hit
2
Miss
Miss
Hit
Hit
3
Miss
Hit
Hit
Miss
4
Miss
Miss
Miss
Miss
Page 32 of 127
CYNSE70064A
BHI[2]
SSF, SSV
BHI[1]
BHI[0] GND
Block of 8 CYNSE70064As Block 0 (Devices 0–7)
BHO[2]
BHO[1]
BHO[0]
SRAM
BHI[2]
BHI[1]
BHI[0] GND
Block of 8 CYNSE70064As Block 1 (Devices 8–15)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8 CYNSE70064As Block 2 (Devices 16–23)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
Block of 7 CYNSE70064As Block 3 (Devices 24–30)
DQ[67:0]
CMD[8:0], CMDV
BHO[2]
BHO[1]
BHO[0]
Figure 10-13. Hardware Diagram for a Table with 31 Devices
Document #: 38-02041 Rev. *E
Page 33 of 127
CYNSE70064A
SRAM
BHI[2:0]
BHI[2:0]
6
3
LHI
CYNSE70064A #0
2
6 5 4 3
CYNSE70064A #1LHI
2
6 5 4 3
LHI
CYNSE70064A #2
2
LHO[1]
BHI[2:0]
DQ[67:0]
CMDV
CMD[8:0]
LHO[1]
BHI[2:0]
5
4
LHO[1]
BHI[2:0]
0
LHO[0]
6 5 4 3
2
LHI
CYNSE70064A #3
LHO[0]
1
0
6 5 4
3
CYNSE70064A #4
LHI
LHO[0]
1
0
2 1
LHI
0
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70064A #6
LHO[0]
1
LHI
1
0
BHI[2:0] 3
2
LHO[0]
LHO[0]
BHI[2:0]
BHI[2:0]3
0
1
LHO[1]
SSV, SSF
1
0
2
6 5
4
CYNSE70064ALHI
#5
LHO[0]
6
5 4
LHI
CYNSE70064A #7
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 10-14. Hardware Diagram for a Block of up to Eight Devices
Document #: 38-02041 Rev. *E
Page 34 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss
on
this
device.)
Search3
(Miss
on
this
device)
Search2 Search4
(Miss
(Miss
on this
on this
device.) device.)
Figure 10-15. Timing Diagram for Each Device In Block Number 0 (Miss on Each Device)
Document #: 38-02041 Rev. *E
Page 35 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0)] stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss
on
this
device.)
Search3
(Miss
on
this
device.)
Search2 Search4
(Miss
(Miss
on this
on this
device.) device.)
Figure 10-16. Timing Diagram for Each Device Above the Winning Device in Block Number 1
Document #: 38-02041 Rev. *E
Page 36 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
Search3
D2
D3
D4
z
A3
z
z
z
z
z
WE_L
z
z
OE_L
z
SSV
z
z
SSF
z
z
CE_L
ALE_L
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss
on
this
device.)
Search3
(This
device
global
winner)
Search2 Search4
(Miss
(Miss
on this
on this
device.) device.)
Figure 10-17. Timing Diagram for Globally Winning Device in Block Number 1
Document #: 38-02041 Rev. *E
Page 37 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss
on
this
device.)
Search3
(Miss
on
this
device.)
Search2 Search4
(Miss
(Miss
on this
on this
device.) device.)
Figure 10-18. Timing Diagram for Devices Below the Winning Device in Block Number 1
Document #: 38-02041 Rev. *E
Page 38 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
Search1
(Miss
on
this
device.)
Search3
(Miss
on
this
device.)
Search2 Search4
(Miss
(Miss
on this
on this
device.) device.)
Figure 10-19. Timing Diagram for Devices Above the Winning Device in Block Number 2
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Document #: 38-02041 Rev. *E
Page 39 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
01
D2
D3
D4
z
A2
z
z
z
0
z
z
0
1
z
WE_L
z
OE_L
z
SSV
z
1
z
SSF
z
1
z
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss
on
this
device.)
Search3
(Hit
but
not
winner.)
Search2 Search4
(Miss
(Global
winner.) on this
device.)
Figure 10-20. Timing Diagram for Globally Winning Device in Block Number 2
Document #: 38-02041 Rev. *E
Page 40 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
01
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss
on this
device.)
Search3
(Miss
on this
device.)
Search4
Search2
(Miss on
(Miss on
this device.) this device.)
Figure 10-21. Timing Diagram for Devices Below the Winning Device in Block Number 2
Document #: 38-02041 Rev. *E
Page 41 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
D2
D3
D4
z
SADR[21:0]
z
CE_L
ALE_L
Search3
01
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3
(Miss on
(Miss on
this device.) this device.)
Search2 Search4
(Miss on
(Miss on
this device.) this device.)
Figure 10-22. Timing Diagram for Devices Above the Winning Device in Block Number 3
Document #: 38-02041 Rev. *E
Page 42 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
ALE_L
D2
D3
D4
z
SADR[21:0]
CE_L
Search3
01
A1
z
z
z
0
z
z
0
WE_L
z
OE_L
z
SSV
z
1
z
z
1
z
SSF
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
1
z
Search1
(Global
winner.)
Search3
(Miss on
this device.)
Search2
(Hit
but not
global
winner.)
Search4
(Miss on
this device.)
Figure 10-23. Timing Diagram for Globally Winning Device in Block Number 3
Document #: 38-02041 Rev. *E
Page 43 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
01
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3
(Miss on (Miss on
this device.)this device.)
Search2 Search4
(Miss on
(Miss on
this device.) this device.)
Figure 10-24. Timing Diagram for Devices Below the Winning Device in Block Number 3
(Except the Last Device [Device 30])
Document #: 38-02041 Rev. *E
Page 44 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
Search3
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
LHO[1:0]
0
0
I(BHI[2:0])
0
BHO[2:0]
0
D2
D3
D4
z
SADR[21:0]
CE_L
0
ALE_L
0
WE_L
OE_L
SSV
SSF
1
0
0
0
z
0
z
0
z
1
z
z
1
0
Search1 Search3
(Hit on
(Hit on
some
some
device
device
above.)
above.)
Search2 Search4
(Hit on
(Global
some
miss; this device
device
default driver.)
above.)
Figure 10-25. Timing Diagram for Device Number 6 in Block Number 3 (Device 30 in Depth-Cascaded Table)
The following is the sequence of operation for a single 68-bit Search command (also refer to the “Command and Command
Parameters,” Subsection 10.2 on page 18).
• Cycle A: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:7] signals must be driven with
the same bits that will be driven on SADR[21:20] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data to
be compared. The CMD[2] signal must be driven to a logic 0.
• Cycle B: The host ASIC continues to drive the CMDV HIGH and applies Search command (10) on CMD[1:0]. CMD[5:2] must
be driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles A
and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching
entry and the hit flag (see page 14 for the description of SSR[0:7]). The DQ[67:0] continues to carry the 68-bit data to be
compared.
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 1, LDEV = 1.
Note: |(BHI[2:0)] stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Note. For 68-bit searches, the host ASIC must supply the same 68-bit data on DQ[67:0] during both cycles A and B and the even
and odd pair of global mask registers selected for the compare must be programmed with the same value.
Document #: 38-02041 Rev. *E
Page 45 of 127
CYNSE70064A
The logical 68-bit Search operation is shown in Figure 10-26. The entire table (31 devices of 68-bit entries) is compared to a
68-bit word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The
effective GMR is the 68-bit word specified by the identical value in both even and odd GMR pairs in each of the eight devices and
selected by the GMR Index in the command’s cycle A. The 68-bit word K (presented on the DQ bus in both cycles A and B of the
command) is also stored in both even and odd comparand register pairs in each of the eight devices and selected by the
Comparand Register Index in command’s cycle B. In the ×68 configuration, the even comparand register can be subsequently
used by the Learn command only in the first non-full device. The word K (presented on the DQ bus in both cycles A and B of the
command) is compared with each entry in the table starting at location 0. The first matching entry’s location address L is the
winning address that is driven as part of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on page 100). The
global winning device will drive the bus in a specific cycle. On global miss cycles the device with LRAM = 1 and LDEV = 1 will be
the default driver for such missed cycles.
0
67
GMR
K
Must be same in each of the 31
devices
0
Location 67
address
0
67
0
1
Comparand Register (even)
2
K
3
Comparand Register (odd)
K
L
(First matching entry)
1015807
Will be same in each of the 31
devices
CFG = 00000000
(68-bit configuration)
Figure 10-26. ×68 Table with 31 Devices
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 68-bit
searches in ×68-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command
cycle (two CLK2X cycles) is shown in Table 10-16.
Table 10-16. The Latency of Search from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
32K × 68 bits
256K × 68 bits
996K × 68 bits
Latency in CLK Cycles
4
5
6
For up to 31 devices in the table (TLSZ = 10), Search latency from command to SRAM access cycle is 6. In addition, SSV and
SSF shift further to the right for different values of HLAT, as specified in Table 10-17.
Table 10-17. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
Document #: 38-02041 Rev. *E
Number of CLK Cycles
0
1
2
3
4
5
6
7
Page 46 of 127
CYNSE70064A
10.9
136-bit Search on Tables Configured as ×136 Using a Single CYNSE70064A Device
Figure 10-27 shows the timing diagram for a Search command in the 136-bit-configured table (CFG = 01010101) consisting of a
single device for one set of parameters: TLSZ = 00, HLAT = 001, LRAM = 1, and LDEV = 1. The hardware diagram for this Search
subsystem is shown in Figure 10-28.
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search3
01
01
01
Search2
Search4
CMD[8:2]
A B A B A B A B
DQ
A B A B A B A B
D1 D2 D3 D4
SADR[21:0]
A1
CE_L
A3
1
0
1
0
1
1
0
1
0
1
OE_L
1
0
1
0
1
0
1
0
1
0
SSV
0
1
SSF
0
1
ALE_L
WE_L
0
1
0
0
CFG = 01010101, HLAT = 001, TLSZ = 00, LRAM = 1, LDEV = 1.
Search1 Search3
Search2 Search4
Hit Miss Hit Miss
Figure 10-27. Timing Diagram for 136-bit Search (One Device)
6
BHI[2:0]
DQ[67:0]
CMDV, CMD[8:0]
SSF, SSV
5
4
3
LHI
2
1
0
SRAM
CYNSE70064A
BHO[2:0]
LHO[1]
LHO[0]
Figure 10-28. Hardware Diagram for a Table with One Device
The following is the operation sequence for a single 136-bit Search command (also refer to “Command and Command Parameters,” Subsection 10.2 on page 18).
• Cycle A: The host ASIC drives the CMDV HIGH and applies Search command code (10) to CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:7] signals must be driven with
the same bits that will be driven on SADR[21:20] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data
([135:68]) to be compared against all even locations. The CMD[2] signal must be driven to logic 0.
• Cycle B: The host ASIC continues to drive the CMDV HIGH and applies the command code of Search command (10) on
CMD[1:0]. CMD[5:2] must be driven by the index of the comparand register pair for storing the 136-bit word presented on the
DQ bus during cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the
address of the matching entry and hit flag (see page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with 68-bit
data ([67:0]), compared to all odd locations.
Document #: 38-02041 Rev. *E
Page 47 of 127
CYNSE70064A
Note. For 136-bit searches, the host ASIC must supply two distinct 68-bit data words on DQ[67:0] during cycles A and B. The
even-numbered GMR of the pair specified by the GMR Index is used for masking the word in cycle A. The odd-numbered GMR
of the pair specified by the GMR Index is used for masking the word in cycle B.
The logical 136-bit Search operation is shown in Figure 10-29. The entire table of 136-bit entries is compared to a 136-bit word
K (presented on the DQ bus in cycles A and B of the command) using the GMR and the local mask bits. The GMR is the 136-bit
word specified by the even and odd global mask pair selected by the GMR Index in the command’s cycle A. The 136-bit word K
(presented on the DQ bus in cycles A and B of the command) is also stored in both even and odd comparand register pairs
selected by the Comparand Register Index in the command’s cycle B. The two comparand registers can subsequently be used
by the Learn command with the even comparand register stored in an even location, and the odd comparand register stored in
an adjacent odd location. The word K (presented on the DQ bus in cycles A and B of the command) is compared with each entry
in the table starting at location 0. The first matching entry’s location address L is the winning address that is driven as part of the
SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on page 100). Note. The matching address is always going to
an even address for a 136-bit Search.
0
135
Even
A
135
Location
address
0
67
0
2
Comparand Register (even)
4
A
6
Comparand Register (odd)
B
L
GMR
K
Odd
B
0
(First matching entry)
32766
CFG = 01010101
(136-bit configuration)
Figure 10-29. ×136 Table with One Device
The Search command is a pipelined operation that executes searches at half the rate of the frequency of CLK2X for 136-bit
searches in ×136-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 136-bit Search
command cycle (two CLK2X cycles) is shown in Table 10-18.
Table 10-18. The Latency of Search from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
16K × 136 bits
128K × 136 bits
496K × 136 bits
Latency in CLK Cycles
4
5
6
For a single device in the table with TLSZ = 00, the latency of the Search from command to SRAM access cycle is 4. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-19.
Table 10-19. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
Document #: 38-02041 Rev. *E
Number of CLK Cycles
0
1
2
3
4
5
6
7
Page 48 of 127
CYNSE70064A
10.10
136-bit Search on Tables Configured as ×136 Using up to Eight CYNSE70064A Devices
The hardware diagram of the Search subsystem of eight devices is shown in Figure 10-30. The following are parameters
programmed into the eight devices.
• First seven devices (devices 0–6): CFG = 01010101, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0.
• Eighth device (device 7): CFG = 01010101, TLSZ = 01, HLAT = 010, LRAM = 1, and LDEV = 1.
Note. All eight devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be
programmed with LRAM = 1 and LDEV = 1 (device number 7 in this case). All other upstream devices must be programmed with
LRAM = 0 and LDEV = 0 (devices 0 through 6 in this case).
Figure 10-31 shows the timing diagram for a Search command in the 136-bit-configured table of eight devices for device 0.
Figure 10-32 shows the timing diagram for a Search command in the 136-bit-configured table consisting of eight devices for
device number 1. Figure 10-33 shows the timing diagram for a Search command in the 136-bit configured table consisting of
eight devices for device number 7 (the last device in this specific table). For these timing diagrams, four 136-bit searches are
performed sequentially, and the following Hit/Miss assumptions were made (see Table 10-20).
Table 10-20. Hit/Miss Assumption
Search Number
Device 0
Device 1
Devices 2–6
Device 7
Document #: 38-02041 Rev. *E
1
Hit
Miss
Miss
Miss
2
Miss
Hit
Miss
Miss
3
Hit
Hit
Miss
Hit
4
Miss
Miss
Miss
Hit
Page 49 of 127
CYNSE70064A
SRAM
BHI[2:0]
SSF, SSV
6 5 4 3
LHI
CYNSE70064A #0
LHO[1]
BHI[2:0]
6
LHO[1]
DQ[67:0]
CMDV
CMD[8:0]
BHI[2:0]
5
4
LHO[1]
BHI[2:0]
2
6 5 4 3
LHI
CYNSE70064A #2
2
1
0
LHO[0]
1
0
6 5 4 3
2
LHI
CYNSE70064A #3
LHO[0]
1
0
6 5 4
3
CYNSE70064A #4
LHI
LHO[0]
1
0
BHI[2:0] 3
2 1
LHI
0
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70064A #6
LHO[0]
1
LHI
0
LHO[0]
BHI[2:0]
2
1
LHO[0]
3
LHI
CYNSE70064A #1
LHO[1]
BHI[2:0]3
2
0
2
6 5
4
CYNSE70064ALHI
#5
LHO[0]
6
5
4
LHI
CYNSE70064A #7
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 10-30. Hardware Diagram for a Table with Eight Devices
Document #: 38-02041 Rev. *E
Page 50 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search3
01
01
01
Search2
Search4
CMD[8:2]
A B A B A B A B
DQ
A B A B A B A B
D1 D2 D3 D4
|(LHI[6:0])
0
LHO[1:0]
SADR[21:0]
CE_L
ALE_L
WE_L
z
z
z
z
A1
0
0
1
z
z
z
z
A3
0
0
z
z
z
1
z
OE_L
z
SSV
z
1
z
1
z
SSF
z
1
z
1
z
Search1 Search3
(This
(This
device
device
is the
is the
Global
global
winner.)
winner.)
Search2 Search4
(Miss
(Miss
on this
on this
device.) device.)
Figure 10-31. Timing Diagram for 136-bit Search Device Number 0
CFG = 01010101, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
Document #: 38-02041 Rev. *E
Page 51 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
CMD[8:2]
Search3
01
01
01
Search2
Search4
A B A B A B A B
A B A B A B A B
D1 D2 D3 D4
DQ
LHI[6:0]
LHO[1:0]
SADR[21:0]
z
CE_L
z
ALE_L
z
WE_L
z
OE_L
z
SSV
z
1
z
SSF
z
1
z
A2
z
0
z
0
z
1
Search1
(Miss
on this
device.)
Search3
(Local
but not
global
winner.)
Search2 Search4
(Miss
(This
on this
device
device.)
global
winner.)
Figure 10-32. Timing Diagram for 136-bit Search Device Number 1
CFG = 01010101, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
Document #: 38-02041 Rev. *E
Page 52 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search3
01
01
01
Search2
Search4
CMD[8:2]
A B A B A B A B
DQ
A B A B A B A B
D1 D2 D3 D4
|(LHI[6:0])
LHO[1:0]
SADR[21:0]
A4
CE_L
0
ALE_L
0
WE_L
1
OE_L
0
SSV
0
SSF
z
0
z
0
1
z
0
CFG = 01010101, HLAT = 010, TLSZ = 01, LRAM = 1, LDEV = 1.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
z
1
0
z
1
0
Search1
(Miss
on this
device.)
Search3
(Local
but not
global
winner.)
Search2 Search4
(Global
(Miss
winner.)
on this
device.)
Figure 10-33. Timing Diagram for 136-bit Search Device Number 7 (Last Device)
The following is the sequence of operation for a single 136-bit Search command (also see Subsection 10.2, “Commands and
Command Parameters” on page 18).
• Cycle A: The host ASIC drives CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3] signals
must be driven with the index to the GMR pair for use in this Search operation. CMD[8:7] signals must be driven with the same
bits that will be driven by this device on SADR[21:20] if it has a hit. DQ[67:0] must be driven with the 68-bit data ([135:68]) in
order to be compared against all even locations. The CMD[2] signal must be driven to a logic 0.
• Cycle B: The host ASIC continues to drive CMDV HIGH and to apply the command code for Search command (10) on
CMD[1:0]. CMD[5:2] must be driven by the index of the comparand register pair for storing the 136-bit word presented on the
DQ bus during cycles A and B. CMD[8:6] signals must be driven with the SSR index that will be used for storing the address
of the matching entry and the hit flag (see page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with 68-bit data
([67:0]) compared against all odd locations.
Document #: 38-02041 Rev. *E
Page 53 of 127
CYNSE70064A
The logical 136-bit Search operation is shown in Figure 10-34. The entire table (eight devices of 136-bit entries) is compared to
a 136-bit word K (presented on the DQ bus in cycles A and B of the command) using the GMR and local mask bits. The GMR is
the 136-bit word specified by the even and odd global mask pair selected by the GMR Index in the command’s cycle A.
The 136-bit word K (presented on the DQ bus in cycles A and B of the command) is also stored in the even and odd comparand
registers specified by the Comparand Register Index in the command’s cycle B. In ×136 configurations, the even and odd
comparand registers can subsequently be used by the Learn command in only one of the devices (the first non-full device). The
word K (presented on the DQ bus in cycles A and B of the command) is compared to each entry in the table starting at location
0. The first matching entry’s location, address L, is the winning address that is driven as part of the SRAM address on the
SADR[21:0] lines (see “SRAM Addressing” on page 100). The global winning device will drive the bus in a specific cycle. On
global miss cycles the device with LRAM = 1 (the default driving device for the SRAM bus) and LDEV = 1 (the default driving
device for SSF and SSV signals) will be the default driver for such missed cycles. Note. During 136-bit searches of
136-bit-configured tables, the Search hit will always be at an even address.
0
135
Must be same in each of the eight
devices
Even
Odd
GMR
B
A
K
0
Location 135
address
0
67
0
2
Comparand Register (even)
4
A
6
Comparand Register (odd)
B
L
(First matching entry)
Will be same in each of the eight
devices
262142
CFG = 01010101
(136-bit configuration)
Figure 10-34. ×136 Table with Eight Devices
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 136-bit
searches in ×136-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 136-bit Search
command cycle (two CLK2X cycles) is shown in Table 10-21.
Table 10-21. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
16K × 136 bits
128K × 136 bits
496K × 136 bits
Latency in CLK Cycles
4
5
6
For one to eight devices in the table and TLSZ = 01, the latency of a Search from command to SRAM access cycle is 5. In addition,
SSV and SSF shift further to the right for different values of HLAT as specified in Table 10-22.
Table 10-22. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
Document #: 38-02041 Rev. *E
Number of CLK Cycles
0
1
2
3
4
5
6
7
Page 54 of 127
CYNSE70064A
10.11
136-bit Search on Tables Configured as ×136 Using up to 31 CYNSE70064A Devices
The hardware diagram of the Search subsystem of 31 devices is shown in Figure 10-35. Each of the four blocks in the diagram
represents a block of eight CYNSE70064A devices (except the last, which has seven devices). The diagram for a block of eight
devices is shown in Figure 10-36. Following are the parameters programmed into the 31 devices.
• First thirty devices (devices 0–29): CFG = 01010101, TLSZ = 10, HLAT = 001, LRAM = 0, and LDEV = 0.
• Thirty-first device (device 30): CFG = 01010101, TLSZ = 10, HLAT = 001, LRAM = 1, and LDEV = 1.
Note. All 31 devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be
programmed with LRAM = 1 and LDEV = 1 (device number 30 in this case). All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (devices 0 through 29 in this case).
The timing diagrams referred to in this paragraph reference the Hit/Miss assumptions defined in Table 10-23. For the purpose of
illustrating timings, it is further assumed that the there is only one device with a matching entry in each of the blocks. Figure 10-37
shows the timing diagram for a Search command in the 136-bit-configured table (31 devices) for each of the eight devices in
block number 0. Figure 10-38 shows the timing diagram for Search command in the 68-bit-configured table (31 devices) for all
the devices in block number 1 above the winning device in that block. Figure 10-39 shows the timing diagram for the globally
winning device (the final winner within its own block and all blocks) in block number 1. Figure 10-40 shows the timing diagram
for all the devices below the globally winning device in block number 1. Figure 10-41, Figure 10-42, and Figure 10-43 respectively
show the timing diagrams of the devices above globally winning device, the globally winning device and devices below the globally
winning device for block number 2. Figure 10-44, Figure 10-45, Figure 10-46, and Figure 10-47 respectively show the timing
diagrams of the devices above the globally winning device, the globally winning device, and devices below the globally winning
device except the last device (device 30), and the last device (device 30) for block number 3.
The 136-bit Search operation is pipelined and executes as follows. Four cycles from the Search command, each of the devices
knows the outcome internal to it for that operation. In the fifth cycle after the Search command, the devices in a block (being less
than or equal to eight devices resolving the winner within them using the LHI[6:0] and LHO[1:0] signalling mechanism) arbitrate
for a winner amongst them. In the sixth cycle after the Search command, the blocks (of devices) resolve the winning block through
the BHI[2:0] and BHO[2:0] signalling mechanism. The winning device in the winning block is the global winning device for a Search
operation.
Table 10-23. Hit/Miss Assumption
Search Number
Block 0
Block 1
Block 2
Block 3
Document #: 38-02041 Rev. *E
1
Miss
Miss
Miss
Hit
2
Miss
Miss
Hit
Hit
3
Miss
Hit
Hit
Miss
4
Miss
Miss
Miss
Miss
Page 55 of 127
CYNSE70064A
BHI[2]
SSF, SSV
BHI[1]
BHI[0] GND
Block of 8 CYNSE70064As Block 0 (devices 0–7)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
BHI[2]
BHI[1]
BHI[0]
SRAM
GND
Block of 8 CYNSE70064As Block 1 (devices 8–15)
BHO[2]
BHO[1]
BHO[0]
GND
Block of 8 CYNSE70064As Block 2 (devices 16–23)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
Block of 7 CYNSE70064As Block 3 (devices 24–30)
DQ[67:0]
BHO[2]
BHO[1]
BHO[0]
CMD[8:0], CMDV
Figure 10-35. Hardware Diagram for a Table with 31 Devices
Document #: 38-02041 Rev. *E
Page 56 of 127
CYNSE70064A
SRAM
BHI[2:0]
BHI[2:0]
6
LHO[1]
BHI[2:0]
LHO[1]
DQ[67:0]
CMDV
CMD[8:0]
3
LHI
CYNSE70064A #0
6
BHI[2:0]
5
5
4
4
LHO[1]
BHI[2:0]
2
6 5 4 3
LHI
CYNSE70064A #2
2
0
LHO[0]
0
6 5 4 3
2
LHI
CYNSE70064A #3
LHO[0]
1
0
6 5 4
3
CYNSE70064A #4
LHI
LHO[0]
1
0
2 1
LHI
0
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70064A #6
LHO[0]
1
LHI
1
1
BHI[2:0] 3
2
0
LHO[0]
BHI[2:0]
BHI[2:0]3
1
LHO[0]
3
LHI
CYNSE70064A #1
LHO[1]
SSV, SSF
2
0
2
6 5
4
CYNSE70064ALHI
#5
LHO[0]
6
5 4
LHI
CYNSE70064A #7
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 10-36. Hardware Diagram for a Block of Up to Eight Devices
Document #: 38-02041 Rev. *E
Page 57 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
A B A B A B A B
D1 D2 D3 D4
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
Search1
(Miss
on
this
device.)
Search3
(Miss
on
this
device.)
Search2 Search4
(Miss
(Miss
on this
on this
device.) device.)
Figure 10-37. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device)
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Document #: 38-02041 Rev. *E
Page 58 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
A B A B A B A B
D1 D2 D3 D4
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
01
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss
on
this
device.)
Search3
(Miss
on
this
device.)
Search2 Search4
(Miss
(Miss
on this
on this
device.) device.)
Figure 10-38. Timing Diagram for Each Device Above the Winning Device in Block Number 1
Document #: 38-02041 Rev. *E
Page 59 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
A B A B A B A B
D1 D2 D3 D4
z
A3
z
0
z
0
z
z
z
WE_L
z
OE_L
z
SSV
z
1
SSF
z
1
1
z
z
zz
Search1
(Miss
on
this
device.)
Search3
(This
device
global
winner.)
Search2 Search4
(Miss
(Miss
on this
on this
device.)
device)
Figure 10-39. Timing Diagram for Globally Winning Device in Block Number 1
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Document #: 38-02041 Rev. *E
Page 60 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
A B A B A B A B
D1 D2 D3 D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0] stands for the boolean ‘OR’ of the entire4 bus BHI[2:0].
Note: |(LHI(6:0) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss on
this
device.)
Search3
(Miss on
this
device.)
Search2
(Miss
on this
device.)
Search4
(Miss
on this
device.)
Figure 10-40. Timing Diagram for Devices Below the Winning Device in Block Number 1
Document #: 38-02041 Rev. *E
Page 61 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
A B A B A B A B
D1 D2 D3 D4
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss
on this
device.)
Search3
(Miss
on this
device.)
Search2
(Miss
on this
device.)
Search4
(Miss
on this
device.)
Figure 10-41. Timing Diagram for Devices Above the Winning Device in Block Number 2
Document #: 38-02041 Rev. *E
Page 62 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
A B A B A B A B
D1 D2 D3 D4
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
z
A2
z
z
z
0
z
z
0
1
z
WE_L
z
OE_L
z
SSV
z
1
z
SSF
z
1
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss
on this
device.)
Search3
(Hit but not
winner.)
Search2
(Global
winner.)
Search4
(Miss
on this
device.)
Figure 10-42. Timing Diagram for Globally Winning Device in Block Number 2
Document #: 38-02041 Rev. *E
Page 63 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
A B A B A B A B
D1 D2 D3 D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss
on this
device)
Search3
(Miss
on this
device.)
Search2 Search4
(Miss on
(Miss on
this device.) this device.)
Figure 10-43. Timing Diagram for Devices Below the Winning Device in Block Number 2
Document #: 38-02041 Rev. *E
Page 64 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
A B A B A B A B
D1 D2 D3 D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss
on this
device.)
Search3
(Miss
on this
device.)
Search2
(Miss
on this
device.)
Search4
(Miss
on this
device.)
Figure 10-44. Timing Diagram for Devices Above the Winning Device in Block Number 3
Document #: 38-02041 Rev. *E
Page 65 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
A B A B A B A B
D1 D2 D3 D4
z
A1
z
0
z
z
z
z
0
WE_L
z
OE_L
z
SSV
z
1
z
SSF
z
1
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
1
z
Search1
(Global
winner.)
Search3
(Miss
on this
device.)
Search2 Search4
(Miss
(Hit
on this
but not
device.)
global
winner.)
Figure 10-45. Timing Diagram for Globally Winning Device in Block Number 3
Document #: 38-02041 Rev. *E
Page 66 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
A B A B A B A B
D1 D2 D3 D4
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss
on this
device.)
Search3
(Miss
on this
device.)
Search2 Search4
(Miss on (Miss
on this
this
device.) device.)
Figure 10-46. Timing Diagram for Devices Below the Winning Device in Block Number 3
Except Device 30 (the Last Device)
Document #: 38-02041 Rev. *E
Page 67 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
Search3
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
A B A B A B A B
D1 D2 D3 D4
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
z
SADR[21:0]
CE_L
0
ALE_L
0
WE_L
OE_L
1
0
SSV
0
SSF
z
z
0
z
1
z
1
z
0
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 1, LDEV = 1.
Note: |(BHI[2:0)] stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
0
Search1
(Hit on
some
device
above.)
0
Search3
(Hit on
some
device
above.)
Search4
Search2
(Hit on some (Global miss; this device
device above.)default driver.)
Figure 10-47. Timing Diagram for Device Number 6 in Block Number 3 (Device 30 in Depth-Cascaded Table)
The following is the sequence of operation for a single 136-bit Search command (also refer to “Command and Command
Parameters,” Subsection 10.2 on page 18).
• Cycle A: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:7] signals must be driven with
the bits that will be driven on SADR[21:20] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data ([135:68])
in order to be compared against all even locations. The CMD[2] signal must be driven to logic 0.
• Cycle B: The host ASIC continues to drive the CMDV HIGH and to apply Search command code (10) on CMD[1:0]. CMD[5:2]
must be driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles
A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching
entry and the hit flag (see page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with 68-bit data ([67:0])to be compared
against all odd locations.
The logical 136-bit Search operation is as shown in the following Figure 10-48. The entire table of 31 devices (consisting of 136-bit
entries) is compared against a 136-bit word K that is presented on the DQ bus in cycles A and B of the command using the GMR
and local mask bits. The GMR is the 136-bit word specified by the even and odd global mask pair selected by the GMR Index in
the command’s cycle A.
Document #: 38-02041 Rev. *E
Page 68 of 127
CYNSE70064A
The 136-bit word K that is presented on the DQ bus in cycles A and B of the command is also stored in the even and odd
comparand registers specified by the Comparand Register Index in the command’s cycle B. In ×136 configurations, the even and
odd comparand registers can subsequently be used by the Learn command in only the first non-full device. Note. The Learn
command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more than one
block. The word K that is presented on the DQ bus in cycles A and B of the command is compared with each entry in the table
starting at location 0. The first matching entry’s location address L is the winning address that is driven as part of the SRAM
address on the SADR[21:0] lines (see Section 12.0, “SRAM Addressing” on page 100). The global winning device will drive the
bus in a specific cycle. On global miss cycles the device with LRAM = 1 (the default driving device for the SRAM bus) and
LDEV = 1 (the default driving device for SSF and SSV signals) will be the default driver for such missed cycles. Note. During
136-bit searches of 136-bit-configured tables, the Search hit will always be at an even address.
0
135
Must be same in each of the 31
devices
Even
Odd
GMR
B
A
K
Location 135
address
0
Comparand Register (even)
2
A
4
6
Comparand Register (odd)
B
0
0
67
L
(First matching entry)
Will be same in each of the 31
devices
1015806
CFG = 01010101
(136-bit configuration)
Figure 10-48. ×136 Table with 31 Devices
The Search command is a pipelined operation. It executes a Search at half the rate of the frequency of CLK2X for 136-bit searches
in ×136-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 136-bit Search command cycle
(two CLK2X cycles) is shown in Table 10-24.
Table 10-24. The Latency of Search from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
16K × 136 bits
128K × 136 bits
496K × 136 bits
Latency in CLK Cycles
4
5
6
The latency of a Search from command to the SRAM access cycle is 6 for 1–31 devices in the table and where TLSZ = 10. In
addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-25.
Table 10-25. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
Document #: 38-02041 Rev. *E
Number of CLK Cycles
0
1
2
3
4
5
6
7
Page 69 of 127
CYNSE70064A
10.12
272-bit Search on Tables Configured as û272 Using a Single CYNSE70064A Device
Figure 10-49 shows the timing diagram for a Search command in the 272-bit-configured table (CFG = 10101010) consisting of a
single device for one set of parameters: TLSZ = 00, HLAT = 001, LRAM = 1, and LDEV = 1. The hardware diagram for this Search
subsystem is shown in Figure 10-50.
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
01
CMD[2]
CMD[8:2]
A B A B A B A B
DQ
A B C D A B C D
D2
D1
SADR[21:0]
A1
CE_L
ALE_L
WE_L
1
0
1
1
0
1
1
0
OE_L
1
0
SSV
0
1
SSF
0
1
1
0
0
0
1
0
CFG = 10101010, HLAT = 001, TLSZ = 00, LRAM = 1, LDEV = 1.
Search1 Search2
Hit
Miss
Figure 10-49. Timing Diagram for 272-bit Search (One Device)
BHI[2:0]
DQ[67:0]
6
5
CYNSE70064A
CMDV, CMD[8:0]
4
3
LHI
2
1
0
SRAM
SSF, SSV
BHO[2:0]
LHO[1]
LHO[0]
Figure 10-50. Hardware Diagram for a Table with One Device
The following is the sequence of operation for a single 136-bit Search command (also refer to Subsection 10.2, “Commands and
Command Parameters” on page 18).
• Cycle A: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair used for bits [271:136] of the data being searched. DQ[67:0] must be
driven with the 68-bit data ([271:204]) to be compared to all locations 0 in the four 68-bits-word page. The CMD[2] signal must
be driven to logic 1. Note. CMD[2] = 1 signals that the Search is a ×272-bit Search. CMD[8:3] in this cycle is ignored.
Document #: 38-02041 Rev. *E
Page 70 of 127
CYNSE70064A
• Cycle B: The host ASIC continues to drive the CMDV HIGH and continues to apply the command code of Search command
(10) on CMD[1:0]. The DQ[67:0] is driven with the 68-bit data ([204:136]) to be compared to all locations 1 in the four 68-bits-word
page.
• Cycle C: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair used for bits [135:0] of the data being searched. CMD[8:7] signals must
be driven with the bits that will be driven on SADR[21:20] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit
data ([135:68]) to be compared to all locations 2 in the four 68-bits-word page. The CMD[2] signal must be driven to logic 0.
• Cycle D: The host ASIC continues to drive the CMDV HIGH and applies Search command code (10) on CMD[1:0]. CMD[8:6]
signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag
(see page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with the 68-bit data ([67:0]) to be compared to all locations
3 in the four 68-bits-word page. CMD[5:2] is ignored because the Learn instruction is not supported for x272 tables.
Note. For 272-bit searches, the host ASIC must supply four distinct 68-bit data words on DQ[67:0] during cycles A, B, C, and D.
The GMR index in cycle A selects a pair of GMRs that apply to DQ data in cycles A and B. The GMR index in cycle C selects a
pair of GMRs that apply to DQ data in cycles C and D.
The logical 272-bit Search operation is shown in Figure 10-51. The entire table of 272-bit entries is compared to a 272-bit word
K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the
272-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command’s cycles A and C. The 272-bit
word K that is presented on the DQ bus in cycles A, B, C and D of the command is compared with each entry in the table starting
at location 0. The first matching entry’s location address L is the winning address that is driven as part of the SRAM address on
SADR[21:0] lines (See “SRAM Addressing” on page 100.). Note. The matching address is always going to be location 0 in a
four-entry page for a 272-bit Search (two LSBs of the matching index will be 00).
0
271
GMR
K
Location 271
address
0
4
8
12
0
1
A
2
B
3
C
D
0
L
32764
(First matching entry)
CFG = 10101010 (272-bit configuration)
Figure 10-51. ×272 Table with One Device
The Search command is a pipelined operation and executes at one-fourth the rate of the frequency of CLK2X for 272-bit searches
in ×272-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 272-bit Search command
(measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in Table 10-26.
Table 10-26. The Latency of Search from C and D Cycles to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
8K × 272 bits
64K × 272 bits
248K × 272 bits
Latency in CLK Cycles
4
5
6
The latency of a Search from command to SRAM access cycle is 4 for only a single device in the table and TLSZ = 00. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-27.
Table 10-27. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
Document #: 38-02041 Rev. *E
Number of CLK Cycles
0
1
2
3
4
5
6
7
Page 71 of 127
CYNSE70064A
10.13
272-bit Search on Tables x272-configured Using up to Eight CYNSE70064A Devices
The hardware diagram of the Search subsystem of eight devices is shown in Figure 10-52. The following are the parameters
programmed in the eight devices.
• First seven devices (devices 0–6): CFG = 10101010, TLSZ = 01, HLAT = 000, LRAM = 0, and LDEV = 0.
• Eighth device (device 7): CFG = 10101010, TLSZ = 01, HLAT = 000, LRAM = 1, and LDEV = 1.
Note. All eight devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be
programmed with LRAM = 1 and LDEV = 1 (device number 7 in this case). All other upstream devices must be programmed with
LRAM = 0 and LDEV = 0 (devices 0 through 6 in this case).
Figure 10-53 shows the timing diagram for a Search command in the 272-bit-configured table of eight devices for device
number 0. Figure 10-54 shows the timing diagram for a Search command in the 272-bit-configured table of eight devices for
device number 1. Figure 10-55 shows the timing diagram for a Search command in the 272-bit-configured table of eight devices
for device number 7 (the last device in this specific table). For these timing diagrams three 272-bit searches are performed
sequentially. The following Hit/Miss assumptions were made as shown in Table 10-28.
Table 10-28. Hit/Miss Assumption
Search Number
Device 0
Device 1
Devices 2–6
Device 7
Document #: 38-02041 Rev. *E
1
Hit
Miss
Miss
Miss
2
Miss
Hit
Miss
Miss
3
Miss
Miss
Miss
Miss
Page 72 of 127
CYNSE70064A
SRAM
BHI[2:0]
6
LHO[1]
SSF, SSV
BHI[2:0]
LHO[1]
DQ[67:0]
CMDV
CMD[8:0]
3
LHI
CYNSE70064A #0
6
BHI[2:0]
5
5
4
4
LHO[1]
BHI[2:0]
2
6 5 4 3
LHI
CYNSE70064A #2
2
1
0
LHO[0]
1
0
6 5 4 3
2
LHI
CYNSE70064A #3
LHO[0]
1
0
6 5 4
3
CYNSE70064A #4
LHI
LHO[0]
1
0
BHI[2:0] 3
2 1
LHI
0
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70064A #6
LHO[0]
1
LHI
0
LHO[0]
BHI[2:0]
2
1
LHO[0]
3
LHI
CYNSE70064A #1
LHO[1]
BHI[2:0]3
2
0
2
6 5
4
CYNSE70064ALHI
#5
LHO[0]
6
5
4
LHI
CYNSE70064A #7
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 10-52. Hardware Diagram for a Table with Eight Devices
Document #: 38-02041 Rev. *E
Page 73 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
0
LHO[1:0]
SADR[21:0]
z
z
CE_L
z
ALE_L
A1
0
0
z
z
z
1
z
z
1
z
z
1
z
CFG = 10101010, HLAT = 000, TLSZ = 01, LRAM = 0, LDEV = 0.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(This
device
is the
global
winner.)
z
WE_L
z
OE_L
SSV
SSF
Search2
(Miss
on this
device.)
Search3
(Miss
on this
device.)
Figure 10-53. Timing Diagram for 272-bit Search Device Number 0
Document #: 38-02041 Rev. *E
Page 74 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
01
Search3
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
LHO[1:0]
SADR[21:0]
z
CE_L
z
A2
0
z
ALE_L
0
z
WE_L
z
OE_L
z
SSV
z
1
z
SSF
z
1
z
CFG = 10101010, HLAT = 000, TLSZ = 01, LRAM = 0, LDEV = 0.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
1
Search1
(Miss
on this
device.)
z
Search3
(Miss
on this
device.)
Search2
(This device
is global winner.)
Figure 10-54. Timing Diagram for 272-bit Search Device Number 1
Document #: 38-02041 Rev. *E
Page 75 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
LHO[1:0]
SADR[21:0]
CE_L
ALE_L
WE_L
1
0
SSV
0
SSF
0
z
z
0
OE_L
z
z
0
1
z
z
z
z
0
z
0
0
1
0
1
0
z
0
0
CFG = 10101010, HLAT = 000, TLSZ = 01, LRAM = 1, LDEV = 1.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search2 Search3
(Global
(Miss
(Miss
on this
miss.)
on this
device.)
device.)
Figure 10-55. Timing Diagram for 272-bit Search Device Number 7 (Last Device)
The following is the sequence of operation for a single 272-bit Search command (also See “Commands and Command Parameters” on page 18.).
• Cycle A: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair used for bits [271:136] of the data being searched in this operation.
DQ[67:0] must be driven with the 68-bit data ([271:204]) to be compared against all locations 0 in the four-word 68-bit page.
The CMD[2] signal must be driven to logic 1. Note. CMD[2] = 1 signals that the Search is a ×272 bit Search. CMD[8:3] in this
cycle is ignored.
• Cycle B: The host ASIC continues to drive the CMDV HIGH and applies Search command code (10) on CMD[1:0]. The
DQ[67:0] is driven with the 68-bit data ([203:136]) to be compared against all locations 1 in the four 68-bits-word page.
• Cycle C: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair used for bits [135:0] of the data being searched. CMD[8:7] signals must
be driven with the bits that will be driven on SADR[21:20] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit
data ([135:68]) to be compared against all locations 2 in the four 68-bits-word page. The CMD[2] signal must be driven to logic 0.
• Cycle D: The host ASIC continues to drive the CMDV HIGH and applies Search command code (10) on CMD[1:0]. CMD[8:6]
signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag
(see page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with the 68-bit data ([67:0]) to be compared to all locations 3
in the four 68-bits-word page. CMD[5:2] is ignored because the Learn instruction is not supported for x272 tables.
Note. For 272-bit searches, the host ASIC must supply four distinct 68-bit data words on DQ[67:0] during cycles A, B, C, and D.
The GMR index in cycle A selects a pair of GMRs in each of the eight devices that apply to DQ data in cycles A and B. The GMR
index in cycle C selects a pair of GMRs in each of the eight devices that apply to DQ data in cycles C and D.
The logical 272-bit Search operation is shown in Figure 10-56. The entire table of 272-bit entries is compared to a 272-bit word
K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and the local mask bits. The GMR is
the 272-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command’s cycles A and C in each of
the eight devices. The 272-bit word K that is presented on the DQ bus in cycles A, B, C, and D of the command is compared to
Document #: 38-02041 Rev. *E
Page 76 of 127
CYNSE70064A
each entry in the table starting at location 0. The first matching entry’s location address L is the winning address that is driven as
part of the SRAM address on the SADR[21:0] lines (See “SRAM Addressing” on page 100.). Note. The matching address is
always going to be a location 0 in a four-entry page for 272-bit Search (two LSBs of the matching index will be 00).
0
271
GMR
K
0
2
1
A
B
3
C
Must be same in each of the eight
devices
D
0
Location 271
address
0
4
8
12
L
(First matching entry)
262140
CFG = 10101010 (272-bit configuration)
Figure 10-56. ×272 Table with Eight Devices
The Search command is a pipelined operation and executes Search at one fourth the rate of the frequency of CLK2X for 272-bit
searches in x272-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 272-bit Search command
(measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in Table 10-29.
Table 10-29. The Latency of Search from C and D cycles to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
8K × 272 bits
64K × 272 bits
248K × 272 bits
Latency in CLK Cycles
4
5
6
The latency of Search from command to SRAM access cycle is 5 for only a single device in the table and TLSZ = 01. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-30.
Table 10-30. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
10.14
Number of CLK Cycles
0
1
2
3
4
5
6
7
272-bit Search on Tables Configured as ×272 Using up to 31 CYNSE70064A Devices
The hardware diagram of the Search subsystem of 31 devices is shown in Figure 10-57. Each of the four blocks in the diagram
represents a block of eight CYNSE70064A devices, except the last which has seven devices. The diagram for a block of eight
devices is shown in Figure 10-58. The following are the parameters programmed into the 31 devices.
• First thirty devices (devices 0–29): CFG = 10101010, TLSZ = 10, HLAT = 000, LRAM = 0, and LDEV = 0.
• Thirty-first device (device 30): CFG = 10101010, TLSZ = 10, HLAT = 000, LRAM = 1, and LDEV = 1.
Note. All 31 devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be
programmed with LRAM = 1 and LDEV = 1 (device number 30 in this case). All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (devices 0 through 29 in this case).
The timing diagrams referred to in this paragraph reference the Hit/Miss assumptions defined in Table 10-31. For the purpose of
illustrating the timings, it is further assumed that there is only one device with the matching entry in each block. Figure 10-59
Document #: 38-02041 Rev. *E
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CYNSE70064A
shows the timing diagram for a Search command in the 272-bit-configured table consisting of 31 devices for each of the eight
devices in block number 0. Figure 10-60 shows the timing diagram for a Search command in the 272-bit-configured table of 31
devices for all devices above the winning device in block number 1. Figure 10-61 shows the timing diagram for the globally winning
device (the final winner within its own and all blocks) in block number 1. Figure 10-62 shows the timing diagram for all the devices
below the globally winning device in block number 1. Figure 10-63, Figure 10-64, and Figure 10-65, respectively, show the timing
diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winning
device for block number 2. Figure 10-66, Figure 10-67, Figure 10-68, and Figure 10-69, respectively, show the timing diagrams
of the device above the globally winning device, the globally winning device, the devices below the globally winning device (except
device 30), and last device (device 30) for block number 3.
The 272-bit Search operation is pipelined and executes as follows. Four cycles from the last cycle of the Search command each
of the devices knows the outcome internal to it for that operation. In the fifth cycle from the Search command, the devices in a
block (which is less than or equal to eight devices resolving the winner within them using an LHI[6:0] and LHO[1:0] signalling
mechanism) arbitrate for a winner. In the sixth cycle after the Search command, the blocks of devices resolve the winning block
through a BHI[2:0] and BHO[2:0] signalling mechanism. The winning device within the winning block is the global winning device
for the Search operation.
Table 10-31. Hit/Miss Assumption
Search Number
Block 0
Block 1
Block 2
Block 3
Document #: 38-02041 Rev. *E
1
Miss
Miss
Miss
Hit
2
Miss
Miss
Hit
Hit
3
Miss
Hit
Hit
Miss
Page 78 of 127
CYNSE70064A
BHI[2]
SSF, SSV
BHI[1]
BHI[0] GND
Block of 8 CYNSE70064As block 0 (devices 0–7)
BHO[2]
BHO[1]
BHO[0]
SRAM
BHI[2]
BHI[1]
BHI[0] GND
Block of 8 CYNSE70064As block 1 (devices 8–15)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8 CYNSE70064As block 2 (devices 16–23)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
Block of 7 CYNSE70064As block 3 (devices 24–30)
BHO[2]
BHO[1]
BHO[0]
CMD[8:0], CMDV
DQ[67:0]
Figure 10-57. Hardware Diagram for a Table with 31 Devices
Document #: 38-02041 Rev. *E
Page 79 of 127
CYNSE70064A
SRAM
BHI[2:0]
6
BHI[2:0]
LHO[1]
BHI[2:0]
LHO[1]
DQ[67:0]
CMDV
CMD[8:0]
3
LHI
CYNSE70064A #0
6
BHI[2:0]
5
5
4
4
LHO[1]
BHI[2:0]
2
6 5 4 3
LHI
CYNSE70064A #2
2
0
LHO[0]
0
6 5 4 3
2
LHI
CYNSE70064A #3
LHO[0]
1
0
6 5 4
3
CYNSE70064A #4
LHI
LHO[0]
1
0
2 1
LHI
0
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70064A #6
LHO[0]
1
LHI
1
1
BHI[2:0] 3
2
0
LHO[0]
BHI[2:0]
BHI[2:0]3
1
LHO[0]
3
LHI
CYNSE70064A #1
LHO[1]
SSV, SSF
2
0
2
6 5
4
CYNSE70064ALHI
#5
LHO[0]
6
5 4
LHI
CYNSE70064A #7
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 10-58. Hardware Diagram for A Block of up to Eight Devices
Document #: 38-02041 Rev. *E
Page 80 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D2
D1
D3
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search3
Search1
(Misson
(Misson
this device.) Search2 this device.)
(Miss on
this device.)
Figure 10-59. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device)
Document #: 38-02041 Rev. *E
Page 81 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss on
this device.)
Search3
(Miss on
this device.)
Search2
(Miss on
this device.)
Figure 10-60. Timing Diagram for Each Device Above the Winning Device in Block Number 1
Document #: 38-02041 Rev. *E
Page 82 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
01
Search3
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
z
A3
z
CE_L
ALE_L
0
z
0
WE_L
z
OE_L
z
SSV
z
1
SSF
z
1
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
1
Search1
(Miss on
this device.)
Search3
(This device
global winner.)
Search2
(Miss on
this device.)
Figure 10-61. Timing Diagram for Globally Winning Device in Block Number 1
Document #: 38-02041 Rev. *E
Page 83 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
0
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss on
this device.)
Search3
(Miss on
this device.)
Search2
(Miss on
this device.)
Figure 10-62. Timing Diagram for Devices Below the Winning Device in Block Number 1
Document #: 38-02041 Rev. *E
Page 84 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
0
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss on
this device.)
Search3
(Miss on this
device; hit in
block 0 or 1.)
Search2
(Miss on
this device.)
Figure 10-63. Timing Diagram for Devices Above the Winning Device in Block Number 2
Document #: 38-02041 Rev. *E
Page 85 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
0
z
z
A2
z
z
z
0
z
z
z
0
ALE_L
z
WE_L
z
OE_L
z
SSV
z
1
z
SSF
z
1
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss on
this device.)
z
1
Search3
(Hit but not
winner.)
Search2
(Global
winner.)
Figure 10-64. Timing Diagram for Globally Winning Device in Block Number 2
Document #: 38-02041 Rev. *E
Page 86 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
LHO[1:0]
0
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss on
this device.)
Search3
(Miss on
this device.)
Search2
(Miss on
this device.)
Figure 10-65. Timing Diagram for Devices Below the Winning Device in Block Number 2
Document #: 38-02041 Rev. *E
Page 87 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
0
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Miss on
this device.)
Search3
(Miss on
this device.)
Search2
(Miss on
this device.)
Figure 10-66. Timing Diagram for Devices Above the Winning Device in Block Number 3
Document #: 38-02041 Rev. *E
Page 88 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
z
z
CE_L
ALE_L
z
A1
z
z
0
z
0
1
z
z
1
z
z
1
z
WE_L
z
OE_L
z
SSV
SSF
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
(Global
winner.)
Search3
(Miss on
this device.)
Search2
(Hit but not
global winner.)
Figure 10-67. Timing Diagram for Globally Winning Device in Block Number 3
Document #: 38-02041 Rev. *E
Page 89 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
01
Search3
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
LHO[1:0]
0
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
Search3
(Miss on
(Miss on
this device.)
this device.)
Search2
(Miss on
this device.)
Figure 10-68. Timing Diagram for Devices Below the Winning Device in Block Number 3
Except Device 30 (the Last Device)
Document #: 38-02041 Rev. *E
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CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
01
Search3
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0)]
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
CE_L
ALE_L
WE_L
z
z
SADR[21:0]
0
0
OE_L
1
0
SSV
0
z
z
z
z
z
0
0
z
z
0
0
1
z
1
0
z
z
0
0
0
0
SSF
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 1, LDEV = 1.
Search2
Search3
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Search1
(Hit
on some (Hit on some
(Hit
on
some
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
device above.) device above.) device above.)
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-69. Timing Diagram of the Last Device in Block Number 3 (Device 30 in the Table)
The following is the sequence of operation for a single 272-bit Search command (also refer to Subsection 10.2, “Commands and
Command Parameters” on page 18).
• Cycle A: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair used for bits [271:136] of the data being searched. DQ[67:0] must be
driven with the 68-bit data ([271:204])to be compared to all locations 0 in the four 68-bits-word page. The CMD[2] signal must
be driven to logic 1. Note. CMD[2] = 1 signals that the Search is a ×272-bit Search. CMD[8:7] is ignored in this cycle.
• Cycle B: The host ASIC continues to drive the CMDV HIGH and applies Search command (10) on CMD[1:0]. The DQ[67:0]
is driven with the 68-bit data ([203:136]) to be compared to all locations 1 in the four 68-bits-word page.
• Cycle C: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair used for the bits [135:0] of the data being searched. CMD[8:7] signals
must be driven with the bits that will be driven by this device on SADR[21:20] if it has a hit. DQ[67:0] must be driven with the
68-bit data ([135:68]) to be compared to all locations 2 in the four 68-bits-word page. The CMD[2] signal must be driven to logic 0.
• Cycle D: The host ASIC continues to drive the CMDV HIGH and continues to apply Search command code (10) on CMD[1:0].
CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and
the hit flag (see page 14 for a description of SSR[0:7]). The DQ[67:0] is driven with the 68-bit data ([67:0]) to be compared to
all locations 3 in the four 68-bits-word page. CMD[5:2] is ignored because the Learn instruction is not supported for x272 tables.
Note. For 272-bit searches, the host ASIC must supply four distinct 68-bit data words on DQ[67:0] during cycles A, B, C, and D.
The GMR Index in cycle A selects a pair of GMRs in each of the 31 devices that apply to DQ data in cycles A and B. The GMR
Index in cycle C selects a pair of GMRs in each of the 31 devices that apply to DQ data in cycles C and D.
Document #: 38-02041 Rev. *E
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CYNSE70064A
The logical 272-bit Search operation is as shown in Figure 10-70. The entire table of 272-bit entries is compared to a 272-bit word
K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the
272-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command’s cycles A and C in each of the
31 devices. The 272-bit word K that is presented on the DQ bus in cycles A, B, C, and D of the command is compared to each
entry in the table starting at location 0. The first matching entry’s location address L is the winning address that is driven as part
of the SRAM address on the SADR[21:0] lines (See “SRAM Addressing” on page 100.). Note. The matching address is always
going to be location 0 in a four-entry page for 272-bit Search (two LSBs of the matching index will be 00).
0
271
GMR
K
0
2
1
A
B
3
C
Must be same in each
of the 31 devices
D
Location 271
address
0
4
8
12
0
L
(First matching entry)
1015804
CFG = 10101010 (272-bit configuration)
Figure 10-70. ×272 Table with 31 Devices
The Search command is a pipelined operation and executes a Search at one-fourth the rate of the frequency of CLK2X for 272-bit
searches in ×272-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 272-bit Search
command (measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in Table 10-32.
Table 10-32. The Latency of Search from C and D cycles to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
8K × 272 bits
64K × 272 bits
248K × 272 bits
Latency in CLK Cycles
4
5
6
The latency of a Search from command to SRAM access cycle is 6 for only a single device in the table and TLSZ = 10. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-33.
Table 10-33. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
10.15
Number of CLK Cycles
0
1
2
3
4
5
6
7
Mixed-Sized Searches on Tables Configured with Different Widths Using an CYNSE70064A Device
This subsection will cover mixed searches (×68, ×136, and ×272) with tables of different widths (×68, ×136, ×272). The sample
operation shown is for a single device with CFG = 10010000 containing three tables of ×68, ×136, and ×272 widths. The operation
can be generalized to a block of eight to 31 devices using four blocks; the timing and the pipeline operation is the same as
described previously for fixed searches on a table of one-width-size.
Figure 10-71 shows three sequential searches: first, a 68-bit Search on the table configured as ×68, then a 136-bit Search on a
table configured as ×136, and finally a 272-bit Search on the table configured as ×272 bits that each results in a hit. Note. The
DQ[67:66] will be 00 in each of the two A and B cycles of the ×68-bit Search (Search1). DQ[67:66] is 01 in each of the A and B
cycles of the ×136-bit Search (Search2). DQ[67:66] is 10 in each of the A, B, C, and D cycles of the ×272-bit Search (Search3).
By having table designation bits, the CYNSE70064A enables the creation of many tables in a bank of search engines of different
widths.
Document #: 38-02041 Rev. *E
Page 92 of 127
CYNSE70064A
Figure 10-72 shows the sample table. Two bits in each 68-bit entry will need to designated as the table number bits. One example
choice can be the 00 values for the table configured as ×68, 01 values for tables configured as ×136, and 10 values for tables
configured as ×272. For the above explanation, it is further assumed that bits [67:66] for each entry will be designed as such table
designation bits.
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1 Search3
01
01
01
Search2
CMD[1:0]
CMD[2]
CMD[8:2]
A B A B A B A B
DQ
A B A B A B C D
D3
D1 D2
SADR[21:0]
A1
A3
A2
CE_L
1
0
1
0
1
ALE_L
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
WE_L
OE_L
SSV
SSF
1
0
1
0
0
0
CFG = 1010101010101010, HLAT = 010, TLSZ = 00, LRAM = 1, LDEV = 1. Search1
Search2 Search2
×272
×68 ×136
Hit
Hit
Hit
Figure 10-71. Timing Diagram for Mixed Search (One Device)
68
16 K
4K
2K
136
272
CFG = 10010000
Figure 10-72. Multiwidth Configurations Example
10.16
LRAM and LDEV Description
When search engines are cascaded using multiple CYNSE70064As, the SADR, CE_L, and WE_L (three-state signals) are all
tied together. In order to eliminate external pull-ups and pull-downs, one device in a bank is designated as the default driver. For
non-Search or non-Learn cycles (see Subsection 10.17, “Learn Command” on page 94) or Search cycles with a global miss, the
SADR, CE_L, and WE_L signals are driven by the device with the LRAM bit set. It is important that only one device in a bank of
search engines that are cascaded have this bit set. Failure to do so will cause contention on SADR, CE_L, and WE_L and can
potentially cause damage to the device(s).
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CYNSE70064A
Similarly, when search engines using multiple CYNSE70064As are cascaded, SSF and SSV (also three-state signals) are tied
together. In order to eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. For
nonSearch cycles or Search cycles with a global miss the SSF and SSV signals are driven by the device with the LDEV bit set.
It is important that only one device in a bank of search engines that are cascaded together have this bit set. Failure to do so will
cause contention on SSV and SSF and can potentially cause damage to the device(s).
10.17
Learn Command
Bit[0] of each 68-bit data location specifies whether an entry in the database is occupied. If all the entries in a device are occupied,
the device asserts FULO signal to inform the downstream devices that it is full. The result of this communication between
depth-cascaded devices determines the global FULL signal for the entire table. The FULL signal in the last device determines
the fullness of the depth-cascaded table.
The device contains 16 pairs of internal, 68-bit-wide comparand registers that store the comparands as the device executes
searches. On a miss by the Search signalled to ASIC through the SSV and SSF signals (SSV = 1, SSF = 0), the host ASIC can
apply the Learn command to learn the entry from a comparand register to the next-free location (see Subsection 7.8, “NFA
Register” on page 16). The NFA updates to the next-free location following each Write or Learn command.
In a depth-cascaded table, only a single device will learn the entry through the application of a Learn instruction. The determination
of which device is going to learn is based on the FULI and FULO signalling between the devices. The first non-full device learns
the entry by storing the contents of the specified comparand registers to the location(s) pointed to by NFA.
In a ×68-configured table the Learn command writes a single 68-bit location. In a ×136-configured table the Learn command
writes the next even and odd 68-bit locations. In 136-bit mode, bit[0] of the even and odd 68-bit locations is 0, which indicates
that they are cascaded empty, or 1, which indicates that they are occupied.
The global FULL signal indicates to the table controller (the host ASIC) that all entries within a block are occupied and that no
more entries can be learned. The CYNSE70064A updates the signal after each Write or Learn command to a data array. The
Learn command generates a Write cycle to the external SRAM, also using the NFA register as part of the SRAM address (see
Section 12.0, “SRAM Addressing” on page 100).
The Learn command is supported on a single block containing up to eight devices if the table is configured either as a ×68 or
a ×136. The Learn command is not supported for ×272-configured tables.
Learn is a pipelined operation and lasts for two CLK cycles, as shown in Figure 10-73 where TLSZ = 00, and Figure 10-74 and
Figure 10-75 where TLSZ = 01. Figure 10-74 and Figure 10-75 assume that the device performing the Learn operation is not the
last device in the table and has its LRAM bit set to 0. Note. The OE_L for the device with the LRAM bit set goes HIGH for two
cycles for each Learn (one during the SRAM Write cycle, and one the cycle before). The latency of the SRAM Write cycle from
the second cycle of the instruction is shown in Table 10-34.
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Page 94 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Learn1 X Learn2 X
CMD[1:0]
Comp2
Comp1
X
X
CMD[8:2]
1A 1B
DQ
SADR[21:0]
z
X
X
X
X
z
z
CE_L
1
WE_L
1
OE_L
0
SSV
0
SSF
0
A1
0
0
z
z
A2
0
0
1
1
1
0
TLSZ = 00, LRAM = 1, LDEV = 1.
Figure 10-73. Timing Diagram of Learn (TLSZ = 00)
Document #: 38-02041 Rev. *E
Page 95 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Learn1 X Learn2 X
CMD[1:0]
Comp2
Comp1
X
X
CMD[8:2]
1A 1B
DQ
z
z
SADR[21:0]
CE_L
z
WE_L
z
OE_L
z
SSV
z
SSF
z
X
X
X
X
z
A1
z
A2
0
0
0
0
z
TLSZ = 01, LRAM = 0, LDEV = 0.
Figure 10-74. Timing Diagram of Learn (Except on the Last Device [TLSZ = 01])
Document #: 38-02041 Rev. *E
Page 96 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Learn1 X Learn2 X
CMD[1:0]
Comp2
Comp1
X
X
CMD[8:2]
1A 1B
DQ
SADR[21:0]
CE_L
WE_L
z
X
X
X
X
z
z
z
z
1
z
1
OE_L
0
SSV
0
SSF
0
z
1
1
z
z
1
z
1
1
0
TLSZ = 01, LRAM = 1, LDEV = 1.
Figure 10-75. Timing Diagram of Learn on Device Number 7 (TLSZ = 01)
Table 10-34. The Latency of SRAM Write Cycle from Second Cycle of Learn Instruction
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Latency in CLK Cycles
4
5
6
The Learn operation lasts two CLK cycles. The sequence of operation is as follows.
• Cycle 1A: The host ASIC applies the Learn instruction on CMD[1:0] using CMDV = 1. The CMD[5:2] field specifies the index
of the comparand register pair that will be written in the data array in the 136-bit-configured table. For a Learn in a 68-bit-configured table, the even-numbered comparand specified by this index will be written. CMD[8:7] carries the bits that will be driven
on SADR[21:20] in the SRAM Write cycle.
• Cycle 1B: The host ASIC continues to drive the CMDV to 1, the CMD[1:0] to 11, and the CMD[5:2] with the comparand pair
index. CMD[6] must be set to 0 if the Learn is being performed on a 68-bit-configured table, and to 1 if the Learn is being
performed on a 136-bit-configured table.
• Cycle 2: The host ASIC drives the CMDV to 0.
At the end of cycle 2, a new instruction can begin. The latency of the SRAM Write is the same as the Search to the SRAM Read
cycle. It is measured from the second cycle of the Learn instruction.
11.0
Depth-Cascading
The Search engine application can depth-cascade the devices to various table sizes of different widths (68 bits, 136 bits, or 272
bits). The devices perform all the necessary arbitration to decide which device will drive the SRAM bus. The latency of the
searches increases as the table size increases; the Search rate remains constant.
Document #: 38-02041 Rev. *E
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CYNSE70064A
11.1
Depth-Cascading up to Eight Devices (One Block)
Figure 11-1 shows how up to eight devices can be cascaded to form 256K × 68, 128K × 136, or 64K × 272 tables. It also shows
the interconnection between the devices for depth-cascading. Each Search engine asserts the LHO[1] and LHO[0] signals to
inform downstream devices of its result. The LHI[6:0] signals for a device are connected to LHO signals of the upstream devices.
The host ASIC must program the TLSZ to 01 for each of up to eight devices in a block. Only a single device drives the SRAM
bus in any single cycle.
SRAM
6 5 4 3 2 1 0
BHI[2:0]
CYNSE70064A #0LHI
LHO[1]
LHO[0]
SSF, SSV
DQ[67:0]
CMDV
CMD[8:0]
6
BHI[2:0]
LHO[1]
BHI[2:0]
5
4
3
LHI
CYNSE70064A #1
2
6 5 4 3
LHI
CYNSE70064A #2
2
LHO[1]
BHI[2:0]
0
6 5 4 3
2
LHI
CYNSE70064A #3
LHO[0]
1
0
6 5 4
3
CYNSE70064A #4
LHI
LHO[0]
1
0
BHI[2:0] 3
2 1
LHI
0
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70064A #6
LHO[0]
1
LHI
LHO[0]
LHO[0]
BHI[2:0]
2
0
1
LHO[1]
BHI[2:0]3
1
0
2
6 5
4
CYNSE70064ALHI
#5
LHO[0]
6
5
4
LHI
CYNSE70064A #7
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 11-1. Depth-Cascading to Form a Single Block
Document #: 38-02041 Rev. *E
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CYNSE70064A
11.2
Depth-Cascading up to 31 Devices (Four Blocks)
Figure 11-2 shows how to cascade up to four blocks. Each block contains up to eight CYNSE70064A devices except the last,
and the interconnection within each was shown in the previous subsection with the cascading of up to eight devices in a block.
Note. The interconnection between blocks for depth-cascading is important. For each Search, a block asserts BHO[2], BHO[1],
and BHO[0]. The BHO[2:0] signals for a block are the signals taken only from the last device in the block. For all other devices
within that block, these signals stay open and floating. The host ASIC must program the table size (TLSZ) field to 10 in each of
the devices for cascading up to 31 devices (in up to four blocks).
BHI[2]
SSF, SSV
BHI[1]
BHI[0]
GND
SRAM
Block of 8 CYNSE70064As Block 0 (devices 0–7)
BHO[2]
BHI[2]
BHO[1]
BHI[1]
BHO[0]
BHI[0]
GND
Block of 8 CYNSE70064As Block 1 (devices 8–15)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8 CYNSE70064As Block 2 (devices 16–23)
BHO[2]
BHO[1]
BHO[0]
DQ[67:0]
CMD[8:0], CMDV
BHI[2]
BHI[1]
BHI[0]
Block of 7 CYNSE70064As Block 3 (devices 24-30)
BHO[2]
BHO[1]
BHO[0]
Figure 11-2. Depth-Cascading Four Blocks
11.3
Depth-Cascading for a FULL Signal
Bit[0] of each of the 68-bit entries is designated as a special bit (1 = occupied; 0 = empty). For each Learn or PIO Write to the
data array, each device asserts FULO[1] and FULO[0] if it does not have any empty locations within it (see Figure 11-3). Each
device combines the FULO signals from the devices above it with its own full status to generate a FULL signal that gives the full
status of the table up to the device asserting the FULL signal. Figure 11-3 shows the hardware connection diagram for generating
the FULL signal that goes back to the ASIC. In a depth-cascaded block of up to eight devices, the FULL signal from the last device
should be fed back to the ASIC controller to indicate the fullness of the table. The FULL signal of the other devices should be left
open. Note. The Learn instruction is supported for only up to eight devices, whereas FULL cascading is allowed only for one
block in tables containing more than eight devices. In tables for which a Learn instruction is not going to be used, the bit[0] of
each 68-bit entry should always be set to 1.
Document #: 38-02041 Rev. *E
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CYNSE70064A
VDDQ
DQ[67:0]
6 5 4 3
CYNSE70064A FULI
FULO[1]
2
1
0
FULO[0]
FULL
6 5 4 3
CYNSE70064A FULI
2
1
0
FULO[0]
FULO[1]
FULL
6 5 4 3 2
1
CYNSE70064A FULI
FULO[0]
FULO[1]
6 5 4 3
2
FULI
CYNSE70064A
FULO[0]
FULO[1]
6 5 4 3
CYNSE70064A FULI
FULO[0]
3
3
2 1
FULI
0
2 1
FULI
VDDQ
0
2
1
1
VDDQ
0
FULL
VDDQ
FULL
VDDQ
FULL
VDDQ
FULL
VDDQ
0
0
4 FULI
6 5
CYNSE70064A
FULO[0]
6
5
CYNSE70064A
FULO[0]
4
FULI
FULL
3
2 1
FULI
0
6 5 4
CYNSE70064A FULI
FULL
FULO[1] FULO[0]
Figure 11-3. Full Generation in a Cascaded Table
12.0
SRAM Addressing
Table 12-1 describes the commands used to generate addresses on the SRAM address bus. The index [14:0] field contains the
address of a 68-bit entry that results in a hit in 68-bit-configured partition. It is the address of the 68-bit entry that lies at the 136-bit
page, and the 272-bit page boundaries in 136-bit- and 272-bit-configured quadrants, respectively.
Section 7.0, “Registers” on page 13 of this specification, describes the NFA and SSR registers. ADR[14:0] contains the address
supplied on the DQ bus during PIO access to the CYNSE70064A. Command bits 8, and 7 {CMD[8:7]} are passed from the
command to the SRAM address bus. See Section 10.0, “Commands” on page 18, for more information. ID[4:0] is the ID of the
device driving the SRAM bus (see Section 18.0, “Pinout Descriptions and Package Diagrams” on page 121, for more information).
Document #: 38-02041 Rev. *E
Page 100 of 127
CYNSE70064A
12.1
Generating an SRAM BUS Address
Table 12-1. SRAM Bus Address
Command
Search
Learn
PIO Read
PIO Write
Indirect Access
12.2
SRAM Operation
Read
Write
Read
Write
Write/Read
21
C8
C8
C8
C8
C8
20
C7
C7
C7
C7
C7
[19:15]
ID[4:0]
ID[4:0]
ID[4:0]
ID[4:0]
ID[4:0]
[14:0]
Index[14:0]
NFA[14:0]
ADR14:0]
ADR[14:0]
SSR[14:0]
SRAM PIO Access
The remainder of Section 12.0 describes SRAM Read and SRAM Write operations.
SRAM Read enables Read access to the off-chip SRAM containing associative data. The latency from the issuance of the Read
instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will be depend
on the value programmed for the TLSZ parameter in the device configuration register. The latency of the ACK from the Read
instruction is the same as the latency of the Search instruction to the SRAM address plus the HLAT programmed in the configuration register. Note. SRAM Read is a blocking operation—no new instruction can begin until the ACK is returned by the selected
device performing the access.
SRAM Write enables Write access to the off-chip SRAM containing associative data. The latency from the second cycle of the
Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will depend
on the TLSZ value parameter programmed in the device configuration register. Note. SRAM Write is a pipelined operation—new
instruction can begin right after the previous command has ended.
12.3
SRAM Read with a Table of One Device
SRAM Read enables Read access to the off-chip SRAM containing associative data. The latency from the issuance of the Read
instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will depend on
the TLSZ value parameter programmed in the device configuration register. The latency of the ACK from the Read instruction is
the same as the latency of the Search instruction to the SRAM address plus the HLAT programmed in the configuration register.
The following explains the SRAM Read operation in a table with only one device that has the following parameters: TLSZ = 00,
HLAT = 000, LRAM = 1, and LDEV = 1. Figure 12-1 shows the associated timing diagram. For the following description, the
selected device refers to the only device in the table because it is the only device to be accessed.
• Cycle 1A: The host ASIC applies the Read instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the address,
with DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the
DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[21:20] on CMD[8:7].
• Cycle 1B: The host ASIC continues to apply the Read instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the
address with DQ[20:19] set to 10 to select the SRAM address.
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[67:0] and drives ACK from High-Z to LOW.
• Cycle 5: The selected device drives the Read address on SADR[21:0]; it also drives ACK HIGH, CE_L LOW, and ALE_L LOW.
• Cycle 6: The selected device drives CE_L HIGH, ALE_L HIGH, the SADR bus, the DQ bus in a three-state condition, and
ACK LOW.
At the end of cycle 6, the selected device floats ACK in a three-state condition, and a new command can begin.
Document #: 38-02041 Rev. *E
Page 101 of 127
CYNSE70064A
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
CLK2X
PHS_L
CMDV
CMD[1:0]
Read
CMD[8:2]
A
B
Address
DQ
z
z
OE_L
0
WE_L
1
CE_L
1
0
1
1
0
1
ALE_L
SADR
z
ACK
z
SSV
0
SSF
Address
0
1
z
z
0
0
TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1
DQ driven by CYNSE70064A
Figure 12-1. SRAM Read Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1)
12.4
SRAM Read with a Table of up to Eight Devices
The following explains the SRAM Read operation completed through a table of up to eight devices using the following parameters:
TLSZ = 01. Figure 12-2 diagrams a block of eight devices. The following assumes that SRAM access is successfully achieved
through CYNSE70064A device number 0. Figure 12-3 and Figure 12-4 show timing diagrams for device number 0 and device
number 7, respectively.
• Cycle 1A: The host ASIC applies the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21]
lines. During this cycle the host ASIC also supplies SADR[21:20] on CMD[8:7].
• Cycle 1B: The host ASIC continues to apply the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
address, with DQ[20:19] set to 10 to select the SRAM address.
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[67:0].
• Cycle 5: The selected device continues to drive DQ[67:0] and drives ACK from High-Z to LOW.
• Cycle 6: The selected device drives the Read address on SADR[21:0]. It also drives ACK HIGH, CE_L LOW, WE_L HIGH,
and ALE_L LOW.
• Cycle 7: The selected device drives CE_L, ALE_L, WE_L, and DQ bus in a three-state condition. It continues to drive ACK LOW.
At the end of cycle 7, the selected device floats ACK in three-state condition and a new command can begin.
Document #: 38-02041 Rev. *E
Page 102 of 127
CYNSE70064A
SRAM
BHI[2:0]
6
LHO[1]
SSF, SSV
DQ[67:0]
CMDV
CMD[8:0]
BHI[2:0]
3
LHI
CYNSE70064A #0
6
5
5
4
4
3
6 5 4 3
LHI
CYNSE70064A #2
BHI[2:0]
2
1
0
LHO[0]
2
0
6 5 4 3
2
LHI
CYNSE70064A #3
LHO[0]
1
0
6 5 4
3
CYNSE70064A #4
LHI
LHO[0]
1
0
LHO[0]
BHI[2:0]
LHO[1]
BHI[2:0]
BHI[2:0] 3
2 1
LHI
0
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70064A #6
LHO[0]
1
LHI
0
1
LHO[1]
2
1
LHO[0]
CYNSE70064A #1LHI
LHO[1]
BHI[2:0]3
2
0
2
6 5
4
CYNSE70064ALHI
#5
LHO[0]
6
5
4
LHI
CYNSE70064A #7
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 12-2. Table of a Block of Eight Devices
Document #: 38-02041 Rev. *E
Page 103 of 127
CYNSE70064A
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
CLK2X
PHS_L
CMDV
Read
CMD[1:0]
CMD[8:2]
A
B
Address
DQ
OE_L
z
WE_L
z
CE_L
z
z
z
1
z
z
0
ALE_L
z
0
SADR
z
Address
z
0
SSV
z
SSF
z
TLSZ = 01, HLAT = 000, LRAM = 0, LDEV = 0.
z
1
0
DQ driven by selected CYNSE70064A.
Figure 12-3. SRAM Read Through Device Number 0 in a Block of Eight Devices
Document #: 38-02041 Rev. *E
Page 104 of 127
CYNSE70064A
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
CLK2X
PHS_L
CMDV
CMD[1:0]
Read
CMD[8:2]
A
Address
DQ
OE_L
WE_L
B
z
0
1
z
1
CE_L
1
z
1
ALE_L
1
z
z
z
1
SADR
ACK
z
SSV
z
SSF
z
TLSZ = 01, HLAT = 000, LRAM = 1, LDEV = 1.
Figure 12-4. SRAM Read Timing for Device Number 7 in a Block of Eight Devices
12.5
SRAM Read with a Table of up to 31 Devices
The following explains the SRAM Read operation accomplished through a table of up to 31 devices, using the following parameters: TLSZ = 10. The diagram of such a table is shown in Figure 12-5. The following assumes that SRAM access is being
accomplished through CYNSE70064A device number 0, that device number 0 is the selected device. Figure 12-6 and Figure 12-7
show the timing diagrams for device number 0 and device number 30, respectively.
• Cycle 1A: The host ASIC applies the Read instruction to CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. During this cycle, the host ASIC also supplies SADR[21:20] on CMD[8:7].
• Cycle 1B: The host ASIC continues to apply the Read instruction to CMD[1:0] using CMDV = 1. The DQ bus supplies the
address, with DQ[20:19] set to 10, to select the SRAM address.
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[67:0].
• Cycles 5 to 6: The selected device continues to drive DQ[67:0].
• Cycle 7: The selected device continues to drive DQ[67:0] and drives an SRAM Read cycle.
• Cycle 8: The selected device drives ACL from Z to LOW.
• Cycle 9: The selected device drives ACK to HIGH.
• Cycle 10: The selected device drives ACK from HIGH to LOW.
At the end of cycle 10, the selected device floats ACL in a three-state condition.
Document #: 38-02041 Rev. *E
Page 105 of 127
CYNSE70064A
BHI[2]
SSF, SSV
BHI[1]
BHI[0] GND
Block of 8 CYNSE70064As Block 0 (devices 0–7)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
BHI[2]
BHI[1]
BHI[0]
SRAM
GND
Block of 8 CYNSE70064As Block 1 (devices 8–15)
BHO[2]
BHO[1]
BHO[0]
GND
Block of 8 CYNSE70064As Block 2 (devices 16–23)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
Block
of
7
CYNSE70064As
Block
3
(devices
24–30)
DQ[67:0]
BHO[2]
BHO[1]
BHO[0]
CMD[8:0], CMDV
Figure 12-5. Table of 31 Devices Made of Four Blocks
Document #: 38-02041 Rev. *E
Page 106 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Read
00
CMD[1:0]
CMD[8:2]
A B
Address
DQ
OE_L
WE_L
z
z
CE_L
z
ALE_L
z
1
z
z
0
z
0
SADR[21:0]
z
ACK
z
Address
z
0
SSV
z
SSF
z
TLSZ = 10, HLAT = 010, LRAM = 0, LDEV =0
1
0
z
DQ driven by the selected CYNSE70064A
Figure 12-6. SRAM Read Through Device Number 0 in a Bank of 31 Devices
(Device Number 0 Timing)
Document #: 38-02041 Rev. *E
Page 107 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Read
00
CMD[1:0]
CMD[8:2]
A B
Address
DQ
OE_L
WE_L
CE_L
ALE_L
0
1
z
1
1
z
1
1
z
z
1
SADR[21:0]
ACK
z
SSV
0
SSF
0
TLSZ = 10, HLAT = 010, LRAM = 1, LDEV = 1
Figure 12-7. SRAM Read Through Device Number 0 in Bank of 31 Devices
(Device Number 30 Timing)
12.6
SRAM Write with a Table of One Device
SRAM Write enables Write access to the off-chip SRAM that contains associative data. The latency from the second cycle of the
Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction, and will depend
on the TLSZ value parameter programmed in the device configuration register. The following explains the SRAM Write operation
accomplished through a table of only one device with the following parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and
LDEV = 1. Figure 12-8 shows the timing diagram. For the following description the selected device refers to the only device in
the table as it is the only device that will be accessed.
• Cycle 1A: The host ASIC applies the Write instruction on the CMD[1:0], using CMDV = 1. The DQ bus supplies the address
with DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the
DQ[25:21] lines. The host ASIC also supplies SADR[21:20] on CMD[8:7] in this cycle. Note. CMD[2] must be set to 0 for SRAM
Write as burst Writes into the SRAM are not supported.
• Cycle 1B: The host ASIC continues to apply the Write instruction on the CMD[1:0], using CMDV = 1. The DQ bus supplies
the address with DQ[20:19] set to 10 to select the SRAM address. Note that CMD[2] must be set to 0 for SRAM Write as burst
Writes into the SRAM are not supported.
• Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
• Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation, however the Write cycle appears at the
SRAM bus with the same latency as the latency of Search instruction as measured from the second cycle of the Write command.
Document #: 38-02041 Rev. *E
Page 108 of 127
CYNSE70064A
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
CLK2X
PHS_L
CMDV
CMD[1:0]
Write
CMD[8:2]
A
B
Address
DQ
x
x
OE_L
0
WE_L
1
0
CE_L
1
0
1
0
ALE_L
SADR
z
ACK
z
SSV
0
SSF
1
Address
0
TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1.
Figure 12-8. SRAM Write Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1)
12.7
SRAM Write with a Table of up to Eight Devices
The following explains the SRAM Write operation done through a table(s) of up to eight devices with the following parameters
(TLSZ = 01). The diagram of such a table is shown in Figure 12-9. The following assumes that SRAM access is done through
CYNSE70064A device number 0. Figure 12-10 and Figure 12-11 show the timing diagram for device number 0 and device
number 7, respectively.
• Cycle 1A: The host ASIC applies the Write instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the address
with DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the
DQ[25:21] lines. The host ASIC also supplies SADR[21:20] on CMD[8:7] in this cycle. Note. CMD[2] must be set to 0 for SRAM
Write, as burst Writes into the SRAM are not supported.
• Cycle 1B: The host ASIC continues to apply the Write instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the
address with DQ[20:19] set to 10 to select the SRAM address. Note. CMD[2] must be set to 0 for SRAM Write, as burst Writes
into the SRAM are not supported.
• Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
• Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation, but the Write cycle appears at the SRAM
bus with the same latency as that of a Search instruction as measured from the second cycle of the Write command.
Document #: 38-02041 Rev. *E
Page 109 of 127
CYNSE70064A
SRAM
BHI[2:0]
6
LHO[1]
SSF, SSV
DQ[67:0]
CMDV
CMD[8:0]
BHI[2:0]
3
LHI
CYNSE70064A #0
6
5
5
4
4
3
6 5 4 3
LHI
CYNSE70064A #2
BHI[2:0]
2
1
0
LHO[0]
2
0
6 5 4 3
2
LHI
CYNSE70064A #3
LHO[0]
1
0
6 5 4
3
CYNSE70064A #4
LHI
LHO[0]
1
0
LHO[0]
BHI[2:0]
LHO[1]
BHI[2:0]
BHI[2:0] 3
2 1
LHI
0
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70064A #6
LHO[0]
1
LHI
0
1
LHO[1]
2
1
LHO[0]
CYNSE70064A #1LHI
LHO[1]
BHI[2:0]3
2
0
2
6 5
4
CYNSE70064ALHI
#5
LHO[0]
6
5
4
LHI
CYNSE70064A #7
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 12-9. Table of a Block of Eight Devices
Document #: 38-02041 Rev. *E
Page 110 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Write
01
CMD[1:0]
CMD[8:2]
A B
Address
x
DQ
OE_L
WE_L
CE_L
ALE_L
x
z
z
z
0
z
0
z
0
SADR[21:0]
z
ACK
z
SSV
z
SSF
z
Address
z
z
z
z
TLSZ = 01, HLAT = XXX, LRAM = 0, LDEV = 0
Figure 12-10. SRAM Write Through Device Number 0 in a Block of Eight Devices
Document #: 38-02041 Rev. *E
Page 111 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Write
01
CMD[1:0]
CMD[8:2]
A B
Address
x
DQ
OE_L
WE_L
CE_L
x
0
0
1
1
z
1
1
z
1
1
z
1
ALE_L
z
SADR[21:0]
ACK
z
SSV
0
SSF
0
TLSZ = 01, HLAT = XXX, LRAM = 1, LDEV = 1
Figure 12-11. SRAM Write Timing for Device Number 7 in Block of Eight Devices
12.8
SRAM Write with Table(s) of up to 31 Devices
The following explains the SRAM Write operation done through a table(s) of up to 31 devices with the following parameters
(TLSZ = 10). The diagram of such table(s) is shown in Figure 12-12. The following assumes that SRAM access is done through
CYNSE70064A device number 0—device 0 is the selected device. Figure 12-13 and Figure 12-14 show the timing diagram for
device number 0 and device number 30, respectively.
• Cycle 1A: The host ASIC applies the Write instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the address
with DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the
DQ[25:21] lines. The host ASIC also supplies SADR[21:20] on CMD[8:7] in this cycle. Note. CMD[2] must be set to 0 for SRAM
Write, as burst Writes into the SRAM are not supported.
• Cycle 1B: The host ASIC continues to apply the Write instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the
address with DQ[20:19] set to 10 to select the SRAM address. Note. CMD[2] must be set to 0 for SRAM Write, as burst Writes
into the SRAM are not supported.
• Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
• Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation, but the Write cycle appears at the SRAM
bus with the same latency as that of a Search instruction, as measured from the second cycle of the Write command.
Document #: 38-02041 Rev. *E
Page 112 of 127
CYNSE70064A
BHI[2]
BHI[1]
BHI[0]
GND
SRAM
Block of 8 CYNSE70064As Block 0 (devices 0–7)
SSF, SSV
BHO[2]
BHI[2]
BHO[1]
BHI[1]
BHO[0]
BHI[0]
GND
Block of 8 CYNSE70064As Block 1 (devices 8–15)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8 CYNSE70064As Block 2 (devices 16–23)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
Block of 7 CYNSE70064As Block 3 (devices 24–30)
DQ[67:0]
CMD[8:0], CMDV
BHO[2]
BHO[1]
BHO[0]
Figure 12-12. Table of 31 Devices (Four Blocks)
Document #: 38-02041 Rev. *E
Page 113 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Write
01
CMD[1:0]
CMD[8:2]
A B
Address
x
DQ
OE_L
x
z
WE_L
z
CE_L
z
ALE_L
z
SADR[21:0]
z
ACK
z
SSV
z
SSF
z
z
0
0
0
Address
z
z
z
z
TLSZ = 10, HLAT = XXX, LRAM = 0, LDEV = 0
Figure 12-13. SRAM Write Through Device Number 0 in Bank of 31 Devices (Device 0 Timing)
Document #: 38-02041 Rev. *E
Page 114 of 127
CYNSE70064A
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Write
01
CMD[1:0]
CMD[8:2]
A B
Address
x
DQ
OE_L
WE_L
CE_L
ALE_L
x
0
1
z
1
1
z
1
1
z
1
z
SADR[21:0]
ACK
1
z
SSV
0
SSF
0
TLSZ = 10, HLAT = XXX, LRAM = 1, LDEV = 1
Figure 12-14. SRAM Write Through Device Number 0 in Bank of 31 CYNSE70064A Devices
(Device Number 30 Timing)
Document #: 38-02041 Rev. *E
Page 115 of 127
CYNSE70064A
13.0
Power
13.1
Proper Power-up Sequence
The proper power-up sequence is required to correctly initialize the Cypress NSEs before functional access to the device can
begin. RST_L and TRST_L should be held low before the power supplies ramp-up. RST_L must be set low for a duration of time
afterward and then set high. The following steps describe the proper power-up sequence.
1. Set RST_L and TRST_L low.
2. Power up VDD, VDDQ and start running CLK2X and PHS_L. The order in which these signals (including VDD and VDDQ) are
applied is not critical.
3. Hold RST_L low for a minimum of 64 CLK2X cycles. The counting starts on the first rising edge of CLK2X when PHS_L is
high, after both VDD and VDDQ have reached their steady state voltages. Set RST_L high afterward to complete the power-up
sequence. For JTAG reset, TRST_L can be brought high after both VDD and VDDQ have reached their steady state voltages.
Figure 13-1 illustrates the proper sequences of the power-up operation.
VDD
VDDQ
CLK2x
PHS_L
TRST_L
RST_L
64 CLK2x
cycles
Figure 13-1. Power-up Sequence
14.0
Application
Figure 14-1 shows how a Search engine subsystem can be formed using a host ASIC and an CYNSE70064A bank. It also shows
how this Search engine subsystem is integrated in a switch or router. The CYNSE70064A can access synchronous and
asynchronous SRAMs by allowing the host ASIC to set the same HLAT parameter in all search engines within a bank of search
engines.
Document #: 38-02041 Rev. *E
Page 116 of 127
CYNSE70064A
AM k
SR an
B
ch
ar ne
Se ngi
E
m
ra ry
og mo
r
P e
M
Sys
tem
t
os
H SIC
A
Bus
k
or r
w so
et es
N oc
Pr
N et
wor
k
Line
In te
rfac
h
itc ic
Sw abr
F
es
Figure 14-1. Sample Switch/Router Using the CYNSE70064A Device
15.0
JTAG (1149.1) Testing
The CYNSE70064A supports the Test Access Port and Boundary Scan Architecture as specified in the IEEE JTAG standard
number 1149.1. The pin interface to the chip consists of five signals with the standard definitions: TCK, TMS, TDI, TDO, and
TRST_L. Table 15-1 describes the operations that the test access port controller supports, and Table 15-2 describes the TAP
Device ID Register. Note. To disable JTAG functionality, connect the TCK, TMS and TDI pins to VDDQ through a pull-up, and
TRST_L to ground through a pull-down.
Table 15-1. Supported Operations
Instruction
SAMPLE/PRELOAD
Type
Mandatory
EXTEST
Mandatory
BYPASS
Mandatory
IDCODE
Optional
CLAMP
HighZ
Optional
Optional
Description
Sample/Preload. This operation loads the values of signals going to and from I/O
pins into the boundary scan shift register to provide a snapshot of the normal
functional operation, and to initialize boundary scan.
External Test. This operation uses boundary scan values shifted in from TAP to
test connectivity external to the device.
This operation loads a single bit shift register between TDI and TDO and provides
a minimum-length serial path when no test operation is required
This operation selects the Identification register between TDI and TDO and allows
the “idcode” to be read serially through TDO.
This operation drives preset values onto the outputs of devices
This operation leaves the device output pins in a high-impedance state.
Table 15-2. TAP Device ID Register
Field
Range
Initial Value
Description
Revision
[31:28]
0001
Revision Number. This is the current device revision number. Numbers start
from 1 and increment by 1 for each revision of the device.
Part Number
[27:12]
0000 0000 0000 0001
MFID
[11:1]
000_1101_1100
LSB
[0]
1
Document #: 38-02041 Rev. *E
This is the part number for the device.
Manufacturer ID. This field is the same as the manufacturer ID used in the
TAP controller.
Least significant bit.
Page 117 of 127
CYNSE70064A
16.0
Electrical Specifications
This section describes the electrical specifications, capacitance, operating conditions, DC characteristics, and AC timing parameters for the CYNSE70064A, as shown in Table 16-1 and Table 16-2.
Table 16-1. DC Electrical Characteristics for CYNSE70064A
Parameter
Description
Test Conditions
Min.
Max.
Unit
–10
10
µA
ILI
Input leakage current
VDDQ = VDDQ Max., VIN = 0 to VDDQ Max.
ILO
Output leakage current
VDDQ = VDDQ Max., VIN = 0 to VDDQ Max.
–10
10
µA
VIL
Input LOW voltage (VDDQ = 3.3V)
–0.3
0.8
V
VIH
Input HIGH voltage (VDDQ = 3.3V)
2.0
VDDQ + 0.3
V
VOL
Output LOW voltage (VDDQ = 3.3V)
VDDQ = VDDQ Min., IOL = 8 mA
0.4
V
VDDQ = VDDQ Min., IOH = 8 mA
VOH
Output HIGH voltage (VDDQ = 3.3V)
VIL
Input LOW voltage (VDDQ = 2.5V)
–0.3
2.4
0.7
V
V
VIH
Input HIGH voltage (VDDQ = 2.5V)
1.7
VDDQ + 0.3
V
VOL
Output LOW voltage (VDDQ = 2.5V)
0.4
V
VDDQ = VDDQ Min., IOL = 8 mA
VOH
Output HIGH voltage (VDDQ = 2.5V)
VDDQ = VDDQ Min., IOH = 8 mA
IDD2
3.3V supply current at VDD Max.
83-MHz Search rate, lOUT = 0 mA
2.0
270
mA
V
IDD2
3.3V supply current at VDD Max.
66-MHz Search rate, lOUT = 0 mA
200
mA
IDD2
3.3V supply current at VDD Max.
50-MHz Search rate, lOUT = 0 mA
150
mA
IDD2
2.5V supply current at VDD Max.
83-MHz Search rate, lOUT = 0 mA
220
mA
IDD2
2.5V supply current at VDD Max.
66-MHz Search rate, lOUT = 0 mA
160
mA
IDD2
2.5V supply current at VDD Max.
50-MHz Search rate, lOUT = 0 mA
120
mA
IDDl
1.8V supply current at VDD Max.
83-MHz Search rate
3000
mA
IDDl
1.8V supply current at VDD Max.
66-MHz Search rate
2300
mA
IDDl
1.8V supply current at VDD Max.
50-MHz Search rate
1800
mA
Parameter
Description
Max
Unit
CIN
Input capacitance
6
pF[7]
COUT
Output capacitance
6
pF[8]
Table 16-2. Operating Conditions for CYNSE70064A
Parameter
Description
Min (3.3V)
Max (3.3V)
Min (2.5V)
Max (2.5V)
Unit
VDDQ
Operating voltage for IO
3.135
3.465
2.4
2.6
V
VDD
Operating supply voltage
1.7
1.9
1.7
1.9
V
Input HIGH
voltage[9]
2.0
VDDQ + 0.3
1.7
VDDQ + 0.3
V
VIL
Input LOW
voltage[10]
–0.3
0.8
–0.3
0.7
V
tA
Ambient operating temperature
°C
VIH
Supply voltage tolerance
0
70
0
70
–5%
+5%
–5%
+5%
Notes:
7. f = 1 MHz, VIN = 0V.
8. f = 1 MHz, VOUT = 0V.
9. Maximum allowable applies to overshoot only (VDDQ is 2.5V supply).
10. Minimum allowable applies to undershoot only.
Document #: 38-02041 Rev. *E
Page 118 of 127
CYNSE70064A
17.0
AC Timing Waveforms
Table 17-1 shows the AC timing parameters for the CYNSE70064A device; Table 17-2 shows the same parameters but for 2.5V.
Table 17-1. AC Timing Parameters with CLK2X
CYNSE70064A- CYNSE70064A- CYNSE70064A50
66
83
Parameter
fCLOCK
Description
Min.
Max.
CLK2X frequency
Min.
100
Min.
133
Max.
Unit
166
MHz
10
7.5
6.0
ns
tCKHI
CLK2X HIGH
pulse[11]
4.0
3.0
2.4
ns
tCKLO
CLK2X LOW pulse[11]
4.0
3.0
2.4
ns
2.5
2.5
1.8
ns
0.6
0.6
0.6
ns
4.2
4.2
3.5
ns
0.6
0.6
0.6
ns
tCLK
CLK2X period
Max.
[11]
tISCH
Input set-up time to CLK2X rising edge
tIHCH
Input hold time to CLK2X rising edge[11]
[11]
tICSCH
Cascaded input set-up time to CLK2X rising edge
tICHCH
Cascaded input hold time to CLK2X rising edge[11]
tCKHOV
Rising edge of CLK2X to LHO, FULO, BHO, FULL
valid[12]
tCKHDV
Rising edge of CLK2X to DQ valid[12]
tCKHDZ
Rising edge of CLK2X to DQ High-Z[13]
9.5
8.5
10.0
1.2
9.5
[12]
tCKHSV
Rising edge of CLK2X to SRAM bus valid
tCKHSHZ
Rising edge of CLK2X to SRAM bus High-Z[13]
tCKHSLZ
Rising edge of CLK2X to SRAM bus LOW-Z[13]
7.5
9.0
1.2
8.5
1.2
7.0
ns
7.5
ns
7.0
ns
10.0
9.0
7.5
ns
7.0
6.5
6.0
ns
7.0
6.5
ns
Table 17-2. 2.5V AC Table for Test Condition of CYNSE70064A
Conditions
Input pulse levels (VDDQ = 3.3V)
Input pulse levels (VDDQ = 2.5V)
Input rise and fall times measured at 0.3V and 2.7V (VDDQ = 3.3V)
Input rise and fall times measured at 0.25V and 2.25V (VDDQ = 2.5V)
Input timing reference levels (VDDQ = 3.3V)
Input timing reference levels (VDDQ = 2.5V)
Output reference levels (VDDQ = 3.3V)
Output reference levels (VDDQ = 2.5V)
Output load
+2.5 VDDQ = 2.5V/+3.0V VDDQ = 3.3V
90%
Results
GND to 3.0V
GND to 2.5V
≤ 2 ns see (Figure 17-1)
≤ 2 ns see (Figure 17-1)
1.5V
1.25V
1.5V
1.25V
See Figure 17-2 and Figure 17-3
90%
10%
GND
10%
Figure 17-1. Input Waveform for CYNSE70064A
DOUT
AC Load
Z0 = 50Ω
50Ω
VL = 1.25V for VCCIO = 2.5V
VL = 1.5V for VCCIO = 3.3V
C = 30 pF
Figure 17-2. Output Load for CYNSE70064A
Notes:
11. Values are based on 50% signal levels.
12. Based on an AC load of CL = 30 pF (see Figure 17-1, Figure 17-2, and Figure 17-3).
13. These parameters are sampled but not 100% tested, and are based on an AC load of 5 pF.
Document #: 38-02041 Rev. *E
Page 119 of 127
CYNSE70064A
+2.5 V or +3.3V
208Ω (2.5V)
158Ω (3.3V)
Q
5 pF
192Ω (2.5V)
175Ω (3.3V)
For High-Z and VOL/VOH[14,15]
Figure 17-3. 2.5 I/O Output Load Equivalent for CYNSE70064A
Figure 17-4 shows timing waveform diagrams.
cycle
0
cycle
1
cycle
2
cycle cycle
3
4
cycle cycle
5
6
cycle
7
cycle
8
cycle cycle
9
10
cycle
11
cycle
12
CLK2X
CLK
tIHCH
tISCH
Signal
Group 0
tISCH
Signal t
Group 1 ISCH
tIHCH
tIHCH
tICHCH
Signal
Group 2
Signal
Group 3
tIHCH
tICSCH
tCKHOV
tCKHOV
tCKHSHZ
Signal
Group 4
tCKHSV
tCKHDZ
tCKHSLZ
Signal
Group 5
Signal Group 0: PHS_L, RST_L.
Signal Group 1: DQ, CMD, CMDV.
Signal Group 2: LHI, BHI, FULI.
Signal Group 3: LHO, BHO, FULO, FULL.
Signal Group 4: SADR, CE_L, OE_L, WE_L, ALE_L, SSF, SSV.
Signal Group 5: DQ, ACK, EOT.
tCKHDV
Figure 17-4. AC Timing Wave Forms with CLK2X
Notes:
14. Output loading is specified with CL = 5 pF as in Figure 17-3. Transition is measured at ± 200 mV from steady-state voltage.
15. The load used for VOH, VOL testing is shown in Figure 17-3.
Document #: 38-02041 Rev. *E
Page 120 of 127
CYNSE70064A
18.0
Pinout Descriptions and Package Diagrams
In the following figure and table the CYNSE70064A device pinout diagram and pinout descriptions are shown.
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
NC
GND
EOT
NC
NC
VDD
FULI5
FULI4
FULI1
BHO0
VDD
BHI0
LHI6
NC
VDD
ID2
ID0
TDO
NC
NC
1
2
NC
NC
ACK
FULL
NC
FULO1
NC
FULI6
FULI2
BHO1
BHI2
VDDQ
LHI5
LHI3
LHI2
ID3
TMS
TDI
VDD
NC
2
3
DQ64
NC
NC
VDDQ
VDD
VDDQ
NC
NC
VDDQ
BHO2
VDD
LHO1
LHI4
VDDQ
LHIO
ID1
TCK
NC
NC
DQ65
3
4
DQ62
NC
VDD
GND
RSTL
NC
FULO0
GND
FULI3
FULI0
BHI1
LHO0
LHI1
ID4
TRST_L
GND
DQ63
DQ61
DQ57
4
5
DQ60
VDDQ
NC
DQ66
DQ67
DQ59
NC
DQ53
5
6
VDD
NC
DQ56
DQ58
VDDQ
DQ55
DQ49
VDD
6
7
DQ50
VDDQ
DQ52
DQ54
DQ47
VDDQ
DQ51
VDDQ
7
8
NC
DQ46
DQ48
GND
GND
NC
DQ45
DQ43
8
9
DQ40
DQ42
VDDQ
DQ44
DQ41
DQ39
VDD
DQ37
9
10
VDD
NC
DQ36
DQ38
VDDQ
DQ35
DQ33
DQ31
10
GND
TOP
GND
GND
GND
GND
GND
GND
GND
GND
LEFT
RIGHT
11
VDDQ
DQ34
DQ32
DQ30
GND
GND
GND
GND
VDDQ
NC
DQ29
VDD
11
12
NC
DQ28
VDDQ
DQ26
GND
GND
GND
GND
NC
DQ23
DQ25
DQ27
12
13
DQ24
VDD
DQ20
GND
GND
DQ19
VDDQ
DQ21
13
14
DQ22
DQ16
DQ14
VDDQ
VDDQ
NC
DQ15
DQ17
14
15
VDD
DQ18
VDDQ
DQ6
DQ9
DQ11
DQ13
VDD
15
16
NC
DQ12
DQ8
DQ0
DQ1
DQ5
DQ7
NC
16
17
DQ10
NC
VDDQ
GND
NC
CMD4
CMD2
GND
WE_L
CLK2X
VDD
SAD15
GND
VDDQ
SAD5
VDDQ
GND
NC
NC
VDDQ
17
18
DQ2
DQ4
VDD
SSF
CMD6
CMD3
CMD0
ALE_L
OE_L
SAD21
SAD18
SAD16
SAD12
SAD9
SAD7
SAD6
NC
SAD0
VDD
DQ3
18
19
NC
NC
NC
SSV
CMD5
CMD1
CMDV
VDDQ
PHS_L
VDDQ
SAD19
VDDQ
NC
SAD10
SAD11
NC
SAD4
SAD3
NC
NC
19
20
NC
NC
CMD8
CMD7
VDDQ
VDD
NC
CE_L
NC
VDD
SAD20
SAD17
SAD14
SAD13
VDD
SAD8
VDDQ
SAD2
SAD1
NC
20
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
C
B
A
BOTTOM
E
D
Figure 18-1. Pinout Diagram
Document #: 38-02041 Rev. *E
Page 121 of 127
CYNSE70064A
Table 18-1. Pinout Descriptions for Pinout Diagram
Package Ball
Number
Signal Name
Package Ball
Number
Signal Name
Signal Type
A1
A2
NC
C4
DQ63
I/O
NC
C5
DQ59
I/O
A3
DQ65
I/O
C6
DQ55
I/O
A4
DQ57
I/O
C7
VDDQ
3.3V/2.5V
A5
DQ53
I/O
C8
NC
A6
VDD
1.8V
C9
DQ39
I/O
A7
VDDQ
3.3V/2.5V
C10
DQ35
I/O
A8
DQ43
I/O
C11
NC
Signal Type
A9
DQ37
I/O
C12
DQ23
I/O
A10
DQ31
I/O
C13
DQ19
I/O
A11
VDD
1.8V
C14
NC
A12
DQ27
I/O
C15
DQ11
I/O
A13
DQ21
I/O
C16
DQ5
I/O
A14
DQ17
I/O
C17
NC
A15
VDD
1.8V
C18
SAD0
Output-T
A16
NC
C19
SAD3
Output-T
A17
VDDQ
3.3V/2.5V
C20
SAD2
Output-T
A18
DQ3
I/O
D1
ID0
Input
A19
NC
D2
TMS
Input
A20
NC
D3
TCK
Input
B1
NC
B2
VDD
B3
NC
B4
DQ61
D4
GND
Ground
1.8V
D5
DQ67
I/O
D6
VDDQ
3.3V/2.5V
I/O
D7
DQ47
I/O
B5
NC
D8
GND
Ground
B6
DQ49
I/O
D9
DQ41
I/O
B7
DQ51
I/O
D10
VDDQ
3.3V/2.5V
B8
DQ45
I/O
D11
VDDQ
3.3V/2.5V
B9
VDD
1.8V
D12
NC
B10
DQ33
I/O
D13
GND
Ground
B11
DQ29
I/O
D14
VDDQ
3.3V/2.5V
B12
DQ25
I/O
D15
DQ9
I/O
B13
VDDQ
3.3V/2.5V
D16
DQ1
I/O
B14
DQ15
I/O
D17
GND
Ground
B15
DQ13
I/O
D18
NC
B16
DQ7
I/O
D19
SAD4
Output-T
B17
NC
B18
VDD
D20
VDDQ
3.3V/2.5V
1.8V
E1
ID2
Input
E2
ID3
Input
E3
ID1
Input
B19
NC
B20
SAD1
Output-T
C1
TDO
Output-T
E4
TRST_L
Input
C2
TDI
Input
E17
VDDQ
3.3V/2.5V
C3
NC
E18
SAD6
Output-T
Document #: 38-02041 Rev. *E
Page 122 of 127
CYNSE70064A
Table 18-1. Pinout Descriptions for Pinout Diagram (continued)
Package Ball
Number
Signal Name
Package Ball
Number
E19
NC
Signal Name
Signal Type
L2
BHO1
Output
E20
SAD8
F1
VDD
Output-T
L3
BHO2
Output
1.8V
L4
FULI0
Input
F2
LHI2
Input
L17
CLK2X
Input
F3
LHI0
Input
L18
SAD21
Output-T
Signal Type
F4
ID4
Input
L19
VDDQ
3.3V/2.5V
F17
SAD5
Output-T
L20
VDD
1.8V
F18
SAD7
Output-T
M1
FULI1
Input
F19
SAD11
Output-T
M2
FULI2
Input
F20
VDD
1.8V
G1
NC
M3
VDDQ
3.3V/2.5V
M4
FULI3
Input
G2
LHI3
Input
M17
WE_L
Output-T
G3
VDDQ
3.3V/2.5V
M18
OE_L
Output-T
Input
G4
LHI1
Input
M19
PHS_L
G17
VDDQ
3.3V/2.5V
M20
NC
G18
SAD9
Output-T
N1
FULI4
Input
G19
SAD10
Output-T
N2
FULI6
Input
G20
SAD13
Output-T
N3
NC
H1
LHI6
Input
N4
GND
H2
LHI5
Input
N17
GND
Ground
H3
LHI4
Input
N18
ALE_L
Output-T
Ground
H4
GND
Ground
N19
VDDQ
3.3V/2.5V
H17
GND
Ground
N20
CE_L
Output-T
H18
SAD12
Output-T
P1
FULI5
Input
H19
NC
P2
NC
H20
SAD14
Output-T
P3
NC
J1
BHI0
Input
P4
FULO0
J2
VDDQ
3.3V/2.5V
P17
CMD2
Input
J3
LHO1
Output
P18
CMD0
Input
Input
Output
J4
LHO0
Output
P19
CMDV
J17
SAD15
Output-T
P20
NC
J18
SAD16
Output-T
R1
VDD
1.8V
J19
VDDQ
3.3V/2.5V
R2
FULO1
Output
J20
SAD17
Output-T
R3
VDDQ
3.3V/2.5V
K1
VDD
1.8V
R4
NC
K2
BHI2
Input
R17
CMD4
Input
K3
VDD
1.8V
R18
CMD3
Input
K4
BHI1
Input
R19
CMD1
Input
K17
VDD
1.8V
R20
VDD
1.8V
K18
SAD18
Output-T
T1
NC
K19
SAD19
Output-T
T2
NC
K20
SAD20
Output-T
T3
VDD
1.8V
L1
BHO0
Output
T4
RSTL
Input
Document #: 38-02041 Rev. *E
Page 123 of 127
CYNSE70064A
Table 18-1. Pinout Descriptions for Pinout Diagram (continued)
Package Ball
Number
Signal Name
T17
NC
Signal Type
Package Ball
Number
Signal Name
Signal Type
V20
CMD8
Input
Ground
T18
CMD6
Input
W1
GND
T19
CMD5
Input
W2
NC
T20
VDDQ
3.3V/2.5V
W3
NC
U1
NC
W4
NC
U2
FULL
Output
W5
VDDQ
U3
VDDQ
3.3V/2.5V
W6
NC
3.3V/2.5V
U4
GND
Ground
W7
VDDQ
3.3V/2.5V
U5
DQ66
I/O
W8
DQ46
I/O
U6
DQ58
I/O
W9
DQ42
I/O
U7
DQ54
I/O
W10
NC
U8
GND
Ground
W11
DQ34
I/O
U9
DQ44
I/O
W12
DQ28
I/O
U10
DQ38
I/O
W13
VDD
1.8V
U11
DQ30
I/O
W14
DQ16
I/O
U12
DQ26
I/O
W15
DQ18
I/O
U13
GND
Ground
W16
DQ12
I/O
U14
VDDQ
3.3V/2.5V
W17
NC
U15
DQ6
I/O
W18
DQ4
U16
DQ0
I/O
W19
NC
U17
GND
Ground
W20
NC
I/O
U18
SSF
Output-T
Y1
NC
U19
SSV
Output-T
Y2
NC
U20
CMD7
Input
Y3
DQ64
I/O
V1
EOT
Output-T
Y4
DQ62
I/O
V2
ACK
Output-T
Y5
DQ60
I/O
V3
NC
Y6
VDD
1.8V
V4
VDD
Y7
DQ50
I/O
V5
NC
Y8
NC
V6
DQ56
I/O
Y9
DQ40
I/O
V7
DQ52
I/O
Y10
VDD
1.8V
3.3V/2.5V
1.8V
V8
DQ48
I/O
Y11
VDDQ
V9
VDDQ
3.3V/2.5V
Y12
NC
V10
DQ36
I/O
Y13
DQ24
I/O
V11
DQ32
I/O
Y14
DQ22
I/O
V12
VDDQ
3.3V/2.5V
Y15
VDD
1.8V
V13
DQ20
I/O
Y16
NC
V14
DQ14
I/O
Y17
DQ10
I/O
V15
VDDQ
3.3V/2.5V
Y18
DQ2
I/O
V16
DQ8
I/O
Y19
NC
V17
VDDQ
3.3V/2.5V
Y20
NC
V18
VDD
1.8V
V19
NC
Document #: 38-02041 Rev. *E
J9
GND
Ground
J10
GND
Ground
Page 124 of 127
CYNSE70064A
Table 18-1. Pinout Descriptions for Pinout Diagram (continued)
Package Ball
Number
Signal Name
Signal Type
Package Ball
Number
Signal Name
Signal Type
J11
GND
Ground
L10
GND
Ground
J12
GND
Ground
L11
GND
Ground
K9
GND
Ground
L12
GND
Ground
19.0
K10
GND
Ground
M9
GND
Ground
K11
GND
Ground
M10
GND
Ground
K12
GND
Ground
M11
GND
Ground
L9
GND
Ground
M12
GND
Ground
Ordering Information
Table 19-1 provides ordering information.
Table 19-1. Ordering Information
Part Number
Description
Frequency
Temperature Range
CYNSE70064A-50BGC
Search engine
50 MHz
Commercial
CYNSE70064A-66BGC
Search engine
66 MHz
Commercial
CYNSE70064A-83BGC
Search engine
83 MHz
Commercial
Document #: 38-02041 Rev. *E
Page 125 of 127
CYNSE70064A
20.0
Package Diagram
272-lead PBGA (27 x 27 x 2.33 mm) BG272
51-85130-*A
Figure 20-1. Package
Associative Processing Technology is a trademark of Cypress Semiconductor. All product and company names mentioned in this
document are the trademarks of their respective holders.
Document #: 38-02041 Rev. *E
Page 126 of 127
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CYNSE70064A
Document History Page
Document Title: CYNSE70064A Network Search Engine
Document Number: 38-02041
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
111438
02/21/02
AFX
New Data Sheet
*A
116610
07/10/02
OOR
Changed every CYNSE70064 to CYNSE70064A
*B
118153
09/19/02
OOR
Added Power section covering power-up sequence
Updated JTAG section with the Supported Operations table
*C
119282
11/19/02
ED
Added 83-MSPS part information to Overview, DC Electrical Specifications,
AC Timing Parameters
Added note to Power-up Sequence
Removed CYNSE70128/256-specific instructions
Removed alternative method from power-up sequence instructions
*D
123686
02/20/03
KOS
Removed TEST from Signal Description Table 5-1
Added Pin A10 to the pinout descriptions Table 18-1
Added ”Output-T” in the Signal Type field of the Pin E18 Table 18-1
Changed F1 Signal Name and Type from VDDQ to VDD and 3.3V/2.5V to
1.8V Table 18-1
Added “1.8V” in the Signal Type field of Pin F20 Table 18-1
Changed U6 Package Ball Number from U6I/O to U6 Table 18-1
Reordered the pinouts list Table 18-1
*E
126020
05/08/03
ITL
Document #: 38-02041 Rev. *E
Updated Figure 13-1 on page 116 to reselect the correct waveforms.
Corrected the power-up sequence description above the figure.
Page 127 of 127