STMicroelectronics D100NH02L N-channel 24v - 0.0042ohm - 60a - dpak - ipak stripfet tm ii power mosfet Datasheet

STD100NH02L
STD100NH02L-1
N-channel 24V - 0.0042Ω - 60A - DPAK - IPAK
STripFET™ II Power MOSFET
General features
Type
VDSSS
RDS(on)
ID
STD100NH02L
STD100NH02L-1
24V
24V
<0.0048Ω
<0.0048Ω
60A(1)
60A(1)
3
3
2
1
1.
Value limited by wire bonding
■
RDS(on) * Qg industry’s benchmark
■
Conduction losses reduced
■
Switching losses reduced
■
Low threshold device
DPAK
1
IPAK
Internal schematic diagram
Description
This device utilizes the latest advanced design
rules of ST’s proprietary STripFET™ technology.
This is suitable fot the most demanding DC-DC
converter application where high efficiency is to
be achieved.
Applications
■
Switching application
Order codes
Part number
Marking
Package
Packaging
STD100NH02LT4
D100NH02L
DPAK
Tape & reel
STD100NH02L-1
D100NH02L
IPAK
Tube
December 2006
Rev 11
1/16
www.st.com
16
Contents
STD100NH02L
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
Test circuit
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/16
................................................ 8
STD100NH02L
1
Electrical ratings
Electrical ratings
Table 1.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
30
V
Drain-source voltage (VGS = 0)
24
V
Drain-gate voltage (RGS = 20KΩ)
24
V
± 20
V
Vspike (1) Drain-source voltage rating
VDS
VDGR
VGS
Drain-source voltage
ID
(2)
Drain current (continuous) at TC = 25°C
60
A
ID
(2)
Drain current (continuous) at TC=100°C
60
A
Drain current (pulsed)
240
A
Total dissipation at TC = 25°C
100
W
Derating factor
0.67
W/°C
Single pulse avalanche energy
800
mJ
-55 to 175
°C
Value
Unit
IDM
(3)
PTOT
EAS
(4)
Tstg
TJ
Storage temperature
Max. operating junction temperature
1. Garanted when external Rg = 4.7 Ω and tf < tfmax.
2.
Value limited by wire bonding.
3. Pulse width limited by safe operating area
4. Starting TJ = 25 oC, ID = 30A, VDD = 15V
Table 2.
Symbol
Thermal data
Parameter
RthJC
Thermal resistance junction-case Max
1.5
°C/W
RthJA
Thermal resistance junction-ambient Max
100
°C/W
Tl
Maximum lead temperature for soldering
purpose
275
°C
3/16
Electrical characteristics
2
STD100NH02L
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 3.
Symbol
V(BR)DSS
On/off states
Parameter
Drain-source breakdown
voltage
Test conditions
ID = 25mA, VGS = 0
Zero gate voltage drain
current (VGS = 0)
IGSS
Gate body leakage current
(VDS = 0)
VGS = ±20V
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250µA
RDS(on)
Static drain-source on
resistance
VGS = 10V, ID = 30A
Symbol
gfs (1)
Ciss
Coss
Crss
Qg
Qgs
Qgd
Max.
24
V
VDS = 20, TC = 125°C
1
1
10
µA
µA
±100
nA
1.8
V
0.0042 0.0048
0.005 0.009
VGS = 5V, ID = 15A
Unit
Ω
Ω
Dynamic
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Forward transconductance
VDS = 10 V, ID = 30A
50
S
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 15V, f = 1 MHz,
VGS = 0
3940
1020
110
pF
pF
pF
Total gate charge
Gate-source charge
Gate-drain charge
VGS = 10V
62
12
8
VDD = 10V, ID = 30A
84
nC
nC
nC
Qoss(2)
Output charge
VDS = 16V, VGS = 0V
24
nC
Qgls(3)
Third-quadrant gate charge
VDS < 0V, VGS = 10V
56.5
nC
Gate input resistance
f = 1MHz gate DC Bias = 0
Test signal level = 20mV
Open drain
1.1
Ω
RG
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. Qoss = Coss*∆ Vin , Coss = Cgd + Cds . See Chapter Appendix A
3. Gate charge for synchronous operation
4/16
Typ.
VDS = 20
IDSS
Table 4.
Min.
STD100NH02L
Electrical characteristics
Table 5.
Symbol
td(on)
tr
td(off)
tf
Table 6.
Symbol
ISD
ISDM
VSD(1)
trr
Qrr
IRRM
Switching times
Parameter
Max.
Unit
15
200
60
35
47
ns
ns
ns
ns
Typ.
Max
Unit
Source-drain current
60
A
Source-drain current (pulsed)
240
A
1.3
V
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
Min.
VDD = 10V, ID = 30A,
RG = 4.7Ω, VGS = 10V
Figure 13 on page 8
Typ.
Source drain diode
Parameter
Test conditions
Forward on voltage
ISD = 30A, VGS = 0
Reverse recovery time
Reverse recovery charge
Reverse recovery current
di/dt = 100A/µs,
VDD = 15V, TJ = 150°C
ISD = 60A,
Figure 15 on page 8
Min
47
58
2.5
ns
µC
A
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
5/16
Electrical characteristics
STD100NH02L
2.1
Electrical characteristics (curves)
Figure 1.
Safe operating area
Figure 2.
Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
6/16
STD100NH02L
Electrical characteristics
Figure 7.
Gate charge vs gate-source voltage Figure 8.
Figure 9.
Normalized gate threshold voltage
vs temperature
Figure 11. Source-drain diode forward
characteristics
Capacitance variations
Figure 10. Normalized on resistance vs
temperature
Figure 12. Normalized breakdown voltage vs
temperature
7/16
Test circuit
3
STD100NH02L
Test circuit
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
Figure 15. Test circuit for inductive load
Figure 16. Unclamped Inductive load test
switching and diode recovery times
circuit
Figure 17. Unclamped inductive waveform
8/16
STD100NH02L
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
9/16
Package mechanical data
STD100NH02L
TO-251 (IPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
MAX.
MIN.
A
2.2
TYP.
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A3
0.7
1.3
0.027
0.051
B
0.64
0.9
0.025
0.031
B2
5.2
5.4
0.204
0.212
B3
TYP.
MAX.
0.85
B5
0.033
0.3
0.012
B6
0.95
C
0.45
C2
0.48
D
6
E
6.4
6.6
0.037
0.6
0.017
0.023
0.6
0.019
0.023
6.2
0.236
0.244
0.252
0.260
G
4.4
4.6
0.173
0.181
H
15.9
16.3
0.626
0.641
L
9
9.4
0.354
0.370
L1
0.8
1.2
0.031
0.047
L2
0.8
1
0.031
0.039
A1
C2
A3
A
C
H
B
B6
=
1
=
2
G
=
=
=
E
B2
=
3
B5
L
D
B3
L2
L1
0068771-E
10/16
STD100NH02L
Package mechanical data
DPAK MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
A1
A2
B
b4
C
C2
D
D1
E
E1
e
e1
H
L
(L1)
L2
L4
R
V2
TYP
2.2
0.9
0.03
0.64
5.2
0.45
0.48
6
MAX.
MIN.
2.4
1.1
0.23
0.9
5.4
0.6
0.6
6.2
0.086
0.035
0.001
0.025
0.204
0.017
0.019
0.236
6.6
0.252
5.1
6.4
0.260
0.173
0.368
0.039
2.8
0.8
0.181
0.397
0.110
0.031
1
0.023
0.2
0°
0.094
0.043
0.009
0.035
0.212
0.023
0.023
0.244
0.185
0.090
4.6
10.1
0.6
MAX.
0.200
4.7
2.28
4.4
9.35
1
TYP.
0.039
0.008
8°
0°
8°
0068772-F
11/16
Packaging mechanical data
5
STD100NH02L
Packaging mechanical data
DPAK FOOTPRINT
All dimensions are in millimeters
TAPE AND REEL SHIPMENT
REEL MECHANICAL DATA
DIM.
mm
MIN.
A
B
DIM.
mm
MIN.
MAX.
A0
6.8
7
0.267 0.275
B0
10.4
10.6
0.409 0.417
B1
12/16
inch
MIN.
MAX.
12.1
0.476
1.6
0.059 0.063
D
1.5
D1
1.5
E
1.65
1.85
F
7.4
7.6
0.291 0.299
K0
2.55
2.75
0.100 0.108
P0
3.9
4.1
0.153 0.161
P1
7.9
8.1
0.311 0.319
P2
1.9
2.1
0.075 0.082
R
40
W
15.7
0.059
0.065 0.073
1.574
16.3
0.618
0.641
MAX.
MIN.
330
1.5
C
12.8
D
20.2
G
16.4
N
50
T
TAPE MECHANICAL DATA
inch
MAX.
12.992
0.059
13.2
0.504 0.520
18.4
0.645 0.724
0.795
1.968
22.4
0.881
BASE QTY
BULK QTY
2500
2500
STD100NH02L
Buck converter - power losses estimation
Appendix A
Buck converter - power losses estimation
Figure 18. Buck converter: power losses estimation
The power losses associated with the FETs in a synchronous buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.
●
The low side (SW2) device requires:
●
Very low RDS(on) to reduce conduction losses
●
Small Qgls to reduce the gate charge losses
●
Small Coss to reduce losses due to output capacitance
●
Small Qrr to reduce losses on SW1 during its turn-on
●
The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source
●
voltage to avoid the cross conduction phenomenon;
●
The high side (SW1) device requires:
●
Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on
the gate
●
Small Qg to have a faster commutation and to reduce gate charge losses
●
Low RDS(on) to reduce the conduction losses.
13/16
Buck converter - power losses estimation
Table 7.
STD100NH02L
Power losses calculation
High side switching (SW1)
Low side switch (SW2)
R DS(on)SW1 * I 2L * δ
R DS(on)SW2 * I 2L * (1 − δ )
Pconduction
Vin * (Q gsth(SW1) + Q gd(SW1) ) * f *
Pswitching
Recovery
IL
Ig
Zero Voltage Switching
(1)
Not applicable
Vin * Q rr(SW2) * f
Conductio
n
Not applicable
Vf(SW2) * I L * t deadtime * f
Pgate(QG)
Q g(SW1) * Vgg * f
Q gls(SW2) * Vgg * f
PQoss
Vin * Q oss(SW1) * f
Vin * Q oss(SW2) * f
2
2
Pdiode
1. Dissipated by SW1 during turn-on
Table 8.
Paramiters meaning
Parameter
d
Duty-cycle
Qgsth
Post threshold gate charge
Qgls
Third quadrant gate charge
Pconduction
Pswitching
14/16
Meaning
On state losses
On-off transition losses
Pdiode
Conduction and reverse recovery diode losses
Pgate
Gate drive losses
PQoss
Output capacitance losses
STD100NH02L
6
Revision history
Revision history
Table 9.
Revision history
Date
Revision
Changes
09-Sep-2004
9
Complete version
08-Aug-2006
10
The document has been reformatted, updated SOA Figure 1.
18-Dev-2006
11
Typo mistake on Table 3.
15/16
STD100NH02L
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