TI1 DAC6311IDCKRG4 12-bit, low-power, single-channel digital-to-analog converters in sc70 package Datasheet

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DAC5311, DAC6311, DAC7311
SBAS442C – AUGUST 2008 – REVISED JULY 2015
DACx311 2-V to 5.5-V, 80-µA, 8-, 10-, and 12-Bit, Low-Power, Single-Channel,
Digital-to-Analog Converters in SC70 Package
1 Features
3 Description
•
The DAC5311 (8-bit), DAC6311 (10-bit), and
DAC7311 (12-bit) devices are low-power, singlechannel, voltage output digital-to-analog converters
(DACs). The low power consumption of these devices
in normal operation (0.55 mW at 5 V, reducing to 2.5
μW in power-down mode) makes it ideally suited for
portable, battery-operated applications.
1
•
•
•
•
•
•
•
•
•
•
Relative Accuracy:
– 0.25 LSB INL (DAC5311: 8-Bit)
– 0.5 LSB INL (DAC6311: 10-Bit)
– 1 LSB INL (DAC7311: 12-Bit)
microPower Operation: 80 μA at 2.0 V
Power-Down: 0.5 μA at 5 V, 0.1 μA at 2.0 V
Wide Power Supply: 2.0 V to 5.5 V
Power-On Reset to Zero Scale
Straight Binary Data Format
Low Power Serial Interface With SchmittTriggered Inputs: up to 50 MHz
On-Chip Output Buffer Amplifier, Rail-to-Rail
Operation
SYNC Interrupt Facility
Extended Temperature Range –40°C to +125°C
Pin-Compatible Family in a Tiny, 6-Pin SC70
Package
2 Applications
•
•
•
•
Portable, Battery-Powered instruments
Process Controls
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
All devices use an external power supply as a
reference voltage to set the output range. The
devices incorporate a power-on reset (POR) circuit
that ensures the DAC output powers up at 0 V and
remains there until a valid write to the device occurs.
The DAC5311, DAC6311, and DAC7311 contain a
power-down feature, accessed over the serial
interface, that reduces current consumption of the
device to 0.1 μA at 2.0 V in power-down mode.
These devices are pin-compatible with the DAC8311
and DAC8411, offering an easy upgrade path from
8-, 10-, and 12-bit resolution to 14- and 16-bit. All
devices are available in a small, 6-pin, SC70 (SOT)
package. This package offers a flexible, pin- and
function-compatible, drop-in solution within the family
over an extended temperature range of –40°C to
+125°C.
Simplified Schematic
AVDD
These devices are monotonic by design, provide
excellent linearity, and minimize undesired code-tocode transient voltages while offering an easy
upgrade path within a pin-compatible family. All
devices use a versatile, three-wire serial interface that
operates at clock rates of up to 50 MHz and is
compatible with standard SPI™, QSPI™, Microwire,
and digital signal processor (DSP) interfaces.
GND
Power-On
Reset
Device Information(1)
PART NUMBER
REF(+)
DAC
Register
8-/10-/12-Bit
DAC
Output
Buffer
VOUT
DACx311
PACKAGE
SC70 (6)
BODY SIZE (NOM)
2.00 mm × 1.25 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Input Control
Logic
SYNC SCLK
Power-Down
Control Logic
Resistor
Network
DIN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC5311, DAC6311, DAC7311
SBAS442C – AUGUST 2008 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 22
8.1 Overview ................................................................. 22
8.2 Functional Block Diagram ....................................... 22
8.3 Feature Description................................................. 22
8.4 Device Functional Modes........................................ 24
8.5 Programming........................................................... 25
9
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Applications ............................................... 27
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 31
12 Device and Documentation Support ................. 32
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2013) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Added Device Comparison section and moved existing tables to this new section............................................................... 3
•
Moved Operating Temperature parameter from Electrical Characteristics table to Recommended Operating
Conditions table ..................................................................................................................................................................... 4
•
Deleted Parameter Definitions section; definitions moved to new Glossary section............................................................ 32
Changes from Revision A (August 2011) to Revision B
Page
•
Changed all 1.8 V to 2.0 V throughout data sheet ................................................................................................................. 1
•
Deleted the 1.8-V Typical Characteristics section.................................................................................................................. 8
•
Changed X-axis for Figure 36............................................................................................................................................... 12
•
Changed X-axis for Figure 37............................................................................................................................................... 12
Changes from Original (August, 2008) to Revision A
Page
•
Changed specifications and test conditions for input low voltage parameter......................................................................... 6
•
Changed specifications and test conditions for input high voltage parameter ....................................................................... 6
2
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SBAS442C – AUGUST 2008 – REVISED JULY 2015
5 Device Comparison
Table 1. Related Devices
RELATED DEVICES
16-BIT
14-BIT
12-BIT
10-BIT
8-BIT
Pin and Function Compatible
DAC8411
DAC8311
DAC7311
DAC6311
DAC5311
Table 2. Relative Accuracy and Differential Nonlinearity
DEVICE
MAXIMUM
RELATIVE
ACCURACY
(LSB)
MAXIMUM
DIFFERENTIAL
NONLINEARITY
(LSB)
DAC5311
±0.25
±0.25
DAC6311
±0.5
±0.5
DAC7311
±1
±1
6 Pin Configuration and Functions
DCK Package
6-Pin SC70
Top View
SYNC
1
6
VOUT
SCLK
2
5
GND
DIN
3
4
AVDD/VREF
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
AVDD/VREF
4
I
Power supply input, +2.0 V to +5.5 V.
DIN
3
I
Serial Data Input. Data are clocked into the 16-bit input shift register on the falling edge of the
serial clock input.
GND
5
—
SCLK
2
I
Serial clock input. Data are transferred at rates up to 50MHz.
Ground reference point for all circuitry on the part.
SYNC
1
I
Level-triggered control input (active low). This is the frame sychronization signal for the input data.
When SYNC goes low, it enables the input shift register and data are transferred in on the falling
edges of the following clocks. The DAC is updated following 16th clock cycle, unless SYNC is
taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the
write sequence is ignored by the DACx311. See the SYNC Interrupt section for more details.
VOUT
6
O
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Voltage
MIN
MAX
UNIT
AVDD to GND
–0.3
+6
V
Digital input voltage to GND
–0.3
+AVDD + 0.3
V
VOUT to GND
–0.3
+AVDD + 0.3
V
150
°C
150
°C
Junction, TJ max
Temperature
(1)
(1)
Storage, Tstg
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TA
Operating temperature
AVDD
Supply voltage
MAX
UNIT
–40
NOM
125
°C
2
5.5
V
7.4 Thermal Information
DACx311
THERMAL METRIC (1)
DCK (SC70)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
216.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
52.1
°C/W
RθJB
Junction-to-board thermal resistance
65.9
°C/W
ψJT
Junction-to-top characterization parameter
1.3
°C/W
ψJB
Junction-to-board characterization parameter
65.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBAS442C – AUGUST 2008 – REVISED JULY 2015
7.5 Electrical Characteristics
at AVDD = 2.0 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER
STATIC PERFORMANCE
TEST CONDITIONS
DAC5311
DAC6311
Resolution
DAC7311
DAC5311
DAC6311
MIN
Relative accuracy
DAC7311
MAX
UNIT
8
Bits
10
Bits
12
Bits
Measured by the line passing through
codes 3 and 252
±0.01
±0.25
LSB
Measured by the line passing through
codes 12 and 1012
±0.06
±0.5
LSB
Measured by the line passing through
codes 30 and 4050
±0.3
±1
LSB
±0.01
±0.25
LSB
±0.03
±0.5
LSB
±0.2
±1
LSB
±0.05
±4
mV
DAC5311
DAC6311
TYP
(1)
Differential
nonlinearity
DAC7311
Offset error
Measured by the line passing through two
codes (2)
Offset error drift
Zero code error
Full-scale error
All ones loaded to DAC register
Gain error
Gain temperature coefficient
μV/°C
3
All zeros loaded to the DAC register
0.2
mV
0.04
0.2
% of
FSR
0.05
±0.15
% of
FSR
AVDD = 5 V
±0.5
AVDD = 2.0 V
±1.5
ppm of
FSR/°C
OUTPUT CHARACTERISTICS
Output voltage range
Output voltage settling time (3)
0
RL = 2 kΩ, CL = 200 pF, AVDD = 5 V,
1/4 scale to 3/4 scale
RL = 2 MΩ, CL = 470 pF
Slew rate
Capacitive load stability
Code change glitch impulse
RL = ∞
RL = 2 kΩ
1 LSB change around major carry
Power-up time
(1)
(2)
(3)
10
μs
12
μs
0.7
V/μs
470
pF
1000
pF
nV-s
0.5
nV-s
17
mV
0.5
Ω
AVDD = 5 V
50
mA
AVDD = 3 V
20
mA
Coming out of power-down mode
50
μs
RL = 2 kΩ, CL = 200 pF, AVDD = 5 V
DC output impedance
Short circuit current
V
0.5
Digital feedthrough
Power-on glitch impulse
6
AVDD
Linearity calculated using a reduced code range of 3 to 252 for 8-bit, 12 to 1012 for 10bit, and 30 to 4050 for 12-bit, output unloaded.
Straight line passing through codes 3 and 252 for 8-bit, 12 and 1012 for 10-bit, and 30 and 4050 for 12-bit, output unloaded.
Specified by design and characterization, not production tested.
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Electrical Characteristics (continued)
at AVDD = 2.0 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SNR
81
dB
–65
dB
65
dB
65
dB
TA= +25°C, at zero-scale input,
fOUT = 1 kHz, AVDD = 5 V
17
nV/√Hz
TA= +25°C, at mid-code input,
fOUT = 1 kHz, AVDD = 5 V
110
nV/√Hz
TA= +25°C, at mid-code input,
0.1 Hz to 10 Hz, AVDD = 5 V
3
TA= +25°C, BW = 20 kHz, 12-bit level,
AVDD = 5 V,
fOUT = 1 kHz, 1st 19 harmonics removed for
SNR calculation
THD
SFDR
SINAD
DAC output noise density (4)
DAC output noise (5)
μVPP
LOGIC INPUTS (6)
Input current
AVDD = 2.7 V to 5.5 V
VINL, Input low voltage
AVDD = 2.0 V to 2.7 V
VINH, Input high voltage
±1
μA
0.3 × AVDD
V
0.1 × AVDD
V
AVDD = 2.7 V to 5.5 V
0.7 × AVDD
V
AVDD = 2.0 V to 2.7 V
0.9 × AVDD
V
Pin capacitance
1.5
3
pF
5.5
V
AVDD = 3.6 V to 5.5 V
110
160
μA
AVDD = 2.7 V to 3.6 V
95
150
μA
AVDD = 2.0 V to 2.7 V
80
140
μA
AVDD = 3.6 V to 5.5 V
0.5
3.5
μA
AVDD = 2.7 V to 3.6 V
0.4
3
μA
AVDD = 2.0 V to 2.7 V
0.1
2
μA
AVDD = 3.6 V to 5.5 V
0.55
0.88
mW
AVDD = 2.7 V to 3.6 V
0.25
0.54
mW
AVDD = 2.0 V to 2.7 V
0.14
0.38
mW
AVDD = 3.6 V to 5.5 V
2.50
19.2
µW
AVDD = 2.7 V to 3.6 V
1.08
10.8
µW
AVDD = 2.0 V to 2.7 V
0.72
8.1
µW
POWER REQUIREMENTS
AVDD
2.0
VINH = AVDD and
VINL = GND, at
midscale code (7)
Normal mode
IDD
All power-down mode
VINH = AVDD and
VINL = GND, at
midscale code (7)
VINH = AVDD and
VINL = GND, at
midscale code (7)
Normal mode
Power dissipation
All power-down mode
(4)
(5)
(6)
(7)
6
VINH = AVDD and
VINL = GND, at
midscale code (7)
For more details, see Figure 23.
For more details, see Figure 24.
Specified by design and characterization, not production tested.
For more details, see Figure 16 and Figure 58.
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7.6 Timing Requirements
at –40°C to 125°C, and AVDD = 2 V to 5.5 V (unless otherwise noted) (1)
MIN
f(SCLK)
Serial clock frequency
t1
SCLK cycle time
t2
SCLK high time
t3
SCLK low time
t4
SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7
SCLK falling edge to SYNC rising edge
t8
Minimum SYNC high time
t9
16th SCLK falling edge to SYNC falling edge
t10
SYNC rising edge to 16th SCLK falling edge
(for successful SYNC interrupt)
(1)
NOM MAX
AVDD = 2.0 V to 3.6 V
20
AVDD = 3.6 V to 5.5 V
50
AVDD = 2.0 V to 3.6 V
50
AVDD = 3.6 V to 5.5 V
20
AVDD = 2.0 V to 3.6 V
25
AVDD = 3.6 V to 5.5 V
10
AVDD = 2.0 V to 3.6 V
25
AVDD = 3.6 V to 5.5 V
10
AVDD = 2.0 V to 3.6 V
0
AVDD = 3.6 V to 5.5 V
0
AVDD = 2.0 V to 3.6 V
5
AVDD = 3.6 V to 5.5 V
5
AVDD = 2.0 V to 3.6 V
4.5
AVDD = 3.6 V to 5.5 V
4.5
AVDD = 2.0 V to 3.6 V
0
AVDD = 3.6 V to 5.5 V
0
AVDD = 2.0 V to 3.6 V
50
AVDD = 3.6 V to 5.5 V
20
AVDD = 2.0 V to 3.6 V
100
AVDD = 3.6 V to 5.5 V
100
AVDD = 2.0 V to 3.6 V
15
AVDD = 3.6 V to 5.5 V
15
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH) / 2.
t9
t1
SCLK
1
16
t8
t3
t4
t2
t7
SYNC
t10
t6
t5
DIN
DB15
DB0
DB15
Figure 1. Serial Write Operation
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7.7 Typical Characteristics
7.7.1 Typical Characteristics: AVDD = 5 V
at TA = 25°C, AVDD = 5 V, and DAC loaded with midscale code (unless otherwise noted)
0.10
AVDD = 5V
LE (LSB)
0.25
0
-0.50
-0.10
0.2
0.06
0
-0.1
-0.2
512
1024
1536
2048
2560
3072
3584
4096
0
128
256
384
512
640
768
896
1024
Digital Input Code
Figure 2. DAC7311 12-Bit Linearity Error and Differential
Linearity Error vs Code (–40°C)
Figure 3. DAC6311 10-Bit Linearity Error and Differential
Linearity Error vs Code (–40°C)
LE (LSB)
0
0
-0.05
-0.50
-0.10
0.2
0.06
0.1
0
-0.1
AVDD = 5V
0.05
-0.25
DLE (LSB)
LE (LSB)
DLE (LSB)
0.10
AVDD = 5V
0.25
-0.2
0.03
0
-0.03
-0.06
0
512
1024
1536
2048
2560
3072
3584
4096
0
128
256
384
512
640
768
896
1024
Digital Input Code
Digital Input Code
Figure 4. DAC7311 12-Bit Linearity Error and Differential
Linearity Error vs Code (25°C)
Figure 5. DAC6311 10-Bit Linearity Error and Differential
Linearity Error vs Code (25°C)
0.50
0.10
AVDD = 5V
LE (LSB)
0.25
0
0
-0.05
-0.50
-0.10
0.2
0.06
0.1
0
-0.1
-0.2
AVDD = 5V
0.05
-0.25
DLE (LSB)
LE (LSB)
0
-0.03
Digital Input Code
0.50
DLE (LSB)
0.03
-0.06
0
0.03
0
-0.03
-0.06
0
8
0
-0.05
0.1
AVDD = 5V
0.05
-0.25
DLE (LSB)
DLE (LSB)
LE (LSB)
0.50
512
1024
1536
2048
2560
3072
3584
4096
0
128
256
384
512
640
768
896
1024
Digital Input Code
Digital Input Code
Figure 6. DAC7311 12-Bit Linearity Error and Differential
Linearity Error vs Code (125°C)
Figure 7. DAC6311 10-Bit Linearity Error and Differential
Linearity Error vs Code (125°C)
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Typical Characteristics: AVDD = 5 V (continued)
at TA = 25°C, AVDD = 5 V, and DAC loaded with midscale code (unless otherwise noted)
0.4
AVDD = 5V
0.01
AVDD = 5V
0
Zero-Code Error (mV)
LE (LSB)
0.02
-0.01
-0.02
DLE (LSB)
0.02
0.01
0
0.3
0.2
0.1
-0.01
0
-40 -25 -10
-0.02
0
32
64
96
128
160
192
224
256
5
Digital Input Code
110 125
0
Offset Error (mV)
LE (LSB)
95
AVDD = 5V
0.02
DLE (LSB)
80
0.4
-0.02
0.01
0.2
0
-0.2
0
-0.4
-0.01
-0.6
-40 -25 -10
-0.02
0
32
64
96
128
160
192
224
256
5
Digital Input Code
0.02
35
50
65
80
95
110 125
Figure 11. Offset Error vs Temperature
0.06
AVDD = 5V
0.01
20
Temperature (°C)
Figure 10. DAC5311 8-Bit Linearity Error and Differential
Linearity Error vs Code (25°C)
AVDD = 5V
0.04
0
Full-Scale Error (mV)
LE (LSB)
65
0.6
-0.01
-0.01
-0.02
0.02
DLE (LSB)
50
Figure 9. Zero-Code Error vs Temperature
AVDD = 5V
0.01
35
Temperature (°C)
Figure 8. DAC5311 8-Bit Linearity Error and Differential
Linearity Error vs Code (–40°C)
0.02
20
0.01
0
0.02
0
-0.02
-0.04
-0.01
-0.02
0
32
64
96
128
160
192
224
256
-0.06
-40 -25 -10
Digital Input Code
Figure 12. DAC5311 8-Bit Linearity Error and Differential
Linearity Error vs Code (125°C)
5
20
35
50
65
80
95
110 125
Temperature (°C)
Figure 13. Full-Scale Error vs Temperature
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Typical Characteristics: AVDD = 5 V (continued)
at TA = 25°C, AVDD = 5 V, and DAC loaded with midscale code (unless otherwise noted)
0.6
AVDD = 5V
DAC Loaded with 000h
5.0
Analog Output Voltage (V)
Analog Output Voltage (V)
5.5
4.5
4.0
3.5
3.0
AVDD = 5V
DAC Loaded with FFFh
2.5
0
2
0.4
0.2
0
4
6
8
10
0
2
4
ISOURCE (mA)
Figure 14. Source Current at Positive Rail
SYNC Input (all other digital inputs = GND)
Power-Supply Current (mA)
Power-Supply Current (mA)
10
2000
AVDD = 5.5V
100
80
1500
Sweep from
0V to 5.5V
1000
Sweep from
5.5V to 0V
500
0
60
0
512
1024
1536
2048
2560
3072
3584
0
4096
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VLOGIC (V)
Digital Input Code
Figure 17. Power-Supply Current vs Logic Input Voltage
Figure 16. Power-Supply Current vs Digital Input Code
140
1.6
AVDD = 5V
AVDD = 5V
Quiescent Current (mA)
Power-Supply Current (mA)
8
Figure 15. Sink Current at Negative Rail
120
130
120
110
100
-40 -25 -10
5
20
35
50
65
80
95
110 125
1.2
0.8
0.4
0
-40 -25 -10
5
Temperature (°C)
Figure 18. Power-Supply Current vs Temperature
10
6
ISINK (mA)
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20
35
50
65
80
95
110 125
Temperature (°C)
Figure 19. Power-Down Current vs Temperature
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Typical Characteristics: AVDD = 5 V (continued)
at TA = 25°C, AVDD = 5 V, and DAC loaded with midscale code (unless otherwise noted)
102
-20
AVDD = 5V, fS = 225kSPS,
-1dB FSR Digital Input,
Measurement Bandwidth = 20kHz
94
THD
SNR (dB)
THD (dB)
-40
AVDD = 5V, fS = 225kSPS,
-1dB FSR Digital Input,
Measurement Bandwidth = 20kHz
-60
86
2nd Harmonic
78
-80
3rd Harmonic
70
-100
0
1
2
3
4
5
0
1
2
fOUT (kHz)
Figure 20. Total Harmonic Distortion vs Output Frequency
4
5
Figure 21. Signal-to-Noise Ratio vs Output Frequency
0
300
AVDD = 5V,
fOUT = 1kHz, fS = 225kSPS,
Measurement Bandwidth = 20kHz
20
AVDD = 5V
250
Noise (nV/ÖHz)
-40
Gain (dB)
3
fOUT (kHz)
-60
-80
200
150
Midscale
100
-100
Zero Scale
Full Scale
50
-120
0
-140
0
5
10
15
20
10
100
Frequency (kHz)
1k
10k
100k
Frequency (Hz)
Figure 22. Power Spectral Density
Figure 23. DAC Output Noise Density vs Frequency
VNOISE (1mV/div)
VOUT (500mV/div)
AVDD = 5V,
DAC = Midscale, No Load
3mVPP
AVDD = 5V
Clock Feedthrough Impulse ~0.5nV-s
Time (2s/div)
Time (500ns/div)
Figure 24. DAC Output Noise, 0.1-Hz to 10-Hz Bandwidth
Figure 25. Clock Feedthrough, 5-V, 2-MHz, Midscale
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Typical Characteristics: AVDD = 5 V (continued)
at TA = 25°C, AVDD = 5 V, and DAC loaded with midscale code (unless otherwise noted)
Glitch Impulse
< 0.5nV-s
Clock
Feedthrough
~0.5nV-s
VOUT (500mV/div)
VOUT (500mV/div)
AVDD = 5V
From Code: 800h
To Code: 801h
AVDD = 5V
From Code: 801h
To Code: 800h
Clock
Feedthrough
~0.5nV-s
Glitch Impulse
< 0.5nV-s
Time (5ms/div)
Time (5ms/div)
Figure 26. Glitch Energy, 5-V, 12-Bit, 1-LSB Step, Rising
Edge
Figure 27. Glitch Energy, 5-V, 12-Bit, 1-LSB Step, Falling
Edge
VOUT (5mV/div)
VOUT (5mV/div)
Glitch Impulse
~1nV-s
AVDD = 5V
From Code: 80h
To Code: 81h
Clock
Feedthrough
~0.5nV-s
AVDD = 5V
From Code: 81h
To Code: 80h
Glitch Impulse
~1nV-s
Clock
Feedthrough
~0.5nV-s
Time (5ms/div)
Time (5ms/div)
Figure 28. Glitch Energy, 5-V, 8-Bit, 1-LSB Step, Rising
Edge
Figure 29. Glitch Energy, 5-V, 8-Bit, 1-LSB Step, Falling
Edge
AVDD = 5V
From Code: 000h
To Code: FFFh
AVDD = 5V
From Code: FFFh
To Code: 000h
Rising Edge
1V/div
Zoomed Rising Edge
100mV/div
Falling Edge
1V/div
Trigger Pulse 5V/div
Trigger Pulse 5V/div
Time (2ms/div)
Time (2ms/div)
Figure 30. Full-Scale Settling Time, 5-V Rising Edge
12
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Zoomed Falling Edge
100mV/div
Figure 31. Full-Scale Settling Time, 5-V Falling Edge
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Typical Characteristics: AVDD = 5 V (continued)
at TA = 25°C, AVDD = 5 V, and DAC loaded with midscale code (unless otherwise noted)
AVDD = 5V
From Code: C00h
To Code: 400h
Falling
Edge
1V/div
Rising
Edge
1V/div
Zoomed Falling Edge
100mV/div
Zoomed Rising Edge
100mV/div
AVDD = 5V
From Code: 400h
To Code: C00h
Trigger
Pulse
5V/div
Trigger
Pulse
5V/div
Time (2ms/div)
Time (2ms/div)
Figure 33. Half-Scale Settling Time 5-V Falling Edge
AVDD (2V/div)
AVDD = 5V
DAC = Zero Scale
Load = 200pF || 10kW
17mV
AVDD = 5V
DAC = Zero Scale
Load = 200pF || 10kW
VOUT (20mV/div)
VOUT (20mV/div)
AVDD (2V/div)
Figure 32. Half-Scale Settling Time, 5-V Rising Edge
Time (5ms/div)
Time (10ms/div)
Figure 34. Power-On Reset to 0-V Power-On Glitch
Figure 35. Power-Off Glitch
120
0.4
AVDD = 2.0V to 5.5V
110
Quiescent Current (mA)
Power-Supply Current (mA)
AVDD = 2.0V to 5.5V
100
90
80
70
0.3
0.2
0.1
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
AVDD (V)
AVDD (V)
Figure 36. Power-Supply Current vs Power-Supply Voltage
Figure 37. Power-Down Current vs Power-Supply Voltage
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Typical Characteristics: AVDD = 5 V (continued)
at TA = 25°C, AVDD = 5 V, and DAC loaded with midscale code (unless otherwise noted)
50
45
AVDD = 5.5V
40
Occurrences
35
30
25
20
15
10
5
136
140
128
132
120
124
112
116
104
108
96
100
88
92
80
84
0
IDD (mA)
Figure 38. Power-Supply Current Histogram
14
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7.7.2 Typical Characteristics: AVDD = 3.6 V
at TA = 25°C, AVDD = 3.6 V, and DAC loaded with midscale code (unless otherwise noted)
1.2
1200
SYNC Input (all other digital inputs = GND)
Power-Supply Current (mA)
Quiescent Current (mA)
AVDD = 3.6V
0.8
0.4
0
-40 -25 -10
900
Sweep from
0V to 3.6V
600
300
Sweep from
3.6V to 0V
0
5
20
35
50
65
80
95
110 125
0
0.5
1.0
1.5
Temperature (°C)
Figure 39. Power-Down Current vs Temperature
50
45
Analog Output Voltage (V)
35
30
25
20
15
10
5
3.5
4.0
126
3.5
3.3
3.1
2.9
2.7
AVDD = 3.6V
DAC Loaded with FFFFh
2.5
130
118
122
110
114
102
106
94
98
86
90
78
82
0
70
3.0
3.7
AVDD = 3.6V
74
2.5
Figure 40. Power-Supply Current vs Logic Input Voltage
40
Occurrences
2.0
VLOGIC (V)
0
2
4
IDD (mA)
6
8
10
ISOURCE (mA)
Figure 41. Power-Supply Current Histogram
Figure 42. Source Current at Positive Rail
0.6
Analog Output Voltage (V)
AVDD = 3.6V
DAC Loaded with 0000h
0.4
0.2
0
0
2
4
6
8
10
ISINK (mA)
Figure 43. Sink Current at Negative Rail
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7.7.3 Typical Characteristics: AVDD = 2.7 V
at TA = 25°C, AVDD = 2.7 V, and DAC loaded with midscale code (unless otherwise noted)
0.10
AVDD = 2.7V
LE (LSB)
0.25
0
-0.50
-0.10
0.2
0.06
0
-0.1
-0.2
1024
1536
2048
2560
3072
3584
4096
0
128
256
384
512
640
768
896
1024
Digital Input Code
Figure 44. DAC7311 12-Bit Linearity Error and Differential
Linearity Error vs Code (–40°C)
Figure 45. DAC6311 10-Bit Linearity Error and Differential
Linearity Error vs Code (–40°C)
0.10
AVDD = 2.7V
LE (LSB)
0.25
0
0
-0.05
-0.50
-0.10
0.2
0.06
0.1
0
-0.1
AVDD = 2.7V
0.05
-0.25
DLE (LSB)
LE (LSB)
DLE (LSB)
512
-0.2
0.03
0
-0.03
-0.06
0
512
1024
1536
2048
2560
3072
3584
4096
0
128
256
384
512
640
768
896
1024
Digital Input Code
Digital Input Code
Figure 46. DAC7311 12-Bit Linearity Error and Differential
Linearity Error vs Code (25°C)
Figure 47. DAC6311 10-Bit Linearity Error and Differential
Linearity Error vs Code (25°C)
0.50
0.10
AVDD = 2.7V
LE (LSB)
0.25
0
0
-0.05
-0.50
-0.10
0.2
0.06
0.1
0
-0.1
-0.2
AVDD = 2.7V
0.05
-0.25
DLE (LSB)
LE (LSB)
0
-0.03
Digital Input Code
0.50
DLE (LSB)
0.03
-0.06
0
0.03
0
-0.03
-0.06
0
16
0
-0.05
0.1
AVDD = 2.7V
0.05
-0.25
DLE (LSB)
DLE (LSB)
LE (LSB)
0.50
512
1024
1536
2048
2560
3072
3584
4096
0
128
256
384
512
640
768
896
1024
Digital Input Code
Digital Input Code
Figure 48. DAC7311 12-Bit Linearity Error and Differential
Linearity Error vs Code (125°C)
Figure 49. DAC6311 10-Bit Linearity Error and Differential
Linearity Error vs Code (125°C)
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SBAS442C – AUGUST 2008 – REVISED JULY 2015
Typical Characteristics: AVDD = 2.7 V (continued)
at TA = 25°C, AVDD = 2.7 V, and DAC loaded with midscale code (unless otherwise noted)
0.4
AVDD = 2.7V
0.01
AVDD = 2.7V
0
Zero-Code Error (mV)
LE (LSB)
0.02
-0.01
-0.02
DLE (LSB)
0.02
0.01
0
0.3
0.2
0.1
-0.01
0
-40 -25 -10
-0.02
0
32
64
96
128
160
192
224
256
5
Digital Input Code
110 125
0
Offset Error (mV)
LE (LSB)
95
AVDD = 2.7V
0.02
DLE (LSB)
80
0.4
-0.02
0.01
0.2
0
-0.2
0
-0.4
-0.01
-0.6
-40 -25 -10
-0.02
0
32
64
96
128
160
192
224
256
5
Digital Input Code
0.02
35
50
65
80
95
110 125
Figure 53. Offset Error vs Temperature
0.06
AVDD = 2.7V
0.01
20
Temperature (°C)
Figure 52. DAC5311 8-Bit Linearity Error and Differential
Linearity Error vs Code (25°C)
AVDD = 2.7V
0.04
0
Full-Scale Error (mV)
LE (LSB)
65
0.6
-0.01
-0.01
-0.02
0.02
DLE (LSB)
50
Figure 51. Zero-Code Error vs Temperature
AVDD = 2.7V
0.01
35
Temperature (°C)
Figure 50. DAC5311 8-Bit Linearity Error and Differential
Linearity Error vs Code (–40°C)
0.02
20
0.01
0
0.02
0
-0.02
-0.04
-0.01
-0.02
0
32
64
96
128
160
192
224
256
-0.06
-40 -25 -10
Digital Input Code
Figure 54. DAC5311 8-Bit Linearity Error and Differential
Linearity Error vs Code (125°C)
5
20
35
50
65
80
95
110 125
Temperature (°C)
Figure 55. Full-Scale Error vs Temperature
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Typical Characteristics: AVDD = 2.7 V (continued)
at TA = 25°C, AVDD = 2.7 V, and DAC loaded with midscale code (unless otherwise noted)
2.8
0.6
Analog Output Voltage (V)
Analog Output Voltage (V)
AVDD = 2.7V
DAC Loaded with 000h
2.6
2.4
2.2
AVDD = 2.7V
DAC Loaded with FFFh
2.0
0
2
0.4
0.2
0
4
6
8
10
0
2
4
ISOURCE (mA)
Figure 56. Source Current at Positive Rail
SYNC Input (all other digital inputs = GND)
Power-Supply Current (mA)
Power-Supply Current (mA)
10
800
AVDD = 2.7V
90
80
70
60
50
600
Sweep from
0V to 2.7V
400
Sweep from
2.7V to 0V
200
0
0
512
1024
1536
2048
2560
3072
3584
4096
0
0.5
1.0
Digital Input Code
1.5
2.0
2.5
3.0
VLOGIC (V)
Figure 58. Power-Supply Current vs Digital Input Code
Figure 59. Power-Supply Current vs Logic Input Voltage
120
1.0
AVDD = 2.7V
AVDD = 2.7V
110
Quiescent Current (mA)
Power-Supply Current (mA)
8
Figure 57. Sink Current at Negative Rail
100
100
90
80
70
-40 -25 -10
5
20
35
50
65
80
95
110 125
0.8
0.6
0.4
0.2
0
-40 -25 -10
5
Temperature (°C)
Figure 60. Power-Supply Current vs Temperature
18
6
ISINK (mA)
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20
35
50
65
80
95
110 125
Temperature (°C)
Figure 61. Power-Down Current vs Temperature
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Typical Characteristics: AVDD = 2.7 V (continued)
at TA = 25°C, AVDD = 2.7 V, and DAC loaded with midscale code (unless otherwise noted)
94
-20
AVDD = 2.7V, fS = 225kSPS,
-1dB FSR Digital Input,
Measurement Bandwidth = 20kHz
AVDD = 2.7V, fS = 225kSPS,
-1dB FSR Digital Input,
Measurement Bandwidth = 20kHz
90
THD
-40
SNR (dB)
THD (dB)
86
-60
82
78
2nd Harmonic
-80
74
3rd Harmonic
70
-100
0
1
2
3
4
5
0
1
2
fOUT (kHz)
Figure 62. Total Harmonic Distortion vs Output Frequency
50
AVDD
DD = 2.7V,
fOUT
OUT = 1kHz, fS
S = 225kSPS,
Measurement Bandwidth = 20kHz
45
5
AVDD = 2.7V
40
35
Occurrences
-40
Gain (dB)
4
Figure 63. Signal-to-Noise Ratio vs Output Frequency
0
20
3
fOUT (kHz)
-60
-80
30
25
20
15
-100
10
5
-120
104
96
100
92
Figure 65. Power-Supply Current Histogram
Figure 64. Power Spectral Density
VOUT (200mV/div)
AVDD = 2.7V
Clock Feedthrough Impulse ~0.4nV-s
88
IDD (mA)
Frequency (kHz)
VOUT (500mV/div)
84
20
76
15
80
10
72
5
68
0
64
60
0
-140
Glitch Impulse
< 0.3nV-s
AVDD = 2.7V
From Code: 800h
To Code: 801h
Clock
Feedthrough
~0.4nV-s
Time (5ms/div)
Time (5ms/div)
Figure 66. Clock Feedthrough 2.7-V, 20-MHz, Midscale
Figure 67. Glitch Energy, 2.7-V, 12-Bit, 1-LSB Step, Rising
Edge
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Typical Characteristics: AVDD = 2.7 V (continued)
AVDD = 2.7V
From Code: 801h
To Code: 800h
Clock
Feedthrough
~0.4nV-s
VOUT (2mV/div)
VOUT (200mV/div)
at TA = 25°C, AVDD = 2.7 V, and DAC loaded with midscale code (unless otherwise noted)
Glitch Impulse
~1nV-s
Clock
Feedthrough
~0.4nV-s
AVDD = 2.7V
From Code: 80h
To Code: 81h
Glitch Impulse
< 0.3nV-s
Time (5ms/div)
Time (5ms/div)
VOUT (2mV/div)
Figure 68. Glitch Energy, 2.7-V, 12-Bit, 1-LSB Step, Falling
Edge
AVDD = 2.7V
From Code: 81h
To Code: 80h
Figure 69. Glitch Energy, 2.7-V, 8-Bit, 1-LSB Step, Rising
Edge
AVDD = 2.7V
From Code: 000h
To Code: FFFh
Rising Edge
1V/div
Zoomed Rising Edge
100mV/div
Clock
Feedthrough
~0.4nV-s
Glitch Impulse
~1nV-s
Trigger
Pulse
2.7V/div
Time (5ms/div)
Time (2ms/div)
Figure 70. Glitch Energy, 2.7-V, 8-Bit, 1-LSB Step, Falling
Edge
Figure 71. Full-Scale Settling Time, 2.7-V Rising Edge
AVDD = 2.7V
From Code: 400h
To Code: C00h
AVDD = 2.7V
From Code: FFFh
To Code: 000h
Falling Edge
1V/div
Zoomed Falling Edge
100mV/div
Rising
Edge
1V/div
Zoomed Rising Edge
100mV/div
Trigger
Pulse
2.7V/div
Trigger Pulse 2.7V/div
Time (2ms/div)
Time (2ms/div)
Figure 72. Full-Scale Settling Time, 2.7-V Falling Edge
20
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Figure 73. Half-Scale Settling Time, 2.7-V Rising Edge
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Typical Characteristics: AVDD = 2.7 V (continued)
at TA = 25°C, AVDD = 2.7 V, and DAC loaded with midscale code (unless otherwise noted)
AVDD (1V/div)
AVDD = 2.7V
From Code: C00h
To Code: 400h
Trigger
Pulse
2.7V/div
17mV
VOUT (20mV/div)
Falling
Edge
1V/div
Zoomed Falling Edge
100mV/div
AVDD = 2.7V
DAC = Zero Scale
Load = 200pF || 10kW
Time (5ms/div)
Time (2ms/div)
Figure 75. Power-On Reset to 0-V Power-On Glitch
AVDD = 2.7V
DAC = Zero Scale
Load = 200pF || 10kW
VOUT (20mV/div)
AVDD (1V/div)
Figure 74. Half-Scale Settling Time, 2.7-V Falling Edge
Time (10ms/div)
Figure 76. Power-Off Glitch
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8 Detailed Description
8.1 Overview
The DAC5311 (8-bit), DAC6311 (10-bit), and DAC7311 (12-bit) are low-power, single-channel, voltage output
DACs. These devices are monotonic by design, provide excellent linearity, and minimize undesired code-to-code
transient voltages while offering an easy upgrade path within a pin-compatible family. All devices use a versatile,
three-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with standard SPI,
QSPI, Microwire, and digital signal processor (DSP) interfaces.
8.2 Functional Block Diagram
AVDD
GND
Power-On
Reset
REF(+)
DAC
Register
Input Control
Logic
SYNC SCLK
Output
Buffer
8-/10-/12-Bit
DAC
Power-Down
Control Logic
VOUT
Resistor
Network
DIN
8.3 Feature Description
8.3.1 DAC Section
The DAC5311, DAC6311, and DAC7311 are fabricated using Texas Instruments' proprietary HPA07 process
technology. The architecture consists of a string DAC followed by an output buffer amplifier. Because there is no
reference input pin, the power supply (AVDD) acts as the reference. Figure 77 shows a block diagram of the DAC
architecture.
AVDD
REF (+)
DAC Register
Resistor String
VOUT
Output
Amplifier
GND
Figure 77. DACx311 Architecture
The input coding to the DACx311 is straight binary, so the ideal output voltage is given by:
VOUT = AVDD ´
D
2n
where
•
•
22
n = resolution in bits; either 8 (DAC5311), 10 (DAC6311), or 12 (DAC7311).
D = decimal equivalent of the binary code that is loaded to the DAC register. It ranges from 0 to 255 for 8-bit
DAC5311; from 0 to 1023 for the 10-bit DAC6311; and 0 to 4095 for the 12-bit DAC7311.
(1)
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Feature Description (continued)
8.3.2 Resistor String
The resistor string section is shown in Figure 78. It is simply a string of resistors, each of value R. The code
loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the
output amplifier by closing one of the switches connecting the string to the amplifier. The resistor string
architecture is inherently monotonic.
VREF
RDIVIDER
VREF
2
R
R
To Output
Amplifier
R
R
Figure 78. Resistor String
8.3.3 Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range
of 0 V to AVDD. The output amplifier is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The
source and sink capabilities of the output amplifier can be seen in the Typical Characteristics section for the
given voltage input. The slew rate is 0.7 V/μs with a half-scale settling time of typically 6 μs with the output
unloaded.
8.3.4 Power-On Reset
The DACx311 contains a power-on reset circuit that controls the output voltage during power up. On power up,
the DAC register is filled with zeros and the output voltage is 0 V. The DAC register remains that way until a valid
write sequence is made to the DAC. This design is useful in applications where it is important to know the state
of the output of the DAC while it is in the process of powering up.
The occurring power-on glitch impulse is only a few millivolts (typically, 17 mV; see Figure 34).
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8.4 Device Functional Modes
8.4.1 Power-Down Modes
The DACx311 contains four separate modes of operation. These modes are programmable by setting two bits
(PD1 and PD0) in the control register. Table 3 shows how the state of the bits corresponds to the mode of
operation of the device.
Table 3. Modes of Operation for the DACx311
PD1
PD0
OPERATING MODE
NORMAL MODE
0
0
Normal Operation
0
1
Output 1 kΩ to GND
1
0
Output 100 kΩ to GND
1
1
High-Z
POWER-DOWN MODES
When both bits are set to 0, the device works normally with a standard power consumption of typically 80 μA at 2
V. However, for the three power-down modes, the typical supply current falls to 0.5 μA at 5 V, 0.4 μA at 3 V, and
0.1 μA at 2 V. Not only does the supply current fall, but the output stage is also internally switched from the
output of the amplifier to a resistor network of known values. The advantage of this architecture is that the output
impedance of the part is known while the part is in power-down mode. There are three different options: the
output is connected internally to GND either through a 1-kΩ resistor or a 100-kΩ resistor, or is left open-circuited
(High-Z). Figure 79 illustrates the output stage.
Amplifier
Resistor
String DAC
VOUT
Power-down
Circuitry
Resistor
Network
Figure 79. Output Stage During Power-Down
All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit power-down is typically 50 μs for AVDD = 5 V and
AVDD = 3 V.
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8.5 Programming
8.5.1 Serial Interface
The DACx311 has a 3-wire serial interface (SYNC, SCLK, and DIN) compatible with SPI, QSPI, and Microwire
interface standards, as well as most DSPs. See Figure 1 for an example of a typical write sequence.
8.5.1.1 Input Shift Register
The input shift register is 16 bits wide, as shown in Figure 80. The first two bits (PD0 and PD1) are reserved
control bits that set the desired mode of operation (normal mode or any one of three power-down modes) as
indicated in Table 3.
The remaining data bits are either 12 (DAC7311), 10 (DAC6311), or 8 (DAC5311) data bits, followed by don't
care bits, as shown in Figure 80, Figure 81, and Figure 82, respectively.
Figure 80. DAC5311 8-Bit Data Input Register
DB15
PD1
DB14
PD0
D7
D6
D5
D4
D3
D2
D1
DB6
D0
DB5
X
X
X
X
X
DB0
X
DB3
X
X
X
DB0
X
D1
DB2
D0
DB1
X
DB0
X
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 81. DAC6311 10-Bit Data Input Register
DB15
PD1
DB14
PD0
D9
D8
D7
D6
D5
D4
D3
D2
D1
DB4
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 82. DAC7311 12-Bit Data Input Register
DB15
PD1
DB14
PD0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 16-bit shift
register on each falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making
the DACx311 compatible with high-speed DSPs. On the 16th falling edge of the serial clock, the last data bit is
clocked in and the programmed function is executed.
At this point, the SYNC line may be kept low or brought high. In either case, it must be brought high for a
minimum of 20 ns before the next write sequence so that a falling edge of SYNC can initiate the next write
sequence.
8.5.1.2 SYNC Interrupt
In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is
updated on the 16th falling edge. However, bringing SYNC high before the 16th falling edge acts as an interrupt
to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of
the DAC register contents nor a change in the operating mode occurs, as shown in Figure 83.
CLK
SYNC
DIN
DB15
DB0
Invalid Write Sequence:
SYNC HIGH before 16th Falling Edge
DB15
DB0
Valid Write Sequence:
Output Updates on 16th Falling Edge
Figure 83. DACx311 SYNC Interrupt Facility
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Microprocessor Interfacing
9.1.1.1 DACx311 to 8051 Interface
Figure 84 shows a serial interface between the DACx311 and a typical 8051-type microcontroller. The setup for
the interface is as follows: TXD of the 8051 drives SCLK of the DACx311, while RXD drives the serial data line of
the part. The SYNC signal is derived from a bit programmable pin on the port. In this case, port line P3.3 is used.
When data are to be transmitted to the DACx311, P3.3 is taken low. The 8051 transmits data only in 8-bit bytes;
thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 remains low after
the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The 8051 outputs the serial data in a format which has the
LSB first. The DACx311 requires its data with the MSB as the first bit received. Therefore, the 8051 transmit
routine must take this requirement into account, and mirror the data as needed.
80C51/80L51(1)
DACx311(1)
P3.3
SYNC
TXD
SCLK
RXD
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 84. DACx311 to 80C51/80l51 Interfaces
9.1.1.2 DACx311 to Microwire Interface
Figure 85 shows an interface between the DACx311 and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and are clocked into the DACx311 on the rising edge of the SK
signal.
Microwire
DACx311(1)
CS
SYNC
SK
SCLK
SO
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 85. DACx311 to Microwire Interface
9.1.1.3 DACx311 to 68HC11 Interface
Figure 86 shows a serial interface between the DACx311 and the 68HC11 microcontroller. SCK of the 68HC11
drives the SCLK of the DACx311, while the MOSI output drives the serial data line of the DAC. The SYNC signal
is derived from a port line (PC7), similar to what was done for the 8051.
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Application Information (continued)
DACx311(1)
68HC11(1)
PC7
SYNC
SCK
SCLK
MOSI
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 86. DACx311 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. This configuration causes
data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to
the DAC, the SYNC line is taken low (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. Data are transmitted MSB first. In order to load data to
the DACx311, PC7 is held low after the first eight bits are transferred, and a second serial write operation is
performed to the DAC; PC7 is taken high at the end of this procedure.
9.2 Typical Applications
9.2.1 Loop Powered Transmitter
The described loop powered transmitter can accurately source currents from 4 mA to 20 mA.
VREG
Regulator
V+
R5 122.15 kΩ
VREG/VREF
R2
+
30.542 kΩ
Q1
U1
OPA317
R6 60.4 Ω
4.32 kΩ R3
R4 26.7 Ω
Return
Figure 87. Loop Powered Transmitter Schematic
9.2.1.1 Design Requirements
The transmitter has only two external input terminals; a supply connection and a ground (or return) connection.
The transmitter communicates back to the host, typically a PLC analog input module, by precisely controlling the
magnitude of the return current. In order to conform to the 4-mA to 20-mA communication standards, the
complete transmitter must consume less than 4 mA of current.
The complete design of this circuit is outlined in TIPD158, Low Cost Loop-Powered 4-20mA Transmitter
EMC/EMI Tested Reference Design. The design is expected to be low-cost and deliver immunity to the
IEC61000-4 suite of tests with minimum impact on the accuracy of the system. Reference design TIPD158
includes the design goals, simulated results, and measured performance.
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
Amplifier U1 uses negative feedback to make sure that the potentials at the inverting (V–) and noninverting (V+)
input terminals are equal. In this configuration, V– is directly tied to the local GND; therefore, the potential at the
noninverting input terminal is driven to local ground. Thus, the voltage difference across R2 is the DAC output
voltage (VOUT), and the voltage difference across R5 is the regulator voltage (VREG). These voltage differences
cause currents to flow through R2 and R5, as illustrated in Figure 88.
VREG
Regulator
VREG/R2
VREG/VREF
DAC
V+
R5
V+
R2
VOUT
+
Q1
U1
0A
VDAC/R1
V–
iloop
R6
iq
i1
R3 R4
i2
iout
Return
Figure 88. Voltage to Current Conversion
The currents from R2 and R5 sum into i1 (defined in Equation 2), and i1 flows through R3.
VDAC VREG
R2
R5
i1
(2)
Amplifier U2 drives the base of Q1, the NPN bipolar junction transistor (BJT), to allow current to flow through R4
so that the voltage drops across R3 and R4 remain equal. This design keeps the inverting and noninverting
terminals at the same potential. A small part of the current through R4 is sourced by the quiescent current of all
of the components used in the transmitter design (regulator, amplifier, and DAC). The voltage drops across R3
and R4 are equal; therefore, different-sized resistors cause different current flow through each resistor. Use these
different-sized resistors to apply gain to the current flow through R4 by controlling the ratio of resistor R3 to R4, as
shown in Equation 3:
V i1 ˜ R3
9± L2 ˜ 5 4 Ÿ L2
9 9±
i1 ˜ R3
R4
(3)
The current gain in the circuit helps allow a majority of the output current to come directly from the loop through
Q1 instead of from the voltage-to-current converter. This current gain, in addition to the low-power components,
keeps the current consumption of the voltage-to-current converter low. Currents i1 and i2 sum to form output
current iout, as shown in Equation 4:
iout
i1 i2
VDAC VREG R3
R2
R5
R4
§V
·
V
˜ ¨ DAC REG ¸
R5 ¹
© R2
§ VDAC VREG · §
R3 ·
¨
¸ ˜ ¨1 ¸
R5 ¹ ©
R4 ¹
© R2
(4)
The complete transfer function, arranged as a function of input code, is shown in Equation 5. The remaining
sections divide this circuit into blocks for simplified discussion.
iout Code
28
§ VREG ˜ Code
· §
V
R ·
REG ¸ ˜ ¨ 1 3 ¸
¨¨ Resolution
¸
R5 ¹ ©
R4 ¹
˜ R2
©2
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Typical Applications (continued)
Resistor R6 is included to reduce the gain of transistor Q1, and therefore, reduce the closed-loop gain of the
voltage-to-current converter for a stable design. Size resistors R2, R3, R4, and R5 based on the full-scale range of
the DAC, regulator voltage, and the desired current output range of the design.
9.2.1.3 Application Curves
Figure 89 shows the measured transfer function of the circuit. Figure 90 shows the total unadjusted error (TUE)
of the circuit, staying below 0.15 %FSR.
0.20
20
Output Current TUE (%FSR)
0.15
Output Current (mA)
16
12
8
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
4
0
1024
2048
3072
0
4096
1024
2048
3072
4096
DAC Code
DAC Code
Figure 89. Output Current vs Code
Figure 90. Current Total Unadjusted Error vs Code
9.2.2 Using the REF5050 as a Power Supply for the DACx311
As a result of the extremely low supply current required by the DACx311, an alternative option is to use a
REF5050 5-V precision voltage reference to supply the required voltage to the part, as shown in Figure 91. This
option is especially useful if the power supply is too noisy or if the system supply voltages are at some value
other than 5 V. The REF5050 outputs a steady supply voltage for the DACx311. If the REF5050 is used, the
current needed to supply DACx311 is typically 110 μA at 5 V, with no load on the output of the DAC. When the
DAC output is loaded, the REF5050 also needs to supply the current to the load. The total current required (with
a 5 kΩ load on the DAC output) is:
110 μA + (5 V / 5 kΩ) = 1.11 mA
The load regulation of the REF5050 is typically 0.002%/mA, which results in an error of 90 μV for the 1.1 mA
current drawn from it. This value corresponds to a 0.07 LSB error at 12 bits (DAC7311).
+5.5V
+5V
REF5050
1mF
Three-Wire
Serial
Interface
110mA
SYNC
SCLK
VOUT = 0V to 5V
DACx311
DIN
Figure 91. REF5050 as Power Supply to DACx311
For other power-supply voltages, alternative references such as the REF3030 (3 V), REF3033 (3.3 V), or
REF3220 (2.048 V) are recommended. For a full list of available voltage references from TI, see the TI web site
at www.ti.com.
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Typical Applications (continued)
9.2.3 Bipolar Operation Using the DACx311
The DACx311 has been designed for single-supply operation but a bipolar output range is also possible using
the circuit in Figure 92. The circuit shown gives an output voltage range of ±5 V. Rail-to-rail operation at the
amplifier output is achievable using an OPA211, OPA340, or OPA703 as the output amplifier. For a full list of
available operational amplifiers from TI, see the TI web site at www.ti.com
The output voltage for any input code can be calculated as follows:
é
æ R2 ö ù
æ D ö æ R + R2 ö
VO = ê AVDD ´ ç n ÷ ´ ç 1
÷ - AVDD ´ ç
÷ú
è 2 ø è R1 ø
êë
è R1 ø úû
where
•
•
n = resolution in bits; either 8 (DAC5311), 10 (DAC6311), or 12 (DAC7311).
D = decimal equivalent of the binary code that is loaded to the DAC register. It ranges from 0 to 255 for 8-bit
DAC5311; from 0 to 1023 for the 10-bit DAC6311; and 0 to 4095 for the 12-bit DAC7311.
(6)
With AVDD = 5 V, R1 = R2 = 10 kΩ:
ǒ
Ǔ
V O + 10 n D *5V
2
(7)
The resulting output voltage range is ±5 V. Code 000h corresponds to a –5-V output and FFFh (12-bit level)
corresponding to a +5-V output.
R2
10kW
+5V
+5.5V
R1
10kW
OPA211
VOUT
AVDD
10mF
±5V
DACx311
- 5.5V
0.1mF
Three-Wire
Serial
Interface
Figure 92. Bipolar Operation With the DACx311
10 Power Supply Recommendations
The DACx311 is designed to operate with a unipolar analog power supply ranging from 2.0 V to 5.5 V on the
AVDD pin. The AVDD pin supplies power to the digital and analog circuits (including the resistor string) inside the
DAC. The current consumption of this pin is specified in the Electrical Characteristics table. Use a 1 μF to 10 μF
capacitor in parallel with a 0.1 μF bypass capacitor on this pin to remove high-frequency noise.
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11 Layout
11.1 Layout Guidelines
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The DACx311 offers single-supply operation; it is often used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more digital logic present in the design and the higher the
switching speed, the more difficult it is to achieve good performance from the converter.
Because of the single ground pin of the DACx311, all return currents, including digital and analog return currents,
must flow through the GND pin. Ideally, GND is connected directly to an analog ground plane. This plane should
be separate from the ground connection for the digital components until they are connected at the power entry
point of the system.
The power applied to AVDD should be well-regulated and low-noise. Switching power supplies and dc/dc
converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes as the internal logic switches state. This noise can easily
couple into the DAC output voltage through various paths between the power connections and analog output.
This condition is particularly true for the DACx311, as the power supply is also the reference voltage for the DAC.
As with the GND connection, AVDD should be connected to a 5 V power supply plane or trace that is separate
from the connection for digital logic until they are connected at the power entry point. In addition, 1-μF to 10-μF
and 0.1-μF bypass capacitors are strongly recommended. In some situations, additional bypassing may be
required, such as a 100 μF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all
designed to essentially low-pass filter the 5-V supply, removing high-frequency noise.
11.2 Layout Example
U1
Analog IO
Bypass
Capacitors
Digital IO
Figure 93. Recommended Layout
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DAC5311
Click here
Click here
Click here
Click here
Click here
DAC6311
Click here
Click here
Click here
Click here
Click here
DAC7311
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
SPI, QSPI are trademarks of Motorola, Inc.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC5311IDCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D53
DAC5311IDCKRG4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D53
DAC5311IDCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D53
DAC5311IDCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D53
DAC6311IDCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D63
DAC6311IDCKRG4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D63
DAC6311IDCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D63
DAC6311IDCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D63
DAC7311IDCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D73
DAC7311IDCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D73
DAC7311IDCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D73
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Apr-2015
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC5311 :
• Automotive: DAC5311-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Apr-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DAC5311IDCKR
SC70
DCK
6
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
DAC5311IDCKT
SC70
DCK
6
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
DAC6311IDCKR
SC70
DCK
6
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
DAC6311IDCKT
SC70
DCK
6
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
DAC7311IDCKR
SC70
DCK
6
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
DAC7311IDCKT
SC70
DCK
6
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Apr-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC5311IDCKR
SC70
DCK
6
3000
180.0
180.0
18.0
DAC5311IDCKT
SC70
DCK
6
250
180.0
180.0
18.0
DAC6311IDCKR
SC70
DCK
6
3000
180.0
180.0
18.0
DAC6311IDCKT
SC70
DCK
6
250
180.0
180.0
18.0
DAC7311IDCKR
SC70
DCK
6
3000
180.0
180.0
18.0
DAC7311IDCKT
SC70
DCK
6
250
180.0
180.0
18.0
Pack Materials-Page 2
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