TI DAC8881

 DA
DAC8881
C8
88
1
SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
16-Bit, Single-Channel, Low-Noise, Voltage-Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
1
•
•
•
•
•
2345
•
•
•
•
•
•
•
Relative Accuracy: ±0.5 LSB
16-Bit Monotonic Over Temperature Range
Low-Noise: 24nV/√Hz
Fast Settling: 5μs
On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
Wide, Single Power Supply: +2.7V to +5.5V
DAC Loading Control
Selectable Power-On Reset to Zero-Scale or
Midscale
Power-Down Mode
Unipolar Straight Binary or
2's Complement Input Mode
Fast SPI™ Interface with Schmitt-Triggered
Inputs:
Up To 50MHz, 1.8V/3V/5V Logic
Small Package: QFN-24, 4x4mm
The DAC8881 is a 16-bit, single-channel,
voltage-output digital-to-analog converter (DAC) that
offers low-power operation and a flexible SPI serial
interface. It also features 16-bit monotonicity,
excellent linearity, and fast settling time. The on-chip
precision output amplifier allows rail-to-rail output
swing to be achieved over the full supply range of
2.7V to 5.5V.
The device supports a standard SPI serial interface
capable of operating with input data clock frequencies
up to 50MHz. The DAC8881 requires an external
reference voltage to set the output range of the DAC
channel. A programmable power-on reset circuit is
also incorporated into the device to ensure that the
DAC output powers up at zero-scale or midscale, and
remains there until a valid write command.
Additionally, the device has the capability to function
in either unipolar straight binary or 2's complement
mode. The DAC8881 provides a power-down feature,
accessed over the PDN pin, that reduces the current
consumption to 25μA at 5V. Power consumption is
6mW at 5V, reducing to 125μW in power-down mode.
APPLICATIONS
•
•
•
•
•
Industrial Process Control
Data Acquisition Systems
Automatic Test Equipment
Communications
Optical Networking
DVDD
The DAC8881 is available in a 4x4mm QFN-24
package with a specified operating temperature range
of –40°C to +105°C.
DGND
IOVDD
AGND
AVDD
VREFH-S VREFH-F
DAC8881
RST
Power-On
Reset
RSTSEL
Control
Logic
USB/BTC
Resistor
Network
SDI
CS
SCLK
SPI Interface
Shift Register
GAIN
PDN
Input
Register
DAC
Latch
VOUT
DAC
RFB(1)
RFB
SDOSEL
SDO
Serial Out
Control
NOTE: (1) RFB = 5kW for gain = 1,
RFB = 10kW for gain = 2.
LDAC
VREFL-S
VREFL-F
1
2
3
4
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DSP is a trademark of Texas Instruments.
SPI, QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
DAC8881
www.ti.com
SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
DAC8881
QFN-24
RGE
–40°C to +105°C
DAC8881
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
DAC8881
UNIT
AVDD to AGND
–0.3 to 6
V
DVDD to DGND
–0.3 to 6
V
IOVDD to DGND
–0.3 to 6
V
Digital input voltage to DGND
–0.3 to IOVDD + 0.3
V
VOUT to AGND
–0.3 to AVDD + 0.3
V
Operating temperature range
–40 to +105
°C
Storage temperature range
–65 to +150
°C
+150
°C
Human body model (HBM)
3000
V
Charged device model (CDM)
1000
V
Maximum junction temperature (TJ max)
ESD ratings
(1)
2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, AVDD = DVDD = +2.7V to +5.5V, IOVDD = +1.8V to +5.5V, gain = 1X mode, unless
otherwise noted.
DAC8881
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
±0.5
±1
LSB
±0.25
±1
LSB
±4
LSB
±8
LSB
ACCURACY
Linearity error
Measured by line passing through codes 0200h and FE00h
Differential linearity error
Measured by line passing through codes 0200h and FE00h
Monotonicity
Zero-scale error
16
Bits
TA = +25°C, code = 0200h
TMIN to TMAX, code = 0200h
Zero-scale drift
Code = 0200h
±0.5
Gain error
TA = +25°C, Measured by line passing through codes
0200h and FE00h
Gain temperature drift
Measured by line passing through codes 0200h and FE00h
PSRR
VOUT = full-scale, AVDD = +5V ±10%
±1 ppm/°C of FSR
±4
±8
LSB
±0.5
±1
ppm/°C
2
LSB/V
ANALOG OUTPUT (1)
Voltage output (2)
Output voltage drift vs time
0
Device operating for 500 hours
Device operating for 1000 hours
AVDD
V
5
ppm of FSR
8
ppm of FSR
Output current
2.5
Maximum load capacitance
200
pF
+31, –50
mA
Short-circuit current
mA
REFERENCE INPUT (1)
VREFH input voltage range
AVDD = +5.5V
1.25
5.0
AVDD
AVDD = +3V
1.25
2.5
AVDD
VREFH input capacitance
VREFH input impedance
VREFL input voltage range
–0.2
VREFL input capacitance
VREFL input impedance
V
V
5
pF
4.5
kΩ
0
+0.2
V
4.5
pF
5
kΩ
5
μs
DYNAMIC PERFORMANCE (1)
Settling time
To ±0.003% FS, RL = 10kΩ, CL = 50pF, code 1000h to
F000h
Slew rate
From 10% to 90% of 0V to +5V
Code change glitch
Code = 7FFFh to
8000h to 7FFFh
2.5
V/μs
VREFH = 5V, gain = 1X mode
37
nV-s
VREFH = 2.5V, gain = 1X mode
18
nV-s
VREFH = 1.25V, gain = 1X mode
9
nV-s
VREFH = 2.5V, gain = 2X mode
21
nV-s
VREFH = 1.25V, gain = 2X mode
10
nV-s
Digital feedthrough
1
24
30
nV/√Hz
Gain = 2
40
48
nV/√Hz
Output noise voltage density
f = 1kHz to 100kHz,
full-scale output
Output noise voltage
f = 0.1Hz to 10Hz, full-scale output
(1)
(2)
nV-s
Gain = 1
2
μVPP
Ensured by design. Not production tested.
The output from the VOUT pin = [(VREFH – VREFL)/65536] × CODE × Buffer GAIN + VREFL. The maximum range of VOUT is 0V to AVDD.
The full-scale of the output must be less than AVDD; otherwise, output saturation occurs.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = TMIN to TMAX, AVDD = DVDD = +2.7V to +5.5V, IOVDD = +1.8V to +5.5V, gain = 1X mode, unless
otherwise noted.
DAC8881
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (3)
High-level input voltage, VIH
Low-level input voltage, VIL
IOVDD = 4.5V to 5.5V
3.8
IOVDD + 0.3
V
IOVDD = 2.7V to 3.3V
2.1
IOVDD + 0.3
V
IOVDD = 1.7V to 2.0V
1.5
IOVDD + 0.3
V
IOVDD = 4.5V to 5.5V
–0.3
0.8
V
IOVDD = 2.7V to 3.3V
–0.3
0.6
V
IOVDD = 1.7V to 2.0V
–0.3
0.3
V
±10
μA
Digital input current (IIN)
±1
Digital input capacitance
5
pF
DIGITAL OUTPUT (3)
High-level output voltage, VOH
Low-level output voltage, VOL
IOVDD = 2.7V to 5.5V, IOH = –1mA
IOVDD – 0.2
V
IOVDD = 1.7V to 2.0V, IOH = –500μA
IOVDD – 0.2
V
IOVDD = 2.7V to 5.5V, IOL = 1mA
0.2
V
IOVDD = 1.7 to 2.0V, IOL = 500μA
0.2
V
POWER SUPPLY
AVDD
+2.7
+5.5
V
DVDD
+2.7
+5.5
V
IOVDD
+1.7
DVDD
AIDD
VIH = IOVDD, VIL = DGND
DIDD
VIH = IOVDD, VIL = DGND
IOIDD
VIH = IOVDD, VIL = DGND
AIDD power-down
PDN = IOVDD
Power dissipation
AVDD = DVDD = 5.0V
V
1.5
mA
1
10
μA
1
10
μA
25
50
μA
6
7.5
mW
TEMPERATURE RANGE
Specified performance
(3)
4
–40
+105
°C
Ensured by design. Not production tested.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
PIN CONFIGURATION
(1)
SDO
DGND
DVDD
SDOSEL
CS
22
21
20
19
IOVDD
24
23
RGE PACKAGE(1)
QFN-24
(TOP VIEW)
SCLK
1
18
PDN
SDI
2
17
RST
LDAC
3
16
USB/BTC
AGND
4
15
GAIN
AVDD
5
14
RSTSEL
VREFL-S
6
13
NC
DAC8881
10
11
12
NC
RFB
VREFL-F
9
VOUT
VREFH-F
7
8
VREFH-S
(Thermal Pad)
The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left
floating. Keep the thermal pad separate from the digital ground, if possible.
TERMINAL FUNCTIONS
TERMINAL
NO.
NAME
I/O
1
SCLK
I
SPI bus serial clock input
DESCRIPTION
2
SDI
I
SPI bus serial data input
3
LDAC
I
Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent, and the contents of the input
register are transferred to the DAC latch. The DAC output changes to the corresponding level simultaneously when the
DAC latch is updated.
4
AGND
I
Analog ground
5
AVDD
I
Analog power supply
6
VREFL-S
I
Reference low input sense
7
VREFH-S
I
Reference high input sense
8
VOUT
O
Output of output buffer
9
RFB
I
Feedback resistor connected to the inverting input of the output buffer.
10
VREFL-F
I
Reference low input force
11
VREFH-F
I
Reference high input force
12
NC
—
Do not connect.
13
NC
—
Do not connect.
14
RSTSEL
I
Selects the value of the output from the VOUT pin after power-on or hardware reset. If RSTSEL = IOVDD, then register data
= 8000h. If RSTSEL = DGND, then register data = 0000h.
15
GAIN
I
Buffer gain setting. Gain = 1 when the pin is connected to DGND; Gain = 2 when the pin is connected to IOVDD.
16
USB/BTC
I
Input data format selection. Input data are straight binary format when the pin is connected to IOVDD, and in two’s
complement format when the pin is connected to DGND.
17
RST
I
Reset input (active low). Logic low on this pin causes the device to perform a reset.
18
PDN
I
Power-down input (active high). Logic high on this pin forces the device into power-down status. In power-down, the VOUT
pin connects to AGND through 10kΩ resistor.
19
CS
I
SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless CS is low. When CS is
high, SDO is in high-impedance status.
20
SDOSEL
I
SPI serial data output selection. When SDOSEL is tied to IOVDD, the contents of the existing input register are shifted out
from the SDO pin; this is Stand-Alone mode. When SDOSEL is tied to DGND, the contents in the SPI input shift register
are shifted out from the SDO pin; this is Daisy-Chain mode for daisy chaining communication.
21
DVDD
I
Digital power supply (connect to AVDD, pin 5)
22
DGND
I
Digital ground
23
SDO
O
SPI bus serial data output. Refer to the Timing Diagrams for further detail.
24
IOVDD
I
Interface power. Connect to +1.8V for 1.8V logic, +3V for 3V logic, and to +5V for 5V logic.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
TIMING DIAGRAMS
Case 1: Standalone operation without SDO, LDAC tied low.
t1
t2
CS
t3
t4
t7
t6
t5
Input Register
and DAC Latch
Updated
SCLK
t8
Bit 15 (N)
SDI
LDAC
t9
Bit 14 (N)
Bit 1 (N)
Bit 0 (N)
Low
Case 2: Standalone operation without SDO, LDAC active.
t2
t1
CS
Input Register
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 15 (N)
SDI
LDAC
t9
Bit 14 (N)
Bit 1 (N)
Bit 0 (N)
t14
High
t15
DAC Latch
Updated
= Dont Care
Bit 15 = MSB
Bit 0 = LSB
Figure 1. Timing Diagram of Standalone Operation without SDO
6
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
TIMING CHARACTERISTICS for Figure 1 (1) (2) (3)
At –40°C to +105°C, unless otherwise noted.
PARAMETER
fSCLK
Maximum clock frequency
t1
Minumum CS high time
CONDITIONS
t2
CS falling edge to SCLK rising edge
t3
SCLK falling edge to CS falling edge setup
time
t4
SCLK low time
t5
SCLK high time
t6
SCLK cycle time
t7
SCLK rising edge to CS rising edge
t8
Input data setup time
t9
Input data hold time
t14
CS rising edge to LDAC falling edge
t15
LDAC pulse width
(1)
(2)
(3)
MAX
UNIT
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
MIN
40
MHz
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
50
MHz
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
50
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
30
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
8
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
15
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
25
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
20
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
8
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
15
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.
Ensured by design. Not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
Case 1: Standalone operation with output from SDO, LDAC tied low.
t1
t2
CS
Input Register
and DAC Latch
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 15 (N)
SDI
t9
Bit 14 (N)
Bit 1 (N)
t11
High-Z
SDO
LDAC
Bit 15 (N - 1)
from Input Reg.
Bit 14 (N - 1)
from Input Reg.
Bit 0 (N)
t12
t13
Bit 1 (N - 1)
from Input Reg.
Bit 0 (N - 1)
from Input Reg.
High-Z
t10
Low
Case 2: Standalone operation with output from SDO, LDAC active.
t2
t1
CS
Input Register
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 15 (N)
SDI
t9
Bit 14 (N)
Bit 1 (N)
t11
High-Z
SDO
LDAC
High
Bit 15 (N - 1)
from Input Reg.
Bit 14 (N - 1)
from Input Reg.
Bit 0 (N)
t12
Bit 1 (N - 1)
from Input Reg.
t13
Bit 0 (N - 1)
from Input Reg.
t10
t14
High-Z
t15
DAC Latch
Updated
= Dont Care
Bit 15 = MSB
Bit 0 = LSB
Figure 2. Timing Diagram of Standalone Operation with SDO
8
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
Case 1: Daisy Chain, LDAC tied low.
t1
t2
CS
Input Register
and DAC Latch
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 15 (N)
SDI
t9
Bit 14 (N)
Bit 0 (N)
Bit 15 (N + 1)
t11
LDAC
t12
t13
Bit 15 (N)
High-Z
SDO
Bit 0 (N + 1)
Bit 0 (N)
High-Z
t10
Low
Case 2: Daisy Chain, LDAC active.
t1
t2
CS
Input Register
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 15 (N)
SDI
t9
Bit 14 (N)
Bit 0 (N)
Bit 15 (N + 1)
t11
LDAC
High
t12
t13
Bit 15 (N)
High-Z
SDO
Bit 0 (N + 1)
t10
Bit 0 (N)
High-Z
t14
t15
DAC Latch
Updated
= Dont Care
Bit 15 = MSB
Bit 0 = LSB
Figure 3. Timing Diagram of Daisy Chain Mode, Two Cascaded Devices
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TIMING CHARACTERISTICS for Figure 2 and Figure 3 (1) (2) (3)
At –40°C to +105°C, unless otherwise noted.
PARAMETER
fSCLK
Maximum clock frequency
t1
Minumum CS high time
CONDITIONS
t2
CS falling edge to SCLK rising edge
t3
SCLK falling edge to CS falling edge setup
time
t4
SCLK low time
t5
SCLK high time
t6
SCLK cycle time
t7
SCLK rising edge to CS rising edge
t8
Input data setup time
t9
Input data hold time
t10
SDO active from CS falling edge
t11
SDO data valid from SCLK falling edge
t12
SDO data hold from SCLK rising edge
t13
SDO High-Z from CS rising edge
t14
CS rising edge to LDAC falling edge
t15
(1)
(2)
(3)
10
LDAC pulse width
MAX
UNIT
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
MIN
20
MHz
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
25
MHz
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
50
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
30
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
8
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
25
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
20
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
25
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
20
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
50
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
40
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
15
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
20
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
15
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
25
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
20
ns
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
8
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
15
ns
3.6 ≤ DVDD ≤ 5.5V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.
Ensured by design. Not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VDD = +5V
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +25°C
0.8
0.6
0.6
0.4
0.4
0.2
0
-0.2
-0.4
0
-0.2
-0.4
-0.6
-0.8
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 4.
Figure 5.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = -40°C
0.8
0.6
0.6
0.4
0.4
0.2
0
-0.2
-0.4
TA = -40°C
0.8
DNL Error (LSB)
INL Error (LSB)
0.2
-0.6
-1.0
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 6.
Figure 7.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +105°C
0.8
0.6
0.6
0.4
0.4
0.2
0
-0.2
-0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
TA = +105°C
0.8
DNL Error (LSB)
INL Error (LSB)
TA = +25°C
0.8
DNL Error (LSB)
INL Error (LSB)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 8.
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 9.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
LINEARITY ERROR
vs TEMPERATURE
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
1.0
1.0
0.8
0.8
0.6
INL Max
0.4
DNL Error (LSB)
INL Error (LSB)
0.6
0.2
0
-0.2
INL Min
-0.4
0
-0.2
DNL Min
-0.4
-0.6
-0.8
-0.8
-1.0
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
-40
0
20
40
60
Temperature (°C)
80
100
Figure 11.
LINEARITY ERROR
vs TEMPERATURE (GAIN = 2X MODE)
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE (GAIN = 2X MODE)
120
1.0
VREFH = 2.5V
VREFL = 0V
0.8
VREFH = 2.5V
VREFL = 0V
0.8
0.6
0.6
INL Max
DNL Error (LSB)
0.4
0.2
0
-0.2
-0.4
INL Min
0.4
DNL Max
0.2
0
-0.2
DNL Min
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
-40
-20
0
20
40
60
Temperature (°C)
80
100
Figure 12.
Figure 13.
LINEARITY ERROR
vs SUPPLY VOLTAGE
DIFFERENTIAL LINEARITY ERROR
vs SUPPLY VOLTAGE
1.0
120
1.0
VREFH = 2.5V
VREFL = 0V
0.8
VREFH = 2.5V
VREFL = 0V
0.8
0.6
0.4
DNL Error (LSB)
0.6
INL Max
0.2
0
-0.2
INL Min
-0.4
0.4
DNL Max
0.2
0
-0.2
DNL Min
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
2.5
3.0
3.5
4.0
4.5
5.0
Supply Voltage (V)
5.5
6.0
2.5
Figure 14.
12
-20
Figure 10.
1.0
INL Error (LSB)
DNL Max
0.2
-0.6
-1.0
INL Error (LSB)
0.4
3.0
3.5
4.0
4.5
5.0
Supply Voltage (V)
5.5
6.0
Figure 15.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR
vs REFERENCE VOLTAGE
1.0
1.0
0.8
0.8
0.6
0.6
0.4
DNL Error (LSB)
INL Error (LSB)
LINEARITY ERROR
vs REFERENCE VOLTAGE
INL Max
0.2
0
-0.2
INL Min
-0.4
0
-0.2
DNL Min
-0.4
-0.6
-0.8
-0.8
-1.0
0
1
2
3
4
Reference Voltage (V)
5
6
0
1
2
3
4
Reference Voltage (V)
5
6
Figure 16.
Figure 17.
ENDPOINT ERROR
vs TEMPERATURE
ENDPOINT ERROR
vs TEMPERATURE (GAIN = 2X MODE)
1.0
1.0
0.8
0.8
0.6
0.6
Endpoint Error (mV)
Endpoint Error (mV)
DNL Max
0.2
-0.6
-1.0
0.4
0.2
Plus Full-Scale Error
0
-0.2
Minus Full-Scale Error
-0.4
VREFH = 2.5V
VREFL = 0V
Plus Full-Scale Error
0.4
0.2
0
-0.2
Minus Full-Scale Error
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
125
-55
AVDD = 5.0V
VREFH = 5.0V
VREFL = 0V
85
105
AVDD = 2.7V
VREFH = 2.7V
VREFL = 0V
600
AVDD = 2.7V
VREFH = 2.5V
VREFL = 0V
300
125
AVDD = 5.0V
VREFH = 2.5V
VREFL = 0V
900
AVDD Supply Current (mA)
700
400
25
45
65
Temperature (°C)
AVDD SUPPLY CURRENT
vs DIGITAL INPUT CODE (GAIN = 2X MODE)
AVDD = 5.0V
VREFH = 2.5V
VREFL = 0V
500
5
AVDD SUPPLY CURRENT
vs DIGITAL INPUT CODE
1000
800
-15
Figure 19.
1000
900
-35
Figure 18.
1100
AVDD Supply Current (mA)
0.4
800
700
600
AVDD = 2.7V
VREFH = 1.25V
VREFL = 0V
500
400
300
200
100
0
200
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 20.
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 21.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
AVDD SUPPLY CURRENT
vs TEMPERATURE
AVDD POWER-DOWN CURRENT
vs TEMPERATURE
50
1000
AVDD Supply Current (mA)
AVDD Supply Current (mA)
1200
800
VREFH = 5.0V
VREFL = 0V
Gain = 1X Mode
600
VREFH = 2.5V
VREFL = 0V
Gain = 2X Mode
400
200
40
30
AVDD = 5.0V
20
AVDD = 2.7V
10
DAC Code Set to FC00h
0
0
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
125
-55
5
25
45
65
Temperature (°C)
85
105
Figure 23.
REFERENCE CURRENT
vs DIGITAL INPUT CODE
REFERENCE CURRENT
vs DIGITAL INPUT CODE (GAIN = 2X MODE)
1.5
VREFH Current
0.5
0
VREFL Current
-0.5
-1.0
125
VREFH = 2.5V
VREFL = 0V
1.0
Reference Current (mA)
1.0
VREFH Current
0.5
0
-0.5
VREFL Current
-1.0
-1.5
-1.5
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 24.
Figure 25.
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY
(Operation Near AVDD Rail)
5.0
5.00
DAC Loaded with FFFFh
4.5
DAC Loaded with FFFFh
4.0
4.95
DAC Loaded with FE00h
3.5
3.0
VOUT (V)
VOUT (V)
-15
Figure 22.
1.5
Reference Current (mA)
-35
2.5
2.0
4.90
DAC Loaded with FC00h
4.85
1.5
1.0
DAC Loaded with 0000h
0.5
DAC Loaded with F800h
4.80
0
4.75
0
3
6
9
I(SOURCE/SINK) (mA)
12
15
0
Figure 26.
14
1
2
3
ISOURCE (mA)
4
5
Figure 27.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY
(Operation Near AGND Rail)
IOVDD SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
200
0.25
IOVDD Supply Current (mA)
180
0.20
VOUT (V)
DAC Loaded with 0800h
0.15
DAC Loaded with 0400h
0.10
DAC Loaded with 0200h
0.05
IOVDD = 5V
160
140
120
100
80
60
40
IOVDD = 2.7V
20
DAC Loaded with 0000h
0
0
1
2
3
0
4
0
5
ISINK (mA)
0.5
1.0
1.5 2.0 2.5 3.0 3.5
Logic Input Voltage (V)
Figure 28.
Figure 29.
LARGE SIGNAL
SETTLING TIME
LARGE SIGNAL
SETTLING TIME
4.0
4.5
5.0
Large-Signal Output
2V/div
Large-Signal Output
Small-Signal Error
2V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 0000h to FFFFh
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Time (2ms/div)
Code Change: FFFFh to 0000h
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 30.
Figure 31.
LARGE SIGNAL
SETTLING TIME
LARGE SIGNAL
SETTLING TIME
Large-Signal Output
2V/div
Large-Signal Output
2V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 1000h to F000h
Output Loaded with 10kW and
50pF to AGND
Small-Signal Error
5V/div
LDAC
Signal
Time (2ms/div)
Code Change: F000h to 1000h
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 32.
Figure 33.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
LARGE SIGNAL
SETTLING TIME (GAIN = 2X MODE)
VREFH = 2.5V
LARGE SIGNAL
SETTLING TIME (GAIN = 2X MODE)
Code Change: FFFFh to 0000h
Output Loaded with 10kW and
50pF to AGND
VREFH = 2.5V
Large-Signal Output
2V/div
Large-Signal Output
Small-Signal Error
2V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 0000h to FFFFh
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Time (2ms/div)
Time (2ms/div)
Figure 34.
Figure 35.
LARGE SIGNAL
SETTLING TIME (GAIN = 2X MODE)
LARGE SIGNAL
SETTLING TIME (GAIN = 2X MODE)
VREFH = 2.5V
VREFH = 2.5V
Large-Signal Output
2V/div
Large-Signal Output
Small-Signal Error
2V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 1000h to F000h
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Code Change: F000h to 1000h
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Time (2ms/div)
Figure 36.
Figure 37.
MAJOR CARRY GLITCH
MAJOR CARRY GLITCH
Code Change: 7FFFh to 8000h
Output Loaded with 10kW and
50pF to AGND
Gain = 1X Mode
VREFH = +5V
Gain = 1X Mode
VREFH = +5V
Integrated Glitch Energy (34nV-s)
100mV/div
VOUT Signal
100mV/div
VOUT Signal
Integrated Glitch Energy (37nV-s)
5V/div
LDAC
Signal
5V/div
Time (2ms/div)
Code Change: 8000h to 7FFFh
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 38.
16
LDAC
Signal
Figure 39.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
MAJOR CARRY GLITCH
MAJOR CARRY GLITCH
Code Change: 7FFFh to 8000h
Output Loaded with 10kW and
50pF to AGND
Gain = 1X Mode
VREFH = +2.5V
Gain = 1X Mode
VREFH = +2.5V
Integrated Glitch Energy (16nV-s)
VOUT Signal
100mV/div
100mV/div
VOUT Signal
Integrated Glitch Energy (18nV-s)
5V/div
LDAC
Signal
5V/div
Code Change: 8000h to 7FFFh
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 40.
Figure 41.
OUTPUT NOISE DENSITY
vs FREQUENCY
LOW-FREQUENCY OUTPUT NOISE
(0.1Hz to 10Hz)
180
DAC Code Set to 8000h
Output Unloaded
160
140
120
2mV/div
Output Voltage Noise Density (nV/ÖHz)
Time (2ms/div)
LDAC
Signal
100
80
60
Gain = 2X Mode
40
20
Gain = 1X Mode
0
1
10
100
1k
Frequency (Hz)
10k
100k
Figure 42.
Time (1s/div)
Figure 43.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VDD = +2.7V
At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +25°C
0.8
0.6
0.6
0.4
0.4
0.2
0
-0.2
-0.4
0
-0.2
-0.4
-0.6
-0.8
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 45.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
TA = -40°C
0.8
0.6
0.4
0.4
DNL Error (LSB)
0.6
0.2
0
-0.2
-0.4
TA = -40°C
0.8
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 46.
Figure 47.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +105°C
0.8
0.4
DNL Error (LSB)
0.6
0.4
0.2
0
-0.2
-0.4
TA = +105°C
0.8
0.6
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 48.
18
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 44.
1.0
INL Error (LSB)
0.2
-0.6
-1.0
INL Error (LSB)
TA = +25°C
0.8
DNL Error (LSB)
INL Error (LSB)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 49.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VDD = +2.7V (continued)
At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
LINEARITY ERROR
vs REFERENCE VOLTAGE
1.0
1.0
0.8
0.8
0.6
0.6
INL Max
0.2
0
-0.2
0.4
DNL Error (LSB)
0.4
INL Error (LSB)
DIFFERENTIAL LINEARITY ERROR
vs REFERENCE VOLTAGE
INL Min
-0.4
0
-0.2
-0.6
-0.6
-0.8
-0.8
-1.0
0
0.5
1.0
1.5
2.0
VREFH Reference Voltage (V)
2.5
3.0
0
0.5
1.0
1.5
2.0
VREFH Reference Voltage (V)
Figure 50.
Figure 51.
AVDD SUPPLY CURRENT
vs TEMPERATURE
REFERENCE CURRENT
vs DIGITAL INPUT CODE
2.5
3.0
1.00
1000
900
0.75
VREF = 2.5V, Gain = 1X Mode
800
700
Reference Current (mA)
AVDD Supply Current (mA)
DNL Min
-0.4
-1.0
VREF = 1.25V, Gain = 2X Mode
600
500
400
300
200
100
VREFH Current
0.50
VREFH = 2.5V
VREFL = 0V
0.25
0
VREFL Current
-0.25
-0.50
-0.75
DAC Code Set to FFFFh
0
-1.00
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
0
125
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 52.
Figure 53.
REFERENCE CURRENT
vs DIGITAL INPUT CODE (GAIN = 2X MODE)
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY
1.00
3.0
DAC Loaded with FFFFh, VREFH = 2.7V
VREFH = 1.25V
VREFL = 0V
0.75
2.5
0.50
VREFH Current
0.25
0
DAC Loaded with FFFFh, VREFH = 2.5V
2.0
VREFL Current
-0.25
VOUT (V)
Reference Current (mA)
DNL Max
0.2
1.5
1.0
-0.50
0.5
-0.75
DAC Loaded with 0000h
0
-1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 54.
3
6
9
I(SOURCE/SINK) (mA)
12
15
Figure 55.
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VDD = +2.7V (continued)
At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY
(Operation Near AVDD Rail)
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY
(Operation Near AGND Rail)
2.70
0.25
DAC Loaded with FFFFh
2.65
VOUT (V)
2.60
DAC Loaded
with FE00h
2.55
DAC Loaded
with FC00h
2.50
VOUT (V)
0.20
DAC Loaded
with F800h
DAC Loaded
with 0400h
0.15
DAC Loaded
with 0800h
DAC Loaded
with 0200h
0.10
DAC Loaded with FFFFh, VREFH = 2.5V
0.05
2.45
VREFH = 2.7V, unless otherwise noted.
2.40
DAC Loaded with 0000h
0
0
1
2
3
ISOURCE (mA)
4
5
0
1
2
3
4
5
ISINK (mA)
Figure 56.
Figure 57.
LARGE SIGNAL
SETTLING TIME
LARGE SIGNAL
SETTLING TIME
Code Change: FFFFh to 0000h
Output Loaded with 10kW and
50pF to AGND
Large-Signal Output
1V/div
Large-Signal Output
Small-Signal Error
1V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 0000h to FFFFh
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Time (2ms/div)
Time (2ms/div)
Figure 58.
Figure 59.
LARGE SIGNAL
SETTLING TIME
LARGE SIGNAL
SETTLING TIME
Large-Signal Output
Large-Signal Output
1V/div
Small-Signal Error
1V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 1000h to F000h
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Time (2ms/div)
Time (2ms/div)
Figure 60.
20
Code Change: F000h to 1000h
Output Loaded with 10kW and
50pF to AGND
Figure 61.
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TYPICAL CHARACTERISTICS: VDD = +2.7V (continued)
At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted.
MAJOR CARRY GLITCH
MAJOR CARRY GLITCH
Code Change: 7FFFh to 8000h
Output Loaded with 10kW and
50pF to AGND
Gain = 1X Mode
VREFH = +2.5V
Gain = 1X Mode
VREFH = +2.5V
Integrated Glitch Energy (17.5nV-s)
100mV/div
VOUT Signal
VOUT Signal
100mV/div
Integrated Glitch Energy (16.5nV-s)
5V/div
LDAC
Signal
Code Change: 8000h to 7FFFh
Output Loaded with 10kW and
50pF to AGND
LDAC
Signal
5V/div
Time (2ms/div)
Time (2ms/div)
Figure 62.
Figure 63.
MAJOR CARRY GLITCH
MAJOR CARRY GLITCH
Code Change: 7FFFh to 8000h
Output Loaded with 10kW and
50pF to AGND
Gain = 1X Mode
VREFH = +1.25V
Gain = 1X Mode
VREFH = +1.25V
Integrated Glitch Energy (9.4nV-s)
100mV/div
VOUT Signal
100mV/div
VOUT Signal
Integrated Glitch Energy (7.8nV-s)
5V/div
LDAC
Signal
5V/div
Time (2ms/div)
LDAC
Signal
Code Change: 8000h to 7FFFh
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 64.
Figure 65.
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THEORY OF OPERATION
GENERAL DESCRIPTION
The DAC8881 is a single-channel, 16-bit, serial-input, voltage-output digital-to-analog converter (DAC). The
architecture is an R-2R ladder configuration with the four MSBs segmented, followed by an operational amplifier
that serves as a buffer, as shown in Figure 66. The on-chip output buffer allows rail-to-rail output swings while
providing a low output impedance to drive loads. The DAC8881 operates from a single analog power supply that
ranges from 2.7V to 5.5V, and typically consumes 850μA when operating with a 3V supply. Data are written to
the device in a 16-bit word format, via an SPI serial interface. To enable compatibility with 1.8V, 3V, or 5V logic
families, an IOVDD supply pin is provided. This pin allows the DAC8881 input and output logic to be powered
from the same logic supply used to interface signals to and from the device. Internal voltage translators are
included in the DAC8881 to interface digital signals to the device core. Separate AVDD and DVDD supply pins are
provided, but should be connected together. See Figure 67 for the basic configuration of the DAC8881.
To ensure a known power-up state, the DAC8881 is designed with a power-on reset function. Upon power-up,
the DAC8881 is reset to either zero-scale or midscale depending on the state of the RSTSEL pin. The device
can also be hardware reset by using the RST and RSTSEL pins.
RFB(1)
RFB
R
VOUT
2R
2R
2R
2R
2R
2R
2R
2R
2R
5kW
VREFH
5kW
NOTE: (1) RFB = 5kW for gain = 1
RFB = 10kW for gain = 2.
VREFH-F
VREFH-S
VREFL-F
VREFL-S
Figure 66. DAC8881 Architecture
22
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SDOSEL
Chip-Select
CS
19
SDOSEL
20
DVDD
21
22
SDO
4
15
14
5
(Thermal Pad)
VOUT
VREFH-S
13
RST
Reset DAC Registers
USB/BTC
GAIN
RSTSEL
NC
12
6
7
VREFL-S
DAC8881
PDN
NC
AVDD
16
3
11
AGND
17
VREFH-F
Load DAC Registers
2
10
LDAC
18
9
Serial Data In
1
VREFL-F
SDI
8
SCLK
Clock
23
1mF
IOVDD
+
24
0.1mF
DGND
1mF
RFB
+
1.8V to 5V
0.1mF
Serial Data Out
+5V
0V to +5.0V
External Reference
+5.0000V
Figure 67. Basic Configuration
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ANALOG OUTPUT
The DAC8881 offers a force and sense output configuration for the high open-loop gain output amplifier. This
feature allows the loop around the output amplifier to be closed at the load (as shown in Figure 68), thus
ensuring an accurate output voltage. The output buffer VOUT and RFB pins are provided so that the output op amp
buffer feedback can be connected at the load. Without a driven load, the DAC8881 output typically swings to
within 15mV of the AGND and AVDD supply rails. Because of the high accuracy of these DACs, system design
problems such as grounding and contact resistance become very important. A 16-bit converter with a 5V
full-scale range has a 1LSB value of 76μV. With a load current of 1mA, a series wiring and connector resistance
of only 80mΩ (RW2) causes a voltage drop of 80μV. In terms of a system layout, the resistivity of a typical
1-ounce copper-clad printed circuit board is 0.5mΩ per square. For a 1mA load, a 0.25mm wide printed circuit
conductor 25mm long results in a voltage drop of 50μV.
SDOSEL
Chip-Select
19
CS
DVDD
SDOSEL
20
23
21
SDO
4
15
5
14
(Thermal Pad)
8
VOUT
VREFH-S
RW2
13
RST
Reset DAC Registers
USB/BTC
GAIN
RSTSEL
NC
12
6
7
VREFL-S
16
DAC8881
PDN
NC
AVDD
3
11
AGND
17
VREFH-F
Load DAC Registers
2
10
LDAC
18
9
Serial Data In
1
VREFL-F
SDI
RFB
SCLK
Clock
22
1mF
IOVDD
+
24
0.1mF
DGND
1mF
RW1
+
1.8V to 5V
0.1mF
Serial Data Out
+5V
VOUT
External Reference
+5.0000V
Figure 68. Analog Output Closed-Loop Configuration
(RW1 and RW2 represent wiring resistance)
24
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REFERENCE INPUTS
The reference high input, VREFH, can be set to any voltage in the range of 1.25V to AVDD. The reference low
input, VREFL, can be set to any voltage in the range of –0.2V to +0.2V (to provide a small offset to the output of
the DAC8881, if desired). The current into VREFH and out of VREFL depends on the DAC code, and can vary from
approximately 0.5mA to 1mA in the gain = 1X mode of operation. The reference high and low inputs appear as
varying loads to the external reference circuit. If the external references can source or sink the required current,
and if low impedance connections are made to the VREFH and VREFL pins, external reference buffers are not
required. Figure 67 shows a simple configuration of the DAC8881 using external references without force/sense
reference buffers.
Kelvin sense connections for the reference high and low are included on the DAC8881. When properly used with
external reference buffer op amps, these reference Kelvin sense pins ensure that the driven reference high and
low voltages remain stable versus varying reference load currents. Figure 69 shows an example of a reference
force/sense configuration of the DAC8881 operating from a single analog supply voltage. Both the VREFL and
VREFH reference voltages are set to levels of 100mV from the DAC8881 supply rails, and are derived from a +5V
external reference. Figure 71 and Figure 70 illustrate the effect of not using the reference force/sense buffers to
drive the DAC8881 VREFL and VREFH pins. A slight degradation in INL and DNL performance of approximately 0.1
LSB may be seen without the use of the force/sense buffer configuration.
SCLK
SDI
LDAC
+5V
AGND
External Reference
+5.0000V
AVDD
OPA2350
VREFL-S
3
4
DAC8881
5
6
11
9
12
NC
VREFH-F
96kW
RFB
VREFH-S
1000pF
10
+4.900V
VREFL-F
7
50W
8
2200pF
2
VOUT
2kW
1
+0.100V
50W
2kW
2200pF
1000pF
LE (LSB)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
DLE (LSB)
LE (LSB)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
DLE (LSB)
Figure 69. Buffered References (VREFH = +4.900V and VREFL = 100mV)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
+25°C
+25°C
0
8192
16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 70. Linearity and Differential Linearity Error
for Figure 67 without Reference Buffers
+25°C
+25°C
0
8192
16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 71. Linearity and DifferentialLinearity Error
for Figure 69 with Reference Buffers
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SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
OUTPUT RANGE
The maximum output range of the DAC8881 is VREFL to VREFH × G, where G is the output buffer gain set by the
GAIN pin. When the GAIN pin is connected to DGND, the output buffer gain = 1. When the GAIN pin is
connected to IOVDD, the output buffer gain = 2. The output range must not be greater than AVDD; otherwise,
output saturation occurs. The DAC8881 output transfer function is given in Equation 1:
V
- VREFL
VOUT = REFH
´ CODE ´ Buffer Gain + VREFL
65536
(1)
Where:
CODE = 0 to 65535. This is the digital code loaded to the DAC.
Buffer Gain = 1 or 2 (set by the GAIN pin).
VREFH = reference high voltage applied to the device.
VREFL = reference low voltage applied to the device.
INPUT DATA FORMAT
The USB/BTC pin defines the input data format. When this pin is connected to IOVDD, the input data format is
straight binary, as shown in Table 1. When this pin is connected to DGND, the input data format is two's
complement, as shown in Table 2.
Table 1. Output vs Straight Binary Code
USB CODE
5V RANGE
DESCRIPTION
FFFFh
+4.99992
+Full-Scale – 1LSB
C000h
+3.75000
3/4-Scale
8000h
+2.50000
Midscale
4000h
+1.25000
1/4-Scale
0000h
0.00000
Zero-Scale
Table 2. Output vs Two's Complement Code
BTC CODE
5V RANGE
DESCRIPTION
7FFFh
+4.99992
+Full-Scale – 1LSB
4000h
+3.75000
3/4-Scale
0000h
+2.50000
Midscale
FFFFh
+2.49992
Midscale – 1LSB
C000h
+1.25000
1/4-Scale
8000h
0.00000
Zero-Scale
POWER DOWN
The DAC8881 has a hardware power-down function. When the PDN pin is high, the device is in power-down
mode. The VOUT pin is connected to ground through an internal 10kΩ resistor, but the contents of the input
register and the DAC latch do not change. In power-down mode, SPI communication is still active.
HARDWARE RESET
When the RST pin is low, the device is in hardware reset mode, and the input register and DAC latch are set to
the value defined by the RSTSEL pin. After RST goes high, the device is in normal operating mode.
26
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POWER-ON RESET
The DAC8881 has a power-on reset function. After power-on, the value of the input register, the DAC latch, and
the output from the VOUT pin are set to the value defined by the RSTSEL pin.
PROGRAM RESET VALUE
After a power-on reset or a hardware reset, the output voltage from the VOUT pin and the values of the input
register and DAC latch are determined by the status of the RSTSEL pin and the input data format, as shown in
Table 3.
Table 3. Reset Value
RSTSEL PIN
USB/BTC PIN
INPUT FORMAT
VOUT
VALUE OF INPUT REGISTER AND DAC LATCH
DGND
IOVDD
IOVDD
IOVDD
Straight Binary
0
0000h
Straight Binary
Midscale
DGND
8000h
DGND
Two's Complement
Midscale
0000h
IOVDD
DGND
Two's Complement
0
8000h
SERIAL INTERFACE
The DAC8881 is controlled by a versatile 3-wire serial interface that operates at clock rates of up to 50MHz and
is compatible with SPI, QSPI™, MICROWIRE™, and DSP™ interface standards.
Input Shift Register
Data are loaded into the device as a 16-bit word under the control of the serial clock input, SCLK. The timing
diagrams for this operation are shown in the Timing Diagram section.
The CS input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be
transferred into the device only while CS is low. To start the serial data transfer, CS should be taken low,
observing the minimum CS falling edge to SCLK rising edge setup time, t2. After CS goes low, serial data are
clocked into the device input shift register on the rising edges of SCLK for 16 or more clock pulses. If a frame
contains less than 16 bits of data, the frame is invalid. Invalid data are not written into the input register and
DAC, although the input register and DAC will continue to hold data from the preceding valid data cycle. If more
than 16 bits of data are transmitted in one frame, the last 16 bits are written into the shift register and DAC. CS
may be taken high after the rising edge of the 16th SCLK pulse, observing the minimum SCLK rising edge to CS
rising edge time, t7. The contents of the shift register are transferred into the input register on the rising edge of
CS. When data have been transferred into the input register of the DAC, the corresponding DAC register and
DAC output can be updated by taking the LDAC pin low.
Stand-Alone Mode
When the SDOSEL pin is tied to IOVDD, the interface is in Stand-Alone mode. This mode provides serial
readback for diagnostic purposes. The new input data (16 bits) are clocked into the device shift register and the
existing data in the input register (16 bits) are shifted out from the SDO pin. If more than 16 SCLKs are clocked
when CS is low, the contents of the input register are shifted out from the SDO pin, followed by zeroes; the last
16 bits of input data remain in the shift register. If less than 16 SCLKs are clocked while CS is low, the data from
the SDO pin are part of the data in the input register and must be ignored. Refer to Figure 2 for further detail.
Daisy-Chain Mode
When the SDOSEL pin is tied to GND, the interface is in Daisy-Chain mode. For systems that contain several
DACs, the SDO pin may be used to daisy-chain several devices together.
In Daisy-Chain mode, SCLK is continuously applied to the input shift register while CS is low. If more than 16
clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. These data are
clocked out on the falling edge of SCLK and are valid on the rising edge. By connecting this line to the DIN input
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on the next DAC in the chain, a multi-DAC interface is constructed. 16 clock pulses are required for each DAC in
the system. Therefore, the total number of clock cycles must be equal to (16 x N), where N is the total number of
devices in the chain. When the serial transfer to all devices is complete, CS should be taken high. This action
prevents any further data from being clocked into the input shift register. The contents in the shift registers are
transferred into the relevant input registers on the rising edge of the CS signal.
A continuous SCLK source may be used if CS can be held low for the correct number of clock cycles.
Alternatively, a burst clock containing the exact number of clock cycles can be used and CS can be taken high
some time later. When the transfer to all input registers is complete, a common LDAC signal updates all DAC
registers, and all analog outputs update simultaneously.
DOUBLE-BUFFERED INTERFACE
The DAC8881 has a double-buffered interface consisting of two register banks: the input register and the DAC
latch. The input register is connected directly to the input shift register and the digital code is transferred to the
input register upon completion of a valid write sequence. The DAC latch contains the digital code used by the
resistor R-2R ladder. The contents of the DAC latch defines the output from the DAC.
Access to the DAC register is controlled by the LDAC pin. When LDAC is high, the DAC register is latched and
the input register can change state without affecting the contents of the DAC latch. When LDAC is low, however,
the DAC latch becomes transparent and the contents of the input register is transferred to the DAC register.
Load DAC Pin (LDAC)
LDAC transfers data from the input register to the DAC register (and, therefore, updates the DAC output). The
contents of the DAC latch (and the output from DAC) can be changed in two ways, depending on the status of
LDAC.
Synchronous Mode
When LDAC is tied low, the DAC register updates as soon as new data are transferred into the input register
after the rising edge of CS.
Asynchronous Mode
When LDAC is high, the DAC latch is latched. The DAC latch (and DAC output) is not updated at the same time
that the input register is written to. When LDAC goes low, the DAC register updates with the contents of the input
register.
1.8V TO 5.5V LOGIC INTERFACE
All digital input and output pins are compatible with any logic supply voltage between 1.8V and 5.5V. Connect the
interface logic supply voltage to the IOVDD pin. Although timing is specified down to 2.7V (see the Timing
Characteristics), IOVDD can operate as low as 1.8V, but with degraded timing and temperature performance. For
the lowest power consumption, logic VIH levels should be as close as possible to IOVDD, and logic VIL levels
should be as close as possible to GND. Note that the DAC8881 core internal digital logic operates from the same
voltage as the 2.7V to 5.5V AVDD supply, so the DVDD pin must also be connected to the AVDD supply voltage.
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APPLICATION INFORMATION
BIPOLAR OPERATION USING THE DAC8881
The DAC8881 is designed for single-supply operation; however, a bipolar output range is also possible using the
circuit shown in Figure 72. This circuit gives a bipolar output voltage range of VBIP, where VBIP is represented by
Equation 2. Note that for this circuit to work, the DAC8881 must operate in the gain = 1X mode configuration with
GAIN = DGND. The output voltage for any input code can be calculated with Figure 72:
VBIP(CODE) = 1 +
R
R3 R3
CODE
- 3 ´ VREF
+
´
R1
R 2 R1
65536
(2)
Where:
VBIP(CODE) = bipolar output voltage versus CODE from the OPA211.
CODE = 0 to 65535. This is the digital code loaded to the DAC.
VREF = reference high voltage applied to the DAC8881.
By first choosing a value for resistor R3, R1 and R2 can be determined by Equation 3 and Equation 4,
respectively:
V
R1 = REF ´ R3
VBIP
(3)
VREF ´ R3
R2 =
VBIP - VREF
(4)
Where:
VBIP= peak desired output voltage for bipolar output.
VREF = reference high voltage applied to the DAC8881. NOTE: VBIP ≥ VREF.
R3 = OPA211 feedback resistor chosen by user.
Note that R2 is not required in the circuit of Figure 72 for bipolar output voltage ranges equal to ±VREF.
Using the previous equations, and with VREF = 5V and R3 set to 10kΩ, a ±8V output span can be achieved with
R1 calculated to be 6.25kΩ and R2 to be 16.67kΩ.
Similarly, a near ±15V rail-to-rail output can be achieved with R1 calculated to be 3.33kΩ and R2 calculated to be
5kΩ.
VREFL
+15V
DAC8881 VOUT
VREFH
R2
R1
OPA211
VBIP
-15V
R3
VREF
NOTE: Some pins omitted for clarity.
Figure 72. Bipolar Operation Using the DAC8881
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
DAC8881SRGER
ACTIVE
QFN
RGE
24
3000
TBD
Call TI
Call TI
DAC8881SRGERG4
ACTIVE
QFN
RGE
24
3000
TBD
Call TI
Call TI
DAC8881SRGET
ACTIVE
QFN
RGE
24
250
TBD
Call TI
Call TI
DAC8881SRGETG4
ACTIVE
QFN
RGE
24
250
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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Products
Applications
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amplifier.ti.com
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www.ti.com/audio
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dataconverter.ti.com
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www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Telephony
www.ti.com/telephony
Low Power
Wireless
www.ti.com/lpw
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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