Vishay DG2303DL High-speed, low ron, 1.8-v/2.5-v/3.3-v/5-v, spst analog switch (1-bit bus switch) Datasheet

DG2303
New Product
Vishay Siliconix
High-Speed, Low rON, 1.8-V/2.5-V/3.3-V/5-V, SPST Analog Switch
(1-Bit Bus Switch)
FEATURES
D
D
D
D
D
D
SC-70 5-Lead Package
5-W Switch Connection Between Two Ports
Minimal Propagation Delay Through The Switch
Low ICC
Zero Bounce In Flow-Through Mode
Control Inputs Compatible with TTL Level
DESCRIPTION
The DG2303 is a high-speed, 1-bit, low power,
TTL-compatible bus switch.
Using sub-micron CMOS
technology, DG2303 achieves low on-resistance and
negligible propagation delay.
and B. When the output enable (OE) is low, the input/output
pins are connected. When the OE is high, the switch is open
and a high-impedance state exists between input/output pins
A and B.
The DG2303 consist of a bi-directional input/output pins A
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
TRUTH TABLE
SC-70
A
1
B
2
GND
3
5
4
V+
OE
B
Function
L
HiZ State
Disconnect
H
A
Connect
OE
Top View
Device Marking: E6
Document Number: 72073
S-03422—Rev. A, 03-Mar-03
ORDERING INFORMATION
Temp Range
Package
Part Number
-40 to 85°C
SC70-5
DG2303DL
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DG2303
New Product
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Reference to GND
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 V
OE, A, Ba . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+ + 0.3 V)
Continuous Current (Any terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . "50 mA
Peak Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "200 mA
(Pulsed at 1 ms, 10% duty cycle)
Storage Temperature (D Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Power Dissipation (Packages)b
5-Pin SC70c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mW
Notes:
a. Signals on A, or B or OE exceeding V+ will be clamped by internal
diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC Board.
c. Derate 3.1 mW/_C above 70_C
SPECIFICATIONS (V+ = 5.0 V)
Limits
Test Conditions
Otherwise Unless Specified
Parameter
Symbol
-40 to 85_C
V+ = 1.65 V to 5.5 V, VIN = VIH or VILe
Tempa
Minb
Typc
Maxb
Unit
DC Characteristics
On-Resistance
rON Flatnessd
rON
rON Flatness
V+ = 1.8 V, VA = 0 V, IB = 4 mA
Full
28.0
V+ = 1.8 V, VA = 1.8 V, IB = 4 mA
Full
60.0
V+ = 2.3 V, VA = 0 V, IB = 8 mA
Full
12.0
V+ = 2.3 V, VA = 2.3 V, IB = 8 mA
Full
30.0
V+ = 3.0 V, VA = 0 V, IB = 24 mA
Full
9.0
V+ = 3.0 V, VA = 3.0 V, IB = 24 mA
Full
20.0
V+ = 4.5 V, VA = 0 V, IB = 30 mA
Full
7.0
V+ = 4.5 V, VA = 2.4 V, IB = 15 mA
Full
12.0
V+ = 4.5 V, VA = 4.5 V, IB = 30 mA
Full
V+ = 1.8 V, VA = 0 V to V+, IB = 4 mA
Full
125
15.0
V+ = 2.5 V, VA = 0 V to V+, IB = 8 mA
Full
28
V+ = 3.3 V, VA = 0 V to V+, IB = 24 mA
Full
12
V+ = 5.0 V, VA = 0 V to V+, IB = 30 mA
Full
Switch Off Leakage Current
I(off)
V+ = 5.5 V, VA = 1 V/4.5 V, VB = 4.5 V/1 V
Full
-10
10
Switchl-On Leakage Current
I(on)
V+ = 5.5 V, VA = VB = 1 V/4.5 V
Full
-10
10
V+ = 1.65 V to 1.95 V
Full
1.35
V+ = 2.3 V to 2.7 V
Full
1.6
V+ = 3.0 V to 3.6 V
Full
2.0
V+ = 4.5 V to 5.5 V
Full
2.4
V+ = 1.65 V to 1.95 V
Full
0.4
V+ = 2.3 V to 2.7 V
Full
0.4
V+ = 3.0 V to 3.6 V
Full
0.6
V+ = 4.5 V to 5.5 V
Full
VOE = 0 or V+
Full
VLD = Open, V= 1.65 V to 1.95 V, (Figure 1 and 2)
Full
5
VLD = Open, V= 2.3 V to 2.7 V, (Figure 1 and 2)
Full
2
VLD = Open, V= 3.0 V to 3.6 V, (Figure 1 and 2)
Full
1
VLD = Open, V= 4.5 V to 5.5 V, (Figure 1 and 2)
Full
1
Input High Voltage
VIH
Input Low Voltage
VIL
Input Current
IIL or IIH
W
6
mA
V
0.8
-1
1
mA
Dynamic Characteristics
Prop Delay Bus-to-Bus
Bus to Busf
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tPHL, tPLH
ns
Document Number: 72073
S-03422—Rev. A, 03-Mar-03
DG2303
New Product
Vishay Siliconix
SPECIFICATIONS (V+ = 5.0 V)
Test Conditions
Otherwise Unless Specified
Parameter
Symbol
Limits
-40 to 85_C
Minb
Typc
V+ = 1.65 V to 5.5 V, VIN = VIH or VILe
Tempa
VLD = 2 x V+, V+ = 1.65 V to 1.95 V (Figure 1 and 2)
Full
4.2
VLD = 2 x V+, V+ = 2.3 V to 2.7 V (Figure 1 and 2)
Full
3.3
VLD = 2 x V+, V+ = 3.0 V to 3.6 V (Figure 1 and 2)
Full
2.6
VLD = 2 x V+, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
Full
1.8
VLD = 0 V, V+ = 1.65 V to 1.95 V (Figure 1 and 2)
Full
4.4
VLD = 0 V, V+ = 2.3 V to 2.7 V (Figure 1 and 2)
Full
3.3
VLD = 0 V, V+ = 3.0 V to 3.6 V (Figure 1 and 2)
Full
2.7
VLD = 0 V, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
Full
2.0
VLD = 2 x V+, V+ = 1.65 V to 1.95 V (Figure 1 and 2)
Full
14.3
VLD = 2 x V+, V+ = 2.3 V to 2.7 V (Figure 1 and 2)
Full
10.5
VLD = 2 x V+, V+ = 3.0 V to 3.6 V (Figure 1 and 2)
Full
8.6
VLD = 2 x V+, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
Full
7.4
VLD = 0 V, V+ = 1.65 V to 1.95 V (Figure 1 and 2)
Full
10.7
VLD = 0 V, V+ = 2.3 V to 2.7 V (Figure 1 and 2)
Full
9.6
VLD = 0 V, V+ = 3.0 V to 3.6 V (Figure 1 and 2)
Full
8.7
7.5
Maxb
Unit
Dynamic Characteristics
tPZL
Output Enable Timed
tPZH
tPLZ
Output Disable Timed
tPHZ
ns
ns
VLD = 0 V, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
Full
Charge Injectiond
QINJ
CL = 1 nF, VGEN = 0 V, RGEN = 0 W, (Figure 3)
Room
0.5
Off Isolationd
OIRR
RL = 50 W, CL = 5 pF, f = 10 MHz
Room
-50
dB
Insertion Lossd
Loss
RL = 50 W
Room
>200
MHz
4
Input Capacitanced
Cin
Room
Channel-Off Capacitanced
C(off)
Room
9
Channel-On Capacitanced
CON
Room
20
VOE = 0 or V+,
V+ f = 1 MHz
pC
pF
p
Power Supply
Power Supply Range
V+
Power Supply Current
I+
1.65
VOE = 0 or V+
5.5
V
1.0
mA
Notes:
a.
b.
c.
d.
e.
f.
Room = 25°C, Full = as determined by the operating suffix.
The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
Typical values are for design aid only, not guaranteed nor subject to production testing.
Guarantee by design, nor subjected to production test.
VIN = input voltage to perform proper function.
Guaranteed by design and not production tested. The bus switch propagation delay is a function of the RC time constant contributed by the on-resistance and
the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch.
Document Number: 72073
S-03422—Rev. A, 03-Mar-03
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DG2303
New Product
Vishay Siliconix
AC LOADING AND WAVEFORMS
VLD
Ra =
500 W
A
SWITCH
INPUT
B
SWITCH
OUTPUT
Rb =
500 W
CL
LOGIC
INPUT
OE
CL =
50 pF
Input driven by 50-W source terminated in 50 W
CL includes load and stray capacitance
Input PRR = 1.0 MHz, tW = 50 ns
Figure 1. AC Test Circuit
tf = 2.5 ns
tr = 2.5 ns
V+
90%
Switch
Input
tr = 2.5 ns
tf = 2.5 ns
90%
1.5 V
90%
Logic
Input
1.5 V
1.5 V
1.5 V
10%
10%
10%
tw
tPLH
1.5 V
GND
tPLZ
tPHL
VOH
Output
10%
tPZL
GND
V+
90%
VLd
2
1.5 V
Output
VOL + 0.3 V
VOL
1.5 V
tPZH
tPHZ
VOH
VOL
VOH -0.3 V
Output
1.5 V
0V
Figure 2. AC Waveforms
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Document Number: 72073
S-03422—Rev. A, 03-Mar-03
DG2303
New Product
Vishay Siliconix
TEST CIRCUITS
V+
Rgen
DVOUT
V+
B
VOUT
A
VOUT
+
Vgen
OE
IN
CL = 0.1 nF
On
Off
On
GND
Q = DVOUT x CL
VIN = 0 - V+
IN depends on switch configuration: input polarity
determined by sense of switch.
Figure 3. Charge Injection
V+
10 nF
V+
A
OE
VIN
B
RL
VB
Off Isolation + 20 log V
A
GND
Analyzer
Figure 4. Off-Isolation
V+
10 nF
V+
B
Meter
OE
VIN
A
HP4192A
Impedance
Analyzer
or Equivalent
GND
f = 1 MHz
FIGURE 5. Channel Off/On Capacitance
Document Number: 72073
S-03422—Rev. A, 03-Mar-03
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