Maxim DG425C/D Improved low-power, cmos analog switches with latch Datasheet

19-0137; Rev 1; 3/94
Improved Low-Power,
CMOS Analog Switches with Latches
______________________New Features
♦ Plug-In Upgrades for Industry-Standard
DG421/DG423/DG425
♦ Improved r(DS)ON Match Between Channels (3Ω max)
♦ Guaranteed rFLAT(ON) Over Signal Range (4Ω max)
♦ Improved Charge Injection (15pC max)
♦ Improved Off Leakage Current Over Temperature
(<5nA at +85°C)
♦ Withstands Electrostatic Discharge (2000V min)
per Method 3015.7
_______________________Applications
Sample-and-Hold Circuits
Fax Machines
Battery-Operated Systems
Guidance and Control Systems
Audio Signal Routing
Modems
Test Equipment
PBX, PABX
Military Radios
Communication Systems
__________________Existing Features
♦ Low rDS(ON) (35Ω max)
♦ Single-Supply Operation +10V to +30V
Bipolar-Supply Operation ±4.5V to ±20V
♦ Low Power Consumption (35µW max)
♦ Rail-to-Rail Signal Handling Capability
♦ TTL/CMOS-Logic Compatible
______________Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
DG421CJ
0°C to +70°C
16 Plastic DIP
DG421CY
0°C to +70°C
16 SO
DG421C/D
0°C to +70°C
Dice*
DG421DJ
-40°C to +85°C
16 Plastic DIP
DG421DY
-40°C to +85°C
16 SO
DG421DK
-40°C to +85°C
16 CERDIP
DG421AK
-55°C to +125°C
16 CERDIP**
Ordering Information continued at end of data sheet.
* Contact factory for dice specifications.
**Contact factory for availability and processing to MIL-STD-883B.
__Functional Diagrams/Truth Tables
_________________Pin Configurations
TOP VIEW
S1
D1
WR
CK
IN1
D
D
RS
S2
DG421
CK
IN2
R
R
Q
D2
TWO SPST SWITCHES
PER PACKAGE
16 S1
15 IN1
DG421 TRUTH TABLE
N.C. 3
WR RS IN
SWITCH
N.C. 4
Off
On
N.C. 5
12 V L
N.C. 6
11 V+
0
Q
D1 1
WR 2
1
0
1
LOGIC "O" ≤ 0.8V
LOGIC "1" ≥ 2.4V
SWITCHES SHOWN FOR
LOGIC "1" INPUT
Functional Diagrams/Truth Tables continued at end of data sheet.
14 V-
DG421
RS 7
D2 8
13 GND
10 IN2
9
S2
DIP
N.C. = No Internal Connection
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
Call toll free 1-800-998-8800 for free samples or literature.
1
DG421/DG423/DG425
_______________General Description
Maxim’s redesigned DG421/DG423/DG425 monolithic
analog switches now feature guaranteed on-resistance
matching (3Ω max) between switches and on-resistance
flatness over the signal range (4Ω max). These low onresistance switches (20Ω typ) conduct equally well in both
directions. They guarantee a low charge injection of 15pC
maximum and an ESD tolerance of 2000V minimum per
Method 3015.7. Off leakage current over temperature has
also been reduced (less than 5nA at +85°C).
The DG421/DG423/DG425 are precision, dual CMOS
switches with latchable logic inputs that simplify interfacing with microprocessors (µPs). The single-pole/singlethrow DG421 and double-pole/single-throw DG425 are
normally open dual switches. The dual, singlepole/double-throw DG423 has two normally open and
two normally closed switches. Fast switching times
(175ns for t ON and 145ns for t OFF ) and low power
consumption (35µW max) make these parts ideal for
battery-powered applications requiring µP-compatible
switches. Operation is from a single +10V to +30V supply,
or bipolar ±4.5V to ±20V supplies. Fabricated with the
same 44V silicon-gate process, these switches have
rail-to-rail signal handling capabilities.
DG421/DG423/DG425
Improved Low-Power,
CMOS Analog Switches with Latches
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to VV+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+ + 0.3V)
Digital Inputs, VS, VD (Note 1) . . . . . . . . . . . . . . (V- - 2V) to (V+ + 2V)
Current (any terminal, except S or D) .................................30mA
Continuous Current, S or D .................................................20mA
Peak Current, S or D (pulsed at 1ms, 10% duty cycle max)...100mA
Continuous Power Dissipation (TA = +70°C)
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C) . . .842mW
20-Pin PLCC (derate 10.00mW/°C above +70°C) . . . . . 800mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C) . . . 800mW
Operating Temperature Ranges
DG42_C_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
DG42_D_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
DG42_A_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature Ranges
DG42_C_/DG42_D_ . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
DG42_A_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (soldering, 10sec). . . . . . . . . . . . . . . . . . . . +300°C
Note 1: Signals on S, D, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward current to maximum current ratings.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 15V, V- = -15V, VL = +5V, GND = 0V, VINH = +2.4V, VINL = +0.8V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
DG42_C, DG42_D
MIN TYP MAX
(Note 2)
MIN
DG42_A
TYP MAX
(Note 2)
UNITS
SWITCH
Analog Signal Range
Drain-Source
On-Resistance
rDS(ON)
On-Resistance Match
Between Channels
(Note 4)
∆rDS(ON)
On-Resistance
Flatness (Note 4)
rFLAT(ON)
Source-Off
Leakage Current
(Note 5)
IS(OFF)
Drain-Off
Leakage Current
(Note 5)
ID(OFF)
Drain-On
Leakage Current
(Note 5)
2
VANALOG
ID(ON)
(Note 3)
V+ = 13.5V,
V- = -13.5V,
IS = -10mA,
VD = ±10V
-15
TA = +25°C
15
20
-15
45
15
20
V
35
Ω
TA = TMIN to TMAX
45
45
V+ = 16.5V,
V- = -16.5V,
IS = -10mA,
VD = ±10V
TA = +25°C
3
3
TA = TMIN to TMAX
4
4
V+ = 15V,
V- = -15V,
IS = -10mA,
VD = ±5V
TA = +25°C
4
4
TA = TMIN to TMAX
5
5
V+ = 16.5V,
V- = -16.5V,
VD = ±15.5V,
VS = m 15.5V
TA = +25°C
V+ = 16.5V,
V- = -16.5V,
VD = ±15.5V,
VS = m 15.5V
TA = +25°C
V+ = 16.5V,
V- = -16.5V,
VD = ±15.5V,
VS = ±15.5V
TA = +25°C
-1.0
TA = TMIN to TMAX
-10
Ω
Ω
-0.50 -0.01
0.50
-0.25 -0.01
0.25
nA
TA = TMIN to TMAX
-5
5
-0.50 -0.01
0.50
-10
-0.25 -0.01
10
0.25
nA
TA = TMIN to TMAX
-5
5
-0.04
1.0
-10
-0.40 -0.04
10
0.40
nA
10
-20
_______________________________________________________________________________________
20
Improved Low-Power,
CMOS Analog Switches with Latches
(V+ = 15V, V- = -15V, VL = +5V, GND = 0V, VINH = +2.4V, VINL = +0.8V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
INPUT
Input Current with Input Voltage High
Input Current with Input Voltage Low
SUPPLY
Power Supply Range
Positive Supply Current
Negative Supply Current
Logic Supply Current
Ground Current
SYMBOL
IINH
IINL
V+, VI+
I-
IL
IGND
CONDITIONS
IN = 2.4V, all others = 0.8V
IN = 0.8V, all others = 2.4V
(Note 3)
All channels on or off,
V+ = 16.5V, V- = -16.5V,
VIN = 0V or 5V
All channels on or off,
V+ = 16.5V, V- = -16.5V,
VIN = 0V or 5V
All channels on or off,
V+ = 16.5V, V- = -16.5V,
VIN = 0V or 5V
All channels on or off,
V+ = 16.5V, V- = -16.5V,
VIN = 0V or 5V
MIN
-0.50
-0.50
TYP MAX
(Note 2)
0.005
0.005
±4.5
TA = +25°C
-1.0
TA = TMIN to TMAX
-5.0
TA = +25°C
-1.0
TA = TMIN to TMAX
-5.0
TA = +25°C
-1.0
TA = TMIN to TMAX
-5.0
TA = +25°C
-1.0
TA = TMIN to TMAX
-5.0
0.01
UNITS
0.50
0.50
µA
µA
±20
V
1.0
µA
5.0
-0.01
1.0
µA
5.0
-0.01
1.0
µA
5.0
-0.01
1.0
µA
5.0
DYNAMIC
Turn-On Time
tON
Figure 2
Turn-Off Time
tOFF
Figure 2
tWW
tDW
Latch Timing
VS = ±10V,
RL = 300Ω,
CL = 35pF,
Figure 3
tWD
Break-Before-Make Interval (Note 3)
Charge Injection (Note 3)
Off-Isolation Rejection Ratio
(Note 6)
TA = +25°C
TA = -55°C to +125°C
TA = +25°C
TA = -55°C to +125°C
TA = +25°C
TA = -55°C to +125°C
TA = +25°C
150
200
200
100
100
60
100
5
250
300
200
ns
ns
ns
tD
DG423, Figure 4
Q
CL = 10nF, VG = 0V,
RG = 0Ω, Figure 5
TA = +25°C
10
RL = 100Ω, CL = 5pF,
f = 1MHz, Figure 6
TA = +25°C
72
dB
RL = 50Ω, CL = 5pF,
f = 1MHz, Figure 7
TA = +25°C
90
dB
f = 1MHz, Figure 8
f = 1MHz, Figure 8
f = 1MHz, Figure 9
f = 1MHz, Figure 9
TA = +25°C
TA = +25°C
TA = +25°C
TA = +25°C
12
12
39
39
pF
pF
pF
pF
OIRR
Crosstalk (Note 7)
Drain-Off Capacitance
Source-Off Capacitance
Drain-On Capacitance
Source-On Capacitance
TA = +25°C
TA = TMIN to TMAX
CD(OFF)
CS(OFF)
CD(ON)
CS(ON)
25
ns
15
pC
Note 2: Typical values are for design aid only, are not guaranteed, and are not subject to production testing. The algebraic convention,
where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet.
Note 3: Guaranteed by design.
Note 4: On-resistance match between channels and flatness are guaranteed only with bipolar-supply operation. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured at the extremes of the specified analog signal range.
Note 5: Leakage parameters IS(OFF), ID(OFF), and ID(ON) are 100% tested at the maximum rated hot temperature and guaranteed by
correlation at +25°C.
Note 6: Off-Isolation Rejection Ratio = 20log (VD/VS), VD = output, VS = input to off switch.
Note 7: Between any two switches.
_______________________________________________________________________________________
3
DG421/DG423/DG425
ELECTRICAL CHARACTERISTICS (continued)
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
30
A
30
B
25
20
C
20
100
rDS (ON) (Ω)
35
V- = 0V
120
TA = +125°C
TA = +85°C
TA = +25°C
25
rDS (ON) (Ω)
15
V+ = 5V
80
60
TA = -55°C
D
15
V+ = 10V
40
10
10
V+ = 15V
V+ = 15V, V- = -15V
5
-10
10
0
20
-10
-20
10
0
0
20
5
10
15
VD (V)
VD (V)
VD (V)
ON-RESISTANCE vs. VD AND
TEMPERATURE (SINGLE SUPPLY)
OFF LEAKAGE CURRENTS vs.
TEMPERATURE
ON LEAKAGE CURRENTS vs.
TEMPERATURE
100
MAX401-4
70
60
V+ = 16.5V
V- = -16.5V
VD = ±15V
VS = ±15V
10
OFF LEAKAGE (nA)
TA = +125°C
50
TA = +85°C
40
TA = +25°C
30
20
100
MAX401-5
-20
V+ = 20V
20
5
V+ = 16.5V
V- = -16.5V
VD = ±15V
VS = ±15V
10
ON LEAKAGE (nA)
rDS (ON) (Ω)
40
35
1
0.1
0.01
20
MAX401-6
45
V+ = 5V, V- = -5V
V+ = 10V, V- = -10V
V+ = 15V, V- = -15V
V+ = 20V, V- = -20V
140
MAX401-2
A:
B:
C:
D:
50
MAX401-1
55
ON-RESISTANCE vs. VD
(SINGLE SUPPLY)
ON-RESISTANCE vs. VD AND
TEMPERATURE (DUAL SUPPLIES)
MAX401-3
ON-RESISTANCE vs. VD
(DUAL-SUPPLIES)
rDS (ON) (Ω)
1
0.1
0.01
0.001
0.001
V+ = 12V, V- = 0V
10
0.0001
0.0001
0
5
15
10
20
-75
125
25
VD (V)
-75
SUPPLY CURRENT vs.
TEMPERATURE
10
20
1
I+, I-, IL (µA)
40
0
-20
-40
MAX401-8
100
MAX401-7
60
25
TEMPERATURE (°C)
TEMPERATURE (°C)
CHARGE INJECTION vs.
ANALOG VOLTAGE
Q (pC)
DG421/DG423/DG425
Improved Low-Power,
CMOS Analog Switches with Latches
I+ at V+ = 16.5V
0.1
I- at V- = -16.5V
0.01
IL at VL = 5V
0.001
V+ = 15V, V- = -15V
-60
0.0001
-20
-10
0
VD (V)
4
10
20
-75
25
TEMPERATURE (°C)
_______________________________________________________________________________________
125
125
Improved Low-Power,
CMOS Analog Switches with Latches
__________Applications Information
Operation with Supply Voltages
Other Than ±15V
DG421
PIN
NAME
1, 8
D1, D2
––—––
WR
2
3, 4, 5, 6
FUNCTION
Drain Terminals
Write Select
7
N.C.
––—––
RS
No Internal Connection
9, 16
S1, S2
10, 15
IN1, IN2
11
V+
Positive Supply
12
VL
Logic Supply
13
GND
14
V-
Reset Select
The DG421/DG423/DG425 switches operate with ±4.5V
to ±20V bipolar supplies or with a +10V to +30V single
supply. In either case, analog signals ranging from V+
to V- can be switched. The Typical Operating
Characteristics graphs illustrate typical analog-signal
and supply-voltage on-resistance variations. The usual
on-resistance temperature coefficient is 0.5%/°C (typ).
Source Terminals
Logic Inputs
These devices operate with a single positive supply or
with bipolar supplies. They maintain TTL compatibility
with supplies anywhere in the ±4.5V to ±20V range as
long as VL = +5V. If VL is connected to V+ or another
supply at voltages other than +5V, the devices will
operate at CMOS-logic-level inputs.
Input Control
Ground
Negative Supply
Overvoltage Protection
DG423/DG425
DIP
PLCC
NAME
1, 8, 3, 6
2, 10, 4, 8
Drain Terminals
2
3
D1-D4
––—––
WR
Source Terminals
16, 9, 4, 5 20, 12, 5, 7
FUNCTION
Write Select
7
9
S1-S4
––—––
RS
15, 10
19, 13
IN1, IN2
11
14
V+
Positive Supply
12
15
VL
Logic Supply
—
1, 6, 11, 16
N.C.
14
18
V-
13
17
GND
Resets Select
Input Control
No Internal Connection
Proper power-supply sequencing is recommended for
all CMOS devices. Do not exceed the absolute maximum ratings because stresses beyond the listed ratings may cause permanent damage to the devices.
Always sequence V+ on first, followed by VL, V-, and
logic inputs. If power-supply sequencing is not possible, add two small, external signal diodes in series with
supply pins for overvoltage protection (Figure 1).
Adding diodes reduces the analog signal range to 1V
below V+ and 1V above V-, without affecting low switch
resistance and low leakage characteristics. Device
operation is unchanged, and the difference between V+
and V- should not exceed +44V.
Negative Supply
Ground
V+
S
D
Vg
V-
Figure 1. Overvoltage Protection Using External Blocking Diodes
_______________________________________________________________________________________
5
DG421/DG423/DG425
___________________Pin Descriptions
DG421/DG423/DG425
Improved Low-Power,
CMOS Analog Switches with Latches
______________________________________________Timing Diagrams/Test Circuits
VOUT is the steady-state output with the switch on. Feedthrough via switch capacitance may result in spikes at the
leading and trailing edge of the output waveform.
LOGIC
INPUT
tR < 20ns
tF < 20ns
3V
50%
0V
VD = 10V for tON
VD = -10V for tOFF
tOFF
VOUT
SWITCH
OUTPUT
0V
+5V
+15V
VL
V+
S
D
DG421
DG423
DG425
SWITCH OUTPUT
VOUT
RL
GND
LOGIC
INPUT
tON
0.9 x VOUT
-VOUT
V-
-15V
*VD = 10V for tON, VD = -10V for tOFF
VOUT = VD
REPEAT TEST FOR IN2 AND S2.
NOTE: LOGIC INPUT WAVEFORM IS INVERTED FOR
SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE.
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 2. Switching Time
3V
WR
1.5V
0
tWW
tDW
3V
tWD
2.0V
IN
0.8V
0
3V
RS
1.5V
0
SWITCH VOUT
0
OUTPUT
tRS
tOFF(RS)
0.8 x VOUT
Figure 3. Latch Timing
6
CL
IN
0.9 x VOUT
_______________________________________________________________________________________
R
L
( RL + rDS(ON)
)
Improved Low-Power,
CMOS Analog Switches with Latches
3V
LOGIC
INPUT
+5V
DG423
0V
D
0.9 x VOUT
0V
VOUT1
VOUT2
S
IN
WR
LOGIC
INPUT
RL2
300Ω
GND
CL2
35pF
RL1
300Ω
CL1
35pF
V-
0.9 x VOUT
VOUT2
SWITCH
OUTPUT 2
V+
S
VL RS
D
VD = 10V
VD = 10V
VOUT1
SWITCH
OUTPUT 1
+15V
50%
-15V
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
0V
tD
RL = 1000Ω
CL = 35pF
tD
Figure 4. DG423 Break-Before-Make Interval
+5V
∆VOUT
RS VL
Rg
VOUT
IN
0FF
0N
+15V
DG421
DG423
DG425
V+
S
D
Vg
0FF
VOUT
CL
10nF
GND WR
IN
V-
-15V
Q = ∆VOUT x CL
IN DEPENDENT ON SWITCH CONFIGURATION.
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
VIN = 3V
Figure 5. Charge Injection
10nF
SIGNAL GENERATOR
D
+15V
+5V
V+
RS VL
DG421
DG423
DG425
VS
IN
VD
NETWORK
ANALYZER
0V or 2.4V
S
GND
WR
V-
RL
-15V
10nF
Figure 6 . Off-Isolation Rejection Ratio
_______________________________________________________________________________________
7
DG421/DG423/DG425
_________________________________Timing Diagrams/Test Circuits (continued)
DG421/DG423/DG425
Improved Low-Power,
CMOS Analog Switches with Latches
_________________________________Timing Diagrams/Test Circuits (continued)
+15V
10nF
V+
SIGNAL GENERATOR
D
+5V
RS
VL
IN
0V or 2.4V
0V or 2.4V
D
GND WR
RL
50Ω
S
IN
S
NETWORK
ANALYZER
DG421
DG423
DG425
N.C.
V-15V
10nF
Figure 7. Crosstalk
+15V
10nF
V+
+5V
RS
D
VL
CAPACITANCE
METER
IN
S
V+
+5V
RS
D
DG421
DG423
DG425
VL
CAPACITANCE
METER
IN
S
GND WR
Figure 8. Drain/Source-Off Capacitance
GND WR
V-
-15V
8
0V or 2.4V
+15V
10nF
DG421
DG423
DG425
10nF
V-
-15V
Figure 9. Drain/Source-On Capacitance
_______________________________________________________________________________________
10nF
0V or 2.4V
Improved Low-Power,
CMOS Analog Switches with Latches
15 IN1
D3 3
14 V-
DG423
DG425
S3
5
D1
N.C.
S1
IN1
20
19
13 GND
12 V L
D4 6
11 V+
RS 7
10 IN2
D2 8
S2
9
DG423
DG425
18
V-
17
GND
16
N.C.
N.C.
6
S4
7
15
VL
D4
8
14
V+
DIP
9
10
D2
S4 5
4
1
RS
S3 4
D3
2
11
12
13
IN2
WR 2
3
S2
16 S1
N.C.
D1 1
WR
TOP VIEW
PLCC
N.C. = No Internal Connection
_____________________________Functional Diagrams/Truth Tables (continued)
S1
S3
WR
IN1
CK
D1
S1
D1
D3
S3
D3
WR
Q
S2
S4
DG423
CK
Q
DG425
IN2
D R Q
D R Q
CK
S2
S4
D2
D4
Q
D R
RS
RS
IN2
CK
IN1
D R Q
D2
D4
TWO SPDT SWITCHES PER PACKAGE
TWO DPST SWITCHES PER PACKAGE
DG423 TRUTH TABLE
DG425 TRUTH TABLE
WR
0
RS
IN
SWITCH 1, 2
SWITCH 3, 4
1
0
1
Off
On
On
Off
LOGIC "O" ≤ 0.8V
LOGIC "1" ≥ 2.4V
IN
WR RS IN SWITCH
0
LATCH OPERATION TRUTH TABLE
RS WR
X
1
X
1
X
X
0
0
1
0
1
Off
On
LOGIC "O" ≤ 0.8V
LOGIC "1" ≥ 2.4V
LATCH/SWITCH X
Latch operation transparent.
Control data latched in.
Switches on or off as selected by last IN.
X
X
All latches reset. Switches on or off as
when IN = 0, WR = 0, RS = 1.
_______________________________________________________________________________________
9
DG421/DG423/DG425
_____________________________________________Pin Configurations (continued)
DG421/DG423/DG425
Improved Low-Power,
CMOS Analog Switches with Latches
_Ordering Information (continued)
PART
TEMP. RANGE
DG423CJ
0°C to +70°C
16 Plastic DIP
PIN-PACKAGE
DG423CY
0°C to +70°C
16 SO
DG423C/D
0°C to +70°C
Dice*
DG423DJ
-40°C to +85°C
16 Plastic DIP
DG423DY
-40°C to +85°C
16 SO
DG423DN
-40°C to +85°C
20 PLCC
DG423DK
-40°C to +85°C
16 CERDIP
DG423AK
-55°C to +125°C
16 CERDIP**
DG425CJ
0°C to +70°C
16 Plastic DIP
DG425CY
0°C to +70°C
16 SO
DG425C/D
0°C to +70°C
Dice*
DG425DJ
-40°C to +85°C
16 Plastic DIP
DG425DY
-40°C to +85°C
16 SO
DG425DN
-40°C to +85°C
20 PLCC
DG425DK
-40°C to +85°C
16 CERDIP
DG425AK
-55°C to +125°C
16 CERDIP**
* Contact factory for dice specifications.
**Contact factory for availability and processing to MIL-STD-883B.
___________________________________________________________Chip Topographies
DG421
DG421
WR
D1
DG423
DG423/DG425
S1
IN1
WR
N.C.
D1
S1
IN1
D3
V-
N.C.
GND
N.C.
V
VLL
V0.105"
S3
GND
(2.66mm)
S4
VL
VL
V+
D4
RS
RS
D2
S2
IN2
D2
0.082"
0.082"
(2.08mm)
(2.08mm)
TRANSISTOR COUNT: 100
SUBSTRATE CONNECTED TO V+
10
V+
N.C.
S2
IN2
TRANSISTOR COUNT: 100
SUBSTRATE CONNECTED TO V+
______________________________________________________________________________________
0.105"
(2.66mm)
Improved Low-Power,
CMOS Analog Switches with Latches
DIM
D1
A
A1
A2
A3
B
B1
C
D
D1
E
E1
e
eA
eB
L
α
E
E1
D
A3
A A2
L A1
INCHES
MAX
MIN
0.200
–
–
0.015
0.150
0.125
0.080
0.055
0.022
0.016
0.065
0.050
0.012
0.008
0.765
0.745
0.030
0.005
0.325
0.300
0.280
0.240
0.100 BSC
0.300 BSC
0.400
–
0.150
0.115
15˚
0˚
MILLIMETERS
MIN
MAX
–
5.08
0.38
–
3.18
3.81
1.40
2.03
0.41
0.56
1.27
1.65
0.20
0.30
18.92
19.43
0.13
0.76
7.62
8.26
6.10
7.11
2.54 BSC
7.62 BSC
–
10.16
2.92
3.81
0˚
15˚
21-587A
α
16-PIN PLASTIC
DUAL-IN-LINE
PACKAGE
C
e
B1
eA
B
eB
DIM
S1
S
E1
E
D
A
A
B
B1
C
D
E
E1
e
L
L1
Q
S
S1
α
INCHES
MAX
MIN
0.200
–
0.023
0.014
0.065
0.038
0.015
0.008
0.840
–
0.310
0.220
0.320
0.290
0.100 BSC
0.200
0.125
–
0.150
0.060
0.015
0.080
–
–
0.005
15˚
0˚
MILLIMETERS
MIN
MAX
–
5.08
0.36
0.58
0.97
1.65
0.20
0.38
–
21.34
5.59
7.87
7.37
8.13
2.54 BSC
3.18
5.08
3.81
–
0.38
1.52
–
2.03
0.13
–
0˚
15˚
21-590B
α
Q
L
L1
e
B1
B
C
16-PIN CERAMIC
DUAL-IN-LINE
PACKAGE
______________________________________________________________________________________
11
DG421/DG423/DG425
________________________________________________________Package Information
DG421/DG423/DG425
Improved Low-Power,
CMOS Analog Switches with Latches
___________________________________________Package Information (continued)
DIM
A2
C
e B1
D1 D
B
D2
A
A1
A2
A3
B
B1
C
D
D1
D2
D3
e
INCHES
MAX
MIN
0.180
0.165
0.110
0.100
0.156
0.145
–
0.020
0.021
0.013
0.032
0.026
0.011
0.009
0.395
0.385
0.355
0.350
0.330
0.290
0.200 REF
0.050 REF
MILLIMETERS
MIN
MAX
4.19
4.57
2.54
2.79
3.68
3.96
0.51
–
0.33
0.53
0.66
0.81
0.23
0.28
9.78
10.03
8.89
9.02
7.37
8.38
5.08 REF
1.27 REF
21-981A
A3
D3
A1
D1
A
D
20-PIN PLASTIC
LEADED CHIP
CARRIER
PACKAGE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1994 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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