VISHAY DG894

DG894
Vishay Siliconix
Component Video Selector
Component Video Switching:
RGB + SYNC, S-VHS, Y-C, etc.
Audio/Video Routing
Digital TV
ATE
I2C Bus Audio/Video Systems
SCART Video Switching
Wide Bandwidth: 200 MHz
Very Low Crosstalk: –70 dB at 5 MHz
CMOS Compatible
I2C Bus Compatible
Fast Switching—tON: <200 ns
Low rDS(on): 44 Single Supply Capability
Low Insertion Loss
Improved System Performance
Reduced Power Consumption
Easily Interfaced
Future System Expansion
via I2C Bus
The DG894 is a monolithic video selector designed for
switching a variety of component video signals. The low
on-resistance and low capacitance of the DG894 make it ideal
for video/audio signal routing. Switch control can be through
direct CMOS addressing or through the two-wire I2C bus.
The DG894 is built on the Vishay Siliconix proprietary
D/CMOS process that combines n-channel DMOS switching
FETs with low-power CMOS control logic and drivers.
Low-capacitance DMOS FETs are used to achieve high levels
of off isolation at low cost.
Dual-In-Line and SOIC
VDD
1
28
C0
Y1
2
27
Y0
C1
3
26
VDD
0
0
I2C
GND
4
25
COUT
0
1
I2C Bus Operation, Address A0 = “0”
Y2
5
24
YOUT
1
0
0
0
All switches off
1
0
0
1
Y0, C0
C2
6
23
SMO
1
0
1
0
Y1, C1
1
0
1
1
Y2, C2
VSS
7
ROUT
8
GOUT
Control Logic/Drivers
9
SMO
SEL
SDA
SCL
Function/Switch On
Bus Operation, Address A0 = “1”
22
SCL
1
1
0
0
R1, G1, B1, F1
21
SDA
1
1
0
1
R2, G2, B2, F2
SEL
1
1
1
0
R1, G1, B1, F1, Y1, C1
1
1
1
1
R2, G2, B2, F2, Y2, C2
20
BOUT
10
19
R1
FBOUT
11
18
G1
FB2
12
17
B1
R2
13
16
FB1
G2
14
15
B2
Temp Range
–40 to 85C
–40 to 85C
Package
Part Number
28-Pin Plastic DIP
DG894DJ
28-Pin Wide Body SOIC
DG894DW
Top View
Document Number: 70072
S-52433—Rev. D, 06-Sep-99
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DG894
Vishay Siliconix
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 19 V
Current (Any Terminal) Pulsed 1 ms, 10% Duty Cycle Max . . . . . . . . 40 mA
V+ to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 19 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 125C
V– to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to 0.3 V
Power Dissipation (Package)a
28-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 mW
28-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.3 V to (V+) +0.3 V
or 20 mA, whichever occurs first
Signal Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS –0.3 V to 8 V
or 20 mA, whichever occurs first
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Notes:
a. All leads welded or soldered to PC board.
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
Limits
–40 to 85C
VDD = 12 V, VSS = –5 V
VINH = 3 V, VINL = 1.5 Ve
Tempa
VDD = 12 V, VSS = GND
Full
0
4
VDD = 12 V, VSS = –5 V
Full
–2
2
Minc
Typb
Maxc
Unit
Analog Switch
Analog Signal Ranged
Drain-Source On-Resistance
Resistance Match
Between Channels
VANALOG
rDS(on)
Room
Full
44
51
Room
10
100
150
IS = –10 mA, VD = 0 V
DrDS(on)
Source Off Leakage Current
IS(off)
VS = 4 V, VD = 0 V
Room
Full
–10
–100
–0.05
10
100
Drain Off Leakage Current
ID(off)
VD = 4 V, VS = 0 V
Room
Full
–10
–100
–0.05
10
100
Total Switch On Leakage Current
ID(on)
VD = VS = 4 V
Room
Full
–10
–100
–0.07
10
100
3
2.55
V
W
nA
Input
Input Voltage High
VINH
Full
Input Voltage Low
VINL
Full
2.55
Input Threshold
Vth
Room
2.55
TCth
Full
–200
Temp Coefficient of
Input Threshold
Input Current
Output Voltage Low
IIN
VIN = GND or VDD
Room
Full
VOL
Pin 21, During Acknowledge,
IOL = 3 mA
Room
–1
–20
0.05
1.5
V
mV/
C
1
20
mA
0.4
V
Dynamic
Input Capacitanced
Cin
Pin 21, 22
Room
3
10
On State Input Capacitanced
CS(on)
VS = VD = 0 V
Room
10
15
Off State Input Capacitanced
CS(off)
VS = 0 V
Room
4
8
Off State Output Capacitanced
CD(off)
VD = 0 V
Room
4
8
BW
RL = 50 W , See Figure 1
Room
Turn On Time
tON
200
tOFF
RL = 1 kW , CL = 35 pF, 50% to 90%
VSS = –5 V, 0 V, VS = 3 V,
See Figure 1
Room
Turn Off Time
Room
180
RIN = 10 W , RL = 1 kW
MH See
S Figure
Fi
d 3
f = 5 MHz,
2 and
Bandwidthd
pF
F
200
500
ns
SCL Max Clock Frequency
FSCL(MAX)
Full
Component Crosstalk
XTALK(CO)
Room
–85
Channel Crosstalk
XTALK(CH)
Room
–85
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MHz
100
kHz
dB
Document Number: 70072
S-52433—Rev. D, 06-Sep-99
DG894
Vishay Siliconix
Test Conditions
Unless Otherwise Specified
Parameter
VDD = 12 V, VSS = –5 V
VINH = 3 V, VINL = 1.5 Ve
Symbol
Limits
–40 to 85C
Tempa
Minc
Typb
Maxc
3
4
8
10
Unit
Supply Voltage
Positive Supply Current
I+
Negative Supply Current
I–
Room
Full
All Control Inputs 0 V, 5 V
Room
Full
–8
–10
mA
–2.5
–3.0
Notes:
a. Room = 25C, Full = as determined by the operating temperature suffix.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Guaranteed by design, not subject to production test.
e. VIN = input voltage to perform proper function.
Purchase of Vishay Siliconix DG894 components conveys a license to use them in the I2C system as defined by Philips.
rDS(on) vs. Drain Voltage
V+ = 12 V
V– = –5 V
IS = –10 mA
180
160
140
120
100
85C
80
25C
60
–40C
40
rDS(on) vs. Drain Voltage
200
r DS(on)– Drain-Source On-Resistance ( )
r DS(on)– Drain-Source On-Resistance ( )
200
V+ = 12 V
V– = 0 V
IS = –10 mA
180
160
140
120
100
85C
80
25C
60
–40C
40
20
20
–4
–2
0
2
4
VD – Drain Voltage (V)
6
8
0
tON vs. Bipolar Supply Voltage
106
2
4
VD – Drain Voltage (V)
8
tOFF vs. Bipolar Supply Voltage
45.5
V– = –5 V
See Figure 1
85C
100
43.5
85C
V– = –5 V
See Figure 1
94
t OFF (ns)
t ON (ns)
6
88
41.5
25C
39.5
25C
82
–40C
37.5
–40C
76
35.5
10.8
11.2
Document Number: 70072
S-52433—Rev. D, 06-Sep-99
11.6
12.0
12.4
V+ – Positive Supply (V)
12.8
13.2
10.8
11.2
11.6
12.0
12.4
V+ – Positive Supply (V)
12.8
13.2
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DG894
Vishay Siliconix
tON vs. Unipolar Supply Voltage
tOFF vs. Unipolar Supply Voltage
57
108
V– = 0 V
See Figure 1
54
100
85C
92
t OFF (ns)
t ON (ns)
85C
V– = 0 V
See Figure 1
84
25C
51
48
25C
45
76
–40C
–40C
42
68
10.8
11.2
11.6
12.0
12.4
12.8
10.8
13.2
11.2
11.6
V+ – Positive Supply (V)
12.0
12.4
12.8
13.2
V+ – Positive Supply (V)
SDA Output Current vs. Supply Voltage
SDA Output Current vs. Temperature
10
12
V– = –5 V
10
V– = 0 V
8
V– = 0 V
8
Current (mA)
Current (mA)
VOL = 0.4 V
TA = 25C
6
Specification
Minimum Limit
4
V+= 12 V
VOL = 0.4 V
V– = –5 V
6
Specification
Minimum Limit
4
2
2
0
0
10.8
11.2
11.6
12.0
12.4
12.8
13.2
–40
–20
0
VSUPPLY (V)
Component Crosstalk
60
80
100
120
VDS = +12 V
VSS = –5 V
RIN = 10 RL = 1 k
See Figure 2
110
100
VDD = +12 V
VSS = –5 V
RIN = 10 RL = 1 k
See Figure 3
110
100
90
90
dB
dB
40
Channel Crosstalk
120
80
80
70
70
60
60
50
50
40
40
1
2
3
4
f – Frequency (MHz)
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20
Temperature (_C)
5
10
1
2
3
4
5
10
f – Frequency (MHz)
Document Number: 70072
S-52433—Rev. D, 06-Sep-99
DG894
Vishay Siliconix
+12 V
5V
V+
VS
D
S
Logic
Input
VO
Switch
Input
IN
RL
1 k
3V
GND
V–
50%
CL
35 pF
VS
90%
Switch
Output
0V
tON
–5 V
tOFF
CL (includes fixture and stray capacitance)
VO = VS
RL
RL + rDS(on)
FIGURE 1. Switching Time
B1
BOUT
FB1
YOUT
or
COUT
e.g., Y or C
e.g., Y1 or C1
R2
10 e.g., Y2 or C2
RL
1 k
10 FBOUT
B2
RL
1 k
G2
10 1 k
VOUT
XTALK(CO) 20 log 10 V
IN
1 k
VOUT
XTALK(CH) 20 log10 V
IN
FIGURE 2. Component Crosstalk
FIGURE 3. Channel Crosstalk
+12 V
C
V+
S
VS
D
VO
Rg = 75 RL
50 GND
V–
–5 V
FIGURE 4. Bandwidth
Document Number: 70072
S-52433—Rev. D, 06-Sep-99
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DG894
Vishay Siliconix
20
16
f a Data Sheet Test Conditions
Operating
Voltage
Area
14
12
10
8
6
4
V+ – Positive Supply Voltage (V)
18
2
–5.5 –5.0 –4.5 –4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5
0
–0.0
V– – Negative Supply Voltage (V)
FIGURE 5.
Symbol
Description
Y0, Y1, Y2
An analog channel input, typically luminance.
C0, C1, C2
An analog channel input, typically chrominance.
R1, R2, G1, G2, B1, B2, FB1, FB2
An analog channel input, typically “red”, “green”, “blue” or “fast blanking”, as appropriate.
GND
Analog and digital ground.
VDD
Positive supply voltagea
VSS
Negative supply voltage
YOUT , COUT
ROUT , GOUT , BOUT , FBOUT
An analog channel output, typically luminance or chrominance, as appropriate
An analog channel output, typically “red”, “green”, “blue” or “fast blanking”, as appropriate.
SMO
A low selects serial mode (I2C) operation. A high selects CMOS operation.
SDA
Serial data lineb
SCL
Serial clock lineb
SEL
CMOS control line or I2C addressc select line
Notes:
a. Both VDD pins (Pin 1 and Pin 26) must be connected for proper operation.
b. SDA and SCL pins become CMOS control inputs when SMO = High.
c. The SEL pin, in I2C bus operation (i.e., with SMO low), is the least significant bit of the device address. This allows two devices to operate on the same I2C
bus, yet retain independent control.
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Document Number: 70072
S-52433—Rev. D, 06-Sep-99
DG894
Vishay Siliconix
Left1
Right1
–5 V
+12 V
VSS
VDD
Y1
YOUT
C1
COUT
Left
Right
R1
R1
75 G1
75 B1
75 SYNC1
75 Left2
G1
B1
FB1
+5 V
Y2
C2
Right2
75 R2
75 G2
R2
ROUT
G2
GOUT
B2
BOUT
ROUT
GOUT
75 B2
75 SYNC2
FB2
BOUT
FBOUT
SYNCOUT
75 CLC114
+5 V
SMO
–5 V
SEL
Control Logic
SDA
SCL
GND
Channel
Select
FIGURE 6.
Document Number: 70072
S-52433—Rev. D, 06-Sep-99
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DG894
Vishay Siliconix
I2C Bus Operation—RGB Switching
Figure 6 shows an inexpensive RGB + stereo selector. The
two audio channels are switched via the C, Y terminals. The
CLC114 quad video buffer drives four 75- output lines.
–
number of devices on bus
–
total bus capacitance
–
supply voltage (Figure 7).
Data Transfer on the I@C Bus
Characteristics of the I@C Bus
The I@C Bus interface is ideally suited for communication
between different ICs or modules. Its salient features are:
If the bus is not being used, both SDA and SCL lines must be
left high.
D Two wire bidirectional serial bus
Every byte put onto the SDA line should be eight bits long
(MSB first), followed by an acknowledge bit, which is
generated by the receiving device.
–
Serial data (SDA) and serial clock (SCL) lines
D Multi-master system (built-in arbitration for multi-master
systems)
Each data transfer is initiated with a start condition and ended
with a stop condition. The first byte after a start condition is
always the address byte. If this is the device’s own address,
the device will generate an acknowledge by pulling the SDA
line low during the ninth clock pulse, then accept the data in
subsequent bytes until another start or stop condition is
detected.
D Devices have independent clocks
D Master and slave devices can be receivers and/or
transmitters.
D Each device has a unique address.
D Maximum bus clock rate of 100 kHz.
The eight bit of the address byte is the read/write bit (high =
read from addressed device, low = write to the addressed
device) so, for the DG894, the address is only considered valid
if the R/W bit is low.
D Any number of interfaces may be connected to the bus
–
Limited only by total capacitance of 400 pF
–
Each pin on bus limited to 10-pF capacitance
–
Input levels:
VIL max = 1.5 V (fixed supply operation)
VIH min = 3 V (fixed supply operation)
VIL max = 0.3 VDD (wide range supply operation)
VIH min = 0.7 VDD (wide range supply operation)
Data bytes are always acknowledged during the ninth clock
pulse by the addressed device. Note that during the
acknowledge period the transmitting device must leave the
SDA line high.
Premature termination of the data transfer is allowed by
generating a stop condition at any time. When this happens,
the DG894 will remain in the state defined by the last complete
data byte transmitted.
System Configuration
Rp value depends on:
Rp
Rp
SCL
SDA
Master
Transmitter/
Receiver
Master
Transmitter
Peripheral
Device
Peripheral
Device
FIGURE 7.
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Document Number: 70072
S-52433—Rev. D, 06-Sep-99
DG894
Vishay Siliconix
SDA
SDA
SCL
SCL
STA
STO
Start Condition
Stop Condition
FIGURE 8. START and STOP Conditions
SDA
MSB
acknowledgement
signal from receiver
byte complete, interrupt within receiver
acknowledgement
signal from receiver
clock line held low while interrupts are serviced
SCL
1
2
7
8
STA
9
ACK
1
Start Condition
2
3-8
9
ACK
STO
Stop
Condition
FIGURE 9. Data Transfer on the I2C Bus
Timing Specifications of the IC Bus
IC Bus Protocol
IC bus load conditions for timing specifications are as follows:
The DG894 is a slave receiver type of IC interface and has
four allocated addresses, two of which are user programmable
through the SEL pin. Additional addresses may be obtained by
a metal mask option for users requiring more than two DG894s
on the same IC bus. Contact Vishay Siliconix marketing for
further information.
4 kW pull-up resistors to +5 V; 200 pF capacitor to
ground. All values are referred to VIH = 3 V, VIL = 1.5 V.
Parameter
SCL Clock Frequency
Bus Free Before Start
Symbol
Min
Max
Unit
fscl
–
100
kHz
tBUF
4.7
–
Start Condition Set-up Time
tSU;STA
4.7
–
Start Condition Hold Time
tHD;STA
4
–
SCL and SDA Low Period
tLOW
4.7
–
SCL and SDA High Period
tHIGH
4
–
SCL and SDA Rise Time
tr
–
1.0
SCL and SDA Fall Time
tf
–
0.3
Data Set-Up Time (WRITE)
tSU;DAT
0.25
–
Data Hold Time (WRITE)
tHD;DAT
0*
–
*A transmitter must internally provide at lease a hold time to bridge the
undefined region (max 300 ns) of the falling edge of the SCL.
Document Number: 70072
S-52433—Rev. D, 06-Sep-99
After the correct address has been sent, only one data byte is
needed to define the switch configuration. Subsequent data
put onto the bus will update the switches until a STOP
condition (or another START condition) signals that the device
is no longer being addressed. The switches will then remain in
their last configuration as long as power is maintained to the
chip.
ms
Power on Reset
A power on reset function is provided on the DG894 to turn all
switches off following power up if the IC mode is selected. In
the CMOS control mode, the switches are selected according
to the state of the control inputs.
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Vishay Siliconix
SDA
tBUF
tR
tF
tHD;STA
SCL
tLOW
tHD;STA
STO
tHIGH
tSU;DAT
STA
tSU;STA
tSU;STO
STA
tHD;DAT
STO
FIGURE 10.I2C Bus Timing Diagram
Minimum Bit Stream to Set Up DG894 Switches
STA
1
1
0
1
1
Address Byte
STA
A1
A0
R/W
ACK
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
STO
A0
R/W
ACK
X
X
X
D4
D3
D2
D1
D0
ACK
STO
Data Byte
= START CONDITION
= 0 (programmable to “1” with metal mask change)
= SEL. Address bit set by use (address is inverse of SEL logic level)
= READ/WRITE bit (must be “0”, only WRITE mode allowed for DG894)
= Acknowledge bit (“0”) generated by DG894
= 0 –– R2, G2, B2, and FB2 switches off
= 1 –– R2, G2, B2, and FB2 switches on
= 0 –– R1, G1, B1, and FB1 switches off
= 1 –– R1, G1, B1, and FB1 switches on
= 0 –– Y2, C2, switches off
= 1 –– Y2, C2, switches on
= 0 –– Y1, C1, switches off
= 1 –– Y1, C1, switches on
= 0 –– Y0 and C0 switches off
= 1 –– Y0 and C0 switches on
= STOP CONDITION
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Document Number: 70072
S-52433—Rev. D, 06-Sep-99