Power DI-69 15 w multi-output dc-dc converter Datasheet

Design Idea DI-69
DPA-Switch™ 15 W Multi-Output
DC-DC Converter
Application
Device
Power Output
Input Voltage
Output Voltage
Topology
VoIP Phone
DPA424P
15 W
36-75 VDC
5 V / 7.5 V / 20 V
Forward
Design Highlights
• Low component count
• Built-in accurate OV/UV with single resistor
programming
• High efficiency (88%) using synchronous rectification
• Multiple outputs with good cross-regulation
• Built-in output overload, open loop and thermal protection
• 400 kHz switching frequency
• No primary current sense resistor required
Operation
Resistor R1 programs the input under/over voltages to 33 V and
86 V. It also linearly reduces the maximum device duty cycle
(DCMAX) with increasing input voltage, helping to prevent core
saturation during transients.
Capacitor C1, C2 and L1 provide line filtering. Resistor
R2 programs the U1 current limit. The Q22 reflected gate
capacitance provides optimum reset for transformer T1.
Zener VR1 clamps the peak drain voltage to a safe level
during transient conditions.
Resistors R21, R22, C21 and MOSFETs Q21 and Q22 form
a capacitively coupled direct driven synchronous rectifier
for the main (5 V) output. Zener diode VR21 acts both as
a clamp and as a diode to quickly recharge the Q21 drive
capacitor C21. Resistor R23 holds Q21 off when no switching
signal is present.
The 20 V output is generated from a flyback winding on the
L2 inductor, which is rectified and filtered by diode D41 and
C41. Zener VR31 and diode D32 provide a pre-load on the
7.5 V output to enhance regulation at light load.
D41
BAV19WS
J1-1
36-75 VDC
L1
1 µH 2.5 A
1
D31
20CJQ060
8
+
3
DC
Input
Voltage
R1
619 kΩ
1%
Q22
Si4804
7
4
5
C2
1 µF
100 V
L
D
DPA-Switch
U1
DPA424P
CONTROL
VR1
SMBJ
150
RTN
J1-2
DI-69
S
7
6
X
C4
220 nF
R2
13.3 kΩ
1%
C31
100 µF
10 V
C25
C22-C24
R4 1 µF
100 µF 5 V
160 Ω 10 V
5
8
7
J2-3
5 V, 2.4 A
J2-2
2
D6
BAV
19WS
RTN
J2-1
C6
4.7 µF
20 V
U2
PC357N1T
C
F
J2-4
7.5 V, 0.4 A
Q21
VR21 D21
Si4804
SL13
15 V
R23
10 kΩ
T1
C1
1 µF
100 V
3
L2
16 µH 4 A
C21
2.2 nF
R21
10 Ω
R22
10 Ω
6
4
20 V, 10 mA
C41
4.7 µF, 35 V
VR31
D32
6.8 V IN4148
U2
R12
150 Ω
D11
BAV19WS
R3
1.0 Ω
C5
47 µF
10 V
R16
10.0 kΩ
1%
R11
10 kΩ
C11
2.2 µF
10 V
U3
LM431AIM3
C12
100 nF
R13
11 Ω
C13
68 nF
R14
1 kΩ
R15
10.0 kΩ
1%
PI-3799-082404
Figure 1. 15 W DC to DC Converter using DPA424P .
www.powerint.com
August 2004
DI-69
Key Design Points
• Zener VR1 safely limits the DRAIN voltage below
BVDSS.
• At zero load, maximum input voltage, the bias voltage
across C6 should be >8 V (12 V to 15 V under normal
conditions).
• The 5 V output is the regulated output. All other outputs
are derived from it. Therefore, tight transformer secondary
coupling and low PC board trace impedance from the 5
V output to the 7.5 V output are crucial to achieve good
cross-regulation.
• The transformer must reset completely under all line
and load conditions to prevent core saturation. The
gate capacitance of Q22 (with other parasitic circuit
capacitances), determines the minimum reset period. The
transformer core reset voltage also drives the secondary
synchronous rectifier Q22. Efficiency is maximized when
Q22 conduction period is maximized. This Q22 conduction
period can be extended by adding more capacitance (an R-C
snubber across the 5 V winding). The reset period should
be set to give as long a reset as possible when operating
at low-line (maximum duty cycle) while still guaranteeing
complete reset.
• Good layout practices should be followed:
- Locate C4, C5 and R3 close to U1 with grounds returned
to the SOURCE pin.
- Minimize the primary and secondary loop areas to reduce
parasitic leakage inductance.
- Locate D21 and Q22 return connections very close to each
other to provide best cross-regulation between 5 V and
7.5 V.
VOUT
5
7.5
7
Voltage
Range
(VDC)
36-72
36-72
36-72
Load
Cross-Regulation (%)
Range
(%) -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
20-100
0-100
100
Table 1. Worst Case Output Cross-Regulation - All Outputs Taken
from Minimum to Maximum Load.
TRANSFORMER PARAMETERS
Core Material
Ferroxcube P/N: PTS14/8-3F3, ungapped
Bobbin
8 pin P1408 surface mount B&B B-096 or
equivalent
Winding Details
Primary: 8T + 7T, 27 AWG,
5 V 4T, 4 x 28 AWG
7.5 V 2T, 4 x 28 AWG
Winding Order
(pin numbers)
Primary-1 (4-3), 7.5 V (7-8), 5 V (5-6)
Primary-2 (3-1)
Primary
Inductance
434 µH ±25% @ 100 kHz
Primary Resonant
3.8 MHz (minimum)
Frequency
Leakage
Inductance
1 µH (maximum)
Table 2. Transformer Design Parameters.
INDUCTOR PARAMETERS
Core Material
Bobbin
Winding Details
Winding Order
(pin numbers)
Inductance
Epcos N87, P/N: B65755-J-R87, Gap for
AL = 160 nH/T2
8 pin P1408 surface mount B&B B-096 or
equivalent
Bias 26T, 34 AWG
5 V 6T, 2 x 28 AWG
7.5 V 12T, 28 AWG
20 V 40T, 34 AWG
7.5 V (7-6), 5 V (8-5), 20 V (1-2), Bias (4-3)
Pin (5-8): 16 µH ±10% @ 100 kHz
Table 3. Inductor Design Parameters.
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are trademarks of Power Integrations. Copyright 2004, Power Integrations
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