DM54161,DM74161,DM74163 DM54161 DM74161 DM74163 Synchronous 4-Bit Counters Literature Number: SNOS240A DM54161/DM74161/DM74163 Synchronous 4-Bit Counters General Description e external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all low outputs. Low-to-high transitions at the clear input of the 163 are also permissible, regardless of the logic levels on the clock, enable, or load inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both countenable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. Highto-low-level transitions at the enable P or T inputs of the 161 through 163 may occur, regardless of the logic level on the clock. et These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The 161 and 163 are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flipflops clocked simultaneously so that the outputs change coincident with each other when so instructed by the countenable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable input. The clear function for the 161 is asynchronous; and a low level at the clear input sets all four of the flip-flop outputs low, regardless of the levels of clock, load, or enable inputs. The clear function for the 163 is synchronous; and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one Features Y Synchronously programmable Internal look-ahead for fast counting Carry output for n-bit cascading Synchronous counting Load control line Diode-clamped inputs bs ol Y Y Y Y Y Connection Diagram O Dual-In-Line Package TL/F/6551 – 1 Order Number DM54161J, DM54161W, DM74161N or DM74163N See NS Package Number J16A, N16E or W16A C1995 National Semiconductor Corporation TL/F/6551 RRD-B30M105/Printed in U. S. A. DM54161/DM74161/DM74163 Synchronous 4-Bit Counters October 1992 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54 DM74 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions DM54161 Parameter Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 6) 0 tW Pulse Width (Note 6) Clock 25 Clear 20 Setup Time (Note 6) Data 20 Enable P 34 Load 25 2 2 16 25 Clear (Note 5) tH Hold Time (Note 6) TA Free Air Operating Temperature V 0.8 V e 0.8 b 0.8 Units V b 0.8 0 mA 16 mA 25 MHz 25 ns 20 20 34 ns 25 bs ol tSU DM74161 and 163 Min et Symbol 20 20 0 0 b 55 125 0 ns 70 §C Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 1) Max Units b 1.5 V Input Clamp Voltage VCC e Min, II e b12 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min, VIL e Max II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max Enable T 80 VI e 2.4V Clock 80 Low Level Input Current VCC e Max Enable T b 3.2 Clock b 3.2 Others b 1.6 O VI IIL 2.4 0.2 Others VI e 0.4V 2 3.4 V 0.4 V 1 mA mA 40 mA Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) (Continued) Symbol IOS ICCH ICCL Parameter Conditions Typ (Note 1) Min Max Short Circuit Output Current VCC e Max (Note 2) DM54 b 20 b 57 DM74 b 20 b 57 Supply Current with Outputs High VCC e Max (Note 3) DM54 Supply Current with Outputs Low VCC e Max (Note 4) DM54 85 DM74 59 94 63 101 91 DM74 Units mA mA mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time. Note 3: ICCH is measured with the LOAD high, then again with the LOAD low, with all inputs high and all outputs open. Note 4: ICCL is measured with the CLOCK high, then again with the CLOCK input low, with all inputs low and all outputs open. Note 5: Applies to 163 which has synchronous clear inputs. e Note 6: TA e 25§ C and VCC e 5V. Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Parameter fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output tPHL Propagation Delay Time High to Low Level Output tPHL tPLH tPHL tPLH tPHL Min Units Max 25 MHz Clock to Ripple Carry 35 ns Clock to Ripple Carry 35 ns Propagation Delay Time Low to High Level Output Clock (Load High) to Q 20 ns Propagation Delay Time High to Low Level Output Clock (Load High) to Q 23 ns Propagation Delay Time Low to High Level Output Clock (Load Low) to Q 25 ns Propagation Delay Time High to Low Level Output Clock (Load Low) to Q 29 ns Propagation Delay Time Low to High Level Output Enable T to Ripple Carry 16 ns Propagation Delay Time High to Low Level Output Enable T to Ripple Carry 16 ns Propagation Delay Time High to Low Level Output Clear (Note 7) to Q 38 ns O tPHL RL e 400X, CL e 15 pF bs ol tPLH From (Input) To (Output) et Symbol Note 7: Propagation delay for clearing is measured from the clear input for the 161 or from the clock input transition for the 163. 3 Logic Diagrams et e 161 O bs ol TL/F/6551 – 3 4 Logic Diagrams (Continued) O bs ol et e 163 5 TL/F/6551 – 8 Logic Diagrams (Continued) Clear outputs to zero Reset to binary twelve Count to thirteen, fourteen, fifteen, zero, one and two Inhibit O (1) (2) (3) (4) bs ol et e 161, 163 Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences 6 TL/F/6551 – 5 Parameter Measurement Information bs ol et e Switching Time Waveforms TL/F/6551 – 6 Note A: The input pulses are supplied by generators having the following characteristics: PRR s 1 MHz, duty cycle s 50%, ZOUT & 50X. For 161 and 163, tr s 10 ns, tf s 10 ns. Vary PRR to measure fMAX. Note B: Outputs QD and carry are tested at tn a 16 for 161, 163 where tn is the bit time when all outputs are low. O Note C: For 161 and 163, VREF e 1.5V. 7 Parameter Measurement Information (Continued) bs ol et e Switching Time Waveforms TL/F/6551 – 7 Note A: The input pulses are supplied by generators having the following characteristics: PRR s 1 MHz, duty cycle s 50%, ZOUT & 50X. For 161 and 163, tr s 10 ns, tf s 10 ns. Vary PRR to measure fMAX. Note B: Enable P and enable T setup times are measured at tn a 0. O Note C: For 161 and 163, VREF e 1.5V. 8 et e Physical Dimensions inches (millimeters) O bs ol 16-Lead Ceramic Dual-In-Line Package (J) Order Number DM54161J or DM54163AJ NS Package Number J16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM74161N or DM74163N NS Package Number N16E 9 e et 16-Lead Ceramic Flat Package (W) Order Number DM54161W or DM54163AW NS Package Number W16A bs ol DM54161/DM74161/DM74163 Synchronous 4-Bit Counters Physical Dimensions inches (millimeters) (Continued) LIFE SUPPORT POLICY O NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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