54LS174,54LS175,DM54LS174,DM54LS175, DM74LS174,DM74LS175 54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex/Quad D Flip-Flops with Clear Literature Number: SNOS290A 54LS174/DM54LS174/DM74LS174, 54LS175/DM54LS175/DM74LS175 Hex/Quad D Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad (175) versions feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. Y Y Y Y Y Y et Y LS174 contains six flip-flops with single-rail outputs LS175 contains four flip-flops with double-rail outputs Buffered clock and direct clear inputs Individual data input to each flip-flop Applications include: Buffer/storage registers Shift registers Pattern generators Typical clock frequency 40 MHz Typical power dissipation per flip-flop 14 mW Alternate Military/Aerospace device (54LS174, 54LS175) is available. Contact a National Semiconductor Sales Office/Distributor for specifications. e Y Connection Diagrams Dual-In-Line Package bs ol Dual-In-Line Package TL/F/6404 – 1 O Order Number 54LS174DMQB, 54LS174FMQB, 54LS174LMQB, DM54LS174J, DM54LS174W, DM74LS174M or DM74LS174N See NS Package Number E20A, J16A, M16A, N16E or W16A TL/F/6404 – 2 Order Number 54LS175DMQB, 54LS175FMQB, 54LS175LMQB, DM54LS175J DM54LS175W, DM74LS175M or DM74LS175N See NS Package Number E20A, J16A, M16A, N16E or W16A Function Table (Each Flip-Flop) Inputs Outputs Clear Clock D Q Q² L H H H X u u X H L X L H L Q0 H L H Q0 L C1995 National Semiconductor Corporation TL/F/6404 H e High Level (steady state) L e Low Level (steady state) X e Don’t Care u e Transition from low to high level Q0 e The level of Q before the indicated steady-state input conditions were established. ² e LS175 only RRD-B30M105/Printed in U. S. A. 54LS174/DM54LS174/DM74LS174, 54LS175/DM54LS175/DM74LS175 Hex/Quad D Flip-Flops with Clear June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS and 54LS DM74LS 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions DM54LS174 Parameter VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 1) fCLK tW DM74LS174 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 2 2 0.8 V b 0.4 mA 4 30 Clock Frequency (Note 2) 0 25 Pulse Width (Note 6) Clock 20 Clear 20 Data Setup Time (Note 6) 20 tH Data Hold Time (Note 6) 0 tREL Clear Release Time (Note 6) 25 TA Free Air Operating Temperature 8 mA 0 30 MHz 0 25 MHz 20 ns 20 20 ns 0 ns 25 125 ns 0 bs ol b 55 e 0.7 b 0.4 0 tSU V V et Symbol 70 §C Max Units b 1.5 V ’LS174 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Min Typ (Note 3) DM54 2.5 3.4 DM74 2.7 3.4 Conditions VI Input Clamp Voltage VOH High Level Output Voltage VCC e Min, II e b18 mA VCC e Min, IOH e Max VIL e Max, VIH e Min Low Level Output Voltage VCC e Min, IOL e Max VIL e Max, VIH e Min DM54 0.25 DM74 0.35 0.5 IOL e 4 mA, VCC e Min DM74 0.25 0.4 VOL Input Current @ Max Input Voltage VCC e Max, VI e 7V O II IIH High Level Input Current VCC e Max, VI e 2.7V IIL Low Level Input Current VCC e Max VI e 0.4V IOS ICC Clock Short Circuit Output Current VCC e Max (Note 4) Supply Current VCC e Max (Note 5) V 0.4 0.1 mA 20 mA b 0.4 Clear b 0.4 Data b 0.36 DM54 b 20 b 100 DM74 b 20 b 100 16 26 Note 1: CL e 15 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. Note 2: CL e 50 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. Note 3: All typicals are at VCC e 5V, TA e 25§ C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 5: With all outputs open and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V applied to the clock. Note 6: TA e 25§ C and VCC e 5V. 2 V mA mA mA ’LS174 Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol RL e 2 kX From (Input) To (Output) Parameter CL e 15 pF Min CL e 50 pF Max Min 30 Units Max fMAX Maximum Clock Frequency 25 tPLH Propagation Delay Time Low to High Level Output Clock to Output MHz 30 32 ns tPHL Propagation Delay Time High to Low Level Output Clock to Output 30 36 ns tPHL Propagation Delay Time High to Low Level Output Clear to Output 35 42 ns Recommended Operating Conditions VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 1) fCLK Clock Frequency (Note 2) tW Pulse Width (Note 3) tH tREL TA Nom 4.5 5 2 Clock DM74LS175 Clear Data Setup Time (Note 3) Min Nom Max 5.5 4.75 5 5.25 2 V V 0.7 0.8 V b 0.4 b 0.4 mA 4 8 mA 0 30 0 30 MHz 0 25 0 25 MHz 20 20 20 20 20 20 ns ns Data Hold Time (Note 3) 0 0 Clear Release Time (Note 3) 25 25 Free Air Operating Temperature Units Max bs ol tSU Min e DM54LS175 Parameter et Symbol b 55 125 Note 1: CL e 15 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. Note 2: CL e 50 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. O Note 3: TA e 25§ C and VCC e 5V. 3 0 ns ns 70 §C ’LS175 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Min Typ (Note 1) DM54 2.5 3.4 DM74 2.7 3.4 Conditions Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min Low Level Output Voltage VCC e Min, IOL e Max VIL e Max, VIH e Min DM54 0.25 DM74 0.35 0.5 IOL e 4 mA, VCC e Min DM74 0.25 0.4 II Input Current @ Max Input Voltage VCC e Max, VI e 7V IIH High Level Input Current VCC e Max, VI e 2.7V Low Level Input Current VCC e Max VI e 0.4V IIL Clock ICC Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max (Note 3) ’LS175 Switching Characteristics DM54 DM74 0.1 mA 20 mA b 0.4 mA b 0.36 b 20 b 100 b 20 b 100 mA et IOS V b 0.4 Clear Data 0.4 e VOL V 11 18 mA at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Parameter CL e 15 pF CL e 50 pF bs ol Symbol RL e 2 kX From (Input) To (Output) Min Max 30 Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Clock to Q or Q 25 MHz 30 32 ns tPHL Propagation Delay Time High to Low Level Output Clock to Q or Q 30 36 ns tPLH Propagation Delay Time Low to High Level Output Clear to Q 25 29 ns tPHL Propagation Delay Time High to Low Level Output Clear to Q 35 42 ns Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. O Note 3: With all outputs open and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V applied to the clock input. 4 Logic Diagrams LS175 O bs ol et e LS174 TL/F/6404 – 3 5 TL/F/6404 – 4 et e Physical Dimensions inches (millimeters) O bs ol Ceramic Leadless Chip Carrier (E) Order Number 54LS174LMQB or 54LS175LMQB NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS174DMQB, 54LS175DMQB, DM54LS174J or DM54LS175J NS Package Number J16A 6 et e Physical Dimensions inches (millimeters) (Continued) O bs ol 16-Lead Small Outline Molded Package (M) Order Number DM74LS174M or DM74LS175M NS Package Number M16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS174N or DM74LS175N NS Package Number N16E 7 e et bs ol 16-Lead Ceramic Flat Package (W) Order Number 54LS174FMQB, 54LS175FMQB, DM54LS174W or DM54LS175W NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: O 54LS174/DM54LS174/DM74LS174, 54LS175/DM54LS175/DM74LS175 Hex/Quad D Flip-Flops with Clear Physical Dimensions inches (millimeters) (Continued) 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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