ETC DM6381F V.34 integrated data/ fax/voice/speakerphone modem device set Datasheet

DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
General Description
The DM336P integrated modem is a four chipset
design that provides a complete solution for state-ofthe-art, voice-band Plain Old Telephone Service
(POTS) communication. The modem provides for
Data (up to 33,600bps), Fax (up to 14,400bps), Voice
and Full Duplex Speaker-phone functions to comply
with various international standards.
The design of the DM336P is optimized for desktop
personal computer applications and it provides a low
cost, highly reliable, maximum integration, with the
minimum amount of support required. The DM336P
modem can operate over a dial-up network (PSTN) or
2 wire leased lines.
The modem integrates auto dial and answer
capabilities, synchronous and asynchronous data
transmissions, serial and parallel interfaces, various
tone detection schemes and data test modes.
The DM336P modem’s reference design is preapproved for FCC part 68 and provides minimum
design cycle time, with minimum cost to insure the
maximum amount of success.
The simplified modem system, shown in figure below,
illustrates the basic interconnection between the
MCU, DSP, AFE and other basic components of a
modem. The individual elements of the DM336P are:
• DM6380 Analog Front End (AFE). 28-pin PLCC
package
• DM6381 ITU-T V.34 Transmit Digital Signal
Processor (TX DSP). 100-pin QFP package
• DM6382 ITU-T V.34 Receive Digital Signal
Processor (RX DSP). 100-pin QFP package
• DM6383 Modem Controller (MCU) built in Plug &
Play (PnP). 100-pin QFP package
Block Diagram
Ring
Detector
LED
Address &
Data Bus
Micro
Controller
Unit
ISA Bus
MSCLK
PnP
TX DSP
RX DSP
V.24
Interface
TxD
RxD
40.32MHz
SCLK
DIT
DOT
TFS
DIR
DOR
RFS
TxBCLK
TxSCLK*2
RxBCLK
RxSCLK
20.16MHz
TxDCLK
RxDCLK
RxIN
TxA1
Analog
Font End
SPKR
DAA
Line
TxA2
Speaker
Driver
Microphone
Driver
V.24
Interface
Final
Version: DM336P-DS-F02
August 15, 2000
1
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
Table of Contents
General Description ............................................... 1
Block Diagram ....................................................... 1
Features ................................................................ 3
Chipset
• Chip 1: DM6383 Modem Controller Unit with PnP
for ISA (MCU)
DM6383 Description ........................................... 4
DM6383 Block Diagram ...................................... 4
DM6383 Features ............................................... 4
DM6383 Pin Configuration .................................. 5
DM6383 Pin Description ..................................... 6
DM6383 Functional Description .......................... 8
1. Operating Mode Selection............................ 8
2. Micro-controller (8031) Reference ................ 8
3. Micro-controller Register Description............ 8
4. UART (16550A) Emulation Registers ........... 9
5. Plug and Play (PnP) Module .......................14
DM6383 Absolute Maximum Ratings .................20
DM6383 DC Electrical Characteristics................21
DM6383 AC Electrical Characteristics & Timing
Waveforms .....................................................21
• Chip 2: DM6381/DM6382 ITU-T V.34 TX and RX
Digital Signal Processor (TX DSP and RX
DSP) Description
DM6381/82 Description .....................................22
DM6381/82 Block Diagram ................................22
DM6381/82 Features .........................................22
DM6381/82 Pin Configuration ............................23
DM6381/82 Pin Description ...............................24
2
DM6381/82 Functional Description ....................26
1. System Clock .............................................26
2. Serial Port ..................................................26
3. Dual Port RAM ...........................................26
4. Interrupt......................................................26
DM6381/82 Absolute Maximum Ratings ............26
DM6381/82 DC Electrical Characteristics...........27
DM6381/82 AC Electrical Characteristics & Timing
Waveforms.....................................................27
• Chip 3: DM6380 Analog Front End (AFE)
Description
DM6380 Description ..........................................29
DM6380 Block Diagram .....................................29
DM6380 Features..............................................30
DM6380 Pin Configuration.................................30
DM6380 Pin Description ....................................31
DM6380 Functional Description .........................31
DM6380 Absolute Maximum Ratings .................32
DM6380 DC Characteristics...............................32
DM6380 AC Characteristics & Timing Waveforms
..........................................................................33
DM6380 Performance........................................33
Application Circuit (for reference only)...................34
Package Information.............................................38
Ordering Information.............................................40
Company Overview ..............................................40
Contact Windows..................................................40
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
Features
• Compatibility
- ITU-T V.34 (33600 to 2400 bps)
- CCITT V.32bis (14400, 12000, 9600, 7200,
4800bps)
- CCITT V.32 (9600, 7200, 4800bps)
- CCITT V.22bis (2400, 1200bps)
- CCITT V.22 (1200bps)
- CCITT V.23 (1200/75bps)
- Bell 212A (1200bps)
- Bell 103 (300bps)
- CCITT V.17 (14400, 12000, 7200bps)
- CCITT V.29 (9600, 7200bps)
- CCITT V.27ter (4800, 2400bps)
- CCITT V.21 Channel 2 (300bps)
• Data Error Correction
- MNP Class 2, 3 & 4
- CCITT V.42 LAMP
• Data Compression
- MNP Class5
- CCITT V.42bis
- Voice compression
- 2 and 4 bit ADPCM voice compression
• DTE Interface
- DTE speed up to 115200bps
- Serial V.24 (EIA-232-D)
• Enhanced “AT” command set and S registers
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Caller identification (Caller ID) support
Full duplex speakerphone (Telephone Emulation)
16 Bits over-sampling codec
Selectable world wide call progress tone detection
Compromise and adaptive equalizer providing
channel impairment compensation
The channel impairment compensation
Plug and Play (PnP) support
Integrated UART 16550
Enhanced 8031 compatible micro-controller
8 selectable interrupts
Parallel and serial interfaces supported
- 6-, 7- and 8- bit character support
- Even, odd, mark and none parity detection and
generation
- 1 and 2 stop bit support
- Auto DTE data speed detection through ”AT”
Access up to 128K bytes external program memory
Access up to 64K bytes external data memory
NVRAM to store two user configurable, switchable
profiles and three programmable telephone
numbers
Full duplex data mode test capabilities
- Analog loop test
Chipset
The DM336P integrated modem device set contains 4 VLSI devices as described below:
•
•
•
•
DM6383 Modem Controller Unit with PnP for ISA (MCU)
DM6380 Analog Front End (AFE)
DM6381 ITU-T V.34 Transmit Digital Signal Processor (TX DSP)
DM6382 ITU-T V.34 Receive Digital Signal Processor (RX DSP)
Final
Version: DM336P-DS-F02
August 15, 2000
3
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
• Chip 1 : DM6383 Modem Controller Unit With PnP For ISA (MCU)
DM6383 Description
The DM6383 Modem Control Unit (MCU) is designed
for use in high speed internal and external modem
applications. Its interface is compatible with the
DM6381/DM6382 Transmit and Receive Digital
Signal Processor Chipset. The DM6383 incorporates
a micro-controller 80C31, virtual 16550A UART (with
FIFO mode), I/O and Plug & Play control logic. The
DM6383 MCU performs the general modem control
functions. It is also designed to provide Plug and Play
capability for ISA bus systems by implementing PnP
control logic. The PnP logic supports hardware &
software selectable options to allow users to
configure the internal modem card without jumpers.
DM6383 Block Diagram
Mode Selection
PC Data Bus
PC Address Bus
PnP Control
Logic
Virtual 16550
UART
IRQ & R/W Control
8031
Micro-Controller
External ROM,
RAM Interface
I/O Control Logic
Modem Control
Interface
RS 232 Interface
DM6383 Features
•
•
•
•
•
•
•
•
•
4
Control interface support
Supports parallel and serial interfaces
Includes a micro-controller 80C31
Maximum access 128K bytes external program
memory
Maximum access 64K bytes external data memory
Provides automatic configuration capability to
Industry
Configuration selectable by software
Interrupt lines selectable
I/O base conflict avoidable
• Includes a virtual 16550A UART compatible parallel
interface
• Fully programmable serial interface:
- 6-, 7- or 8-bit characters
- Even, odd, or no-parity bit generation and
detection
- 1 and 2 stop bit generation
- Baud rate generation
• Includes I/O control logic for modem control
interface
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
SEL1
/POR
RXRCLK
TXRCLK
88
87
86
D3
SEL2
89
D2
A12
90
81
A13
91
D1
A14
92
82
A15
93
83
/PNPEN
94
GND
GND
95
D0
/TUCS
96
84
PS1
97
85
TEST1
98
V DD
100
99
DM6383 Pin Configuration
UD0
1
80
D4
UD1
2
79
D5
UD2
3
78
D6
UD3
4
77
D7
UD4
5
76
CA0
UD5
6
75
CA1
UD6
7
74
CA2
UD7
8
73
CA3
/IOR
9
72
CA4
GND
10
71
CA5
/IOW
11
70
CA6
/AEN
12
69
CA7
A11
13
68
GND
A10
14
67
CA8
A9
15
66
CA9
A8
16
65
CA10
DM6383F
Final
Version: DM336P-DS-F02
August 15, 2000
50
P1.7
P1.6
51
49
30
48
V DD
RESET
P1.5
52
P1.4
29
47
RXD
IRQ10
P0.0
53
46
28
P1.2
TXD
IRQ7
45
54
P1.1
27
44
ALE/P
IRQ5
/RI
55
43
26
T1
/PSEN
IRQ4
42
56
T0
25
41
/WR
V DD
GND
57
40
24
CA16
/RD
A0
39
58
/RUCS
23
38
IRQ3
A1
EAB/VP
CA15
59
37
60
22
TEST2
21
A2
36
A3
V DD
CA14
35
61
IRQ15
20
34
CA13
A4
IRQ12
62
33
19
IRQ11
CA12
A5
32
CA11
63
31
64
18
XTAL2
17
XTAL1
A7
A6
5
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6383 Pin Description
6
Pin No.
1-8
Pin Name
UD0 - UD7
I/O
I/O
9
/IOR
I
10
11
GND
/IOW
P
I
12
/AEN
I
13 - 24
A11 - A0
I
25, 36, 52,
100
26, 27, 28,
29, 33 - 35
VDD
P
IRQ4, IRQ5,
IRQ7, IRQ10,
IRQ11, IRQ12,
IRQ15
O
30
RESET
I
31
32
37
38
XTAL1
XTAL2
TEST2
EAB/VP
I
O
I
I
39
/RUCS
O
40
CA16
O
41, 68, 85, 96
42
43
44
45, 46,
48 - 51
GND
T0
T1
/RI
P1.1, P1.2,
P1.4 - P1.7
P
I
I
I
I/O
Description
Data Bus Signal, in internal modem:
These signals are connected to the data bus of the PC I/O slot.
They are used to transfer data between the PC and the DM6383.
Modem Control Output, in external Modem:
Memory address mapping of the controller is E800H.
I/O Read:
An active low signal used to read data from the DM6383.
Ground
I/O Write:
An active low signal used to write data to DM6383.
Address Enable:
This is an active low signal to enable the system address for
DM6383.
System Address:
These signals are connected to the bus of PC I/O slot. They are
used to select DM6383 I/O ports.
+5V Power Supply
Interrupt Request:
These are 8 interrupt request pins. Only one pin, which is decoded
from Configuration Register, can be activated, the other pins are
left floating. The active pin will go high when an interrupt request is
generated from the DM6383.
Reset:
An active high signal used to power-on reset the DM6383.
Crystal Oscillator Input
Crystal Oscillator Output
Test Pin (see description of pin 99)
External ROM Select:
Should be connected to low state.
RX DSP Register Select Output:
Memory address mapping of the controller is E400H.
Bank Switch Control:
This signal is used to switch external program memory between
bank 0 (lower 64K bytes) and bank 1 (upper 64K bytes) when the
EPROM for system use is 27010 (128Kx8 bits). Otherwise, this pin
is not connected.
Ground
Controller Counter 0 Input
Controller Counter 1 Input
Ring Signal Input
Controller Port 1 I/O
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6383 Pin Description (continued)
Pin No.
47
53
54
55
Pin Name
P0.0
RXD
TXD
ALE/P
I/O
O
I
O
O
56
/PSEN
O
57
58
59
60 - 67
69 - 76
77 - 84
86
87
88
89, 90
/WR
/RD
IRQ3
CA15 - CA8
CA7 - CA0
D7 - D0
TXRCLK
RXRCLK
/POR
SEL1, SEL2
O
O
O
O
O
I/O
I
I
O
O
91 - 94
A12 - A15
I
95
/PNPEN
I
97
/TUCS
O
98
PS1
O
99
TEST1
I
Description
Modem Control Output (memory map is bit 4 of DAA)
Controller Serial Port Data Input
Controller Serial Port Data Output
Controller Address Latch Enable:
Output pulse for latching the low byte of the address during
accesses to the external memory.
Controller Program Store Enable:
This output goes low during a fetch from external program memory.
Controller External Data Memory Write Control
Controller External Data Memory Read Control
Interrupt Request (see description of pin 26)
Controller Address Bus
Controller Address Bus
Controller Data Bus
Transmitter Baud Rate Clock Input (Controller INT 0)
Receiver Baud Rate Clock Input (Controller INT 1)
DSP Reset Output
Modem Control Output (Memory map is bit 1-2 of DAA at memory
address D000H)
System Address:
These signals are connected to the bus of the PC I/O slot. They are
used to select the DM6383 I/O ports.
PnP Mode Enable:
This pin will be detected to enable/disable the PnP mode. When it
is pulled down by a resistor (3.3K ~ 4.7K), the DM6383 can enter
the PnP mode when it receives the PnP initial key sequence. When
disconnected, an internal pull up will disable the Plug and Play
function.
TX DSP Register Select Output:
Memory address mapping of the controller is F000H.
Modem Control Port Select Output:
Memory address mapping of the controller is D800H.
Test Pin: Used for system configuration and test mode
TEST2
0
0
1
1
Final
Version: DM336P-DS-F02
August 15, 2000
TEST1
0
1
0
1
System Configuartion
Internal mode
External mode
Test mode
Test mode
7
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6383 Functional Description
1. Operating Mode Selection
The DM6383 MCU can be used with both internal and
external modems. When it works within an internal
modem, pin TEST2 and TEST1 must be in a low state.
The DM6383 includes a virtual UART and supports a
parallel interface.
When DM6383 works within an external modem, pin
TEST2 must be in a low state, and pin TEST1 must
be in high. The virtual UART will be disabled and the
RS232 serial interface, enabled.
The clock source of the virtual UART logic is fixed at
1.8432MHz. The clock is derived from the external
crystal used by the DM6383 controller. Therefore, the
UART 1.8432MHz clock must be obtained through
division. When the operating frequency of the
DM6383 controller changes, the divider should be
changed accordingly. This divider is specified by the
Configuration Register which can be written by the
DM6383 controller. The address mapping of the
register is D4000H: (DM6383 controller memory
mapping)
Bit 0: Always 0.
TEST2
LOW
LOW
HIGH
TEST1
LOW
HIGH
X
System Configuration
Internal Modem
External Modem
Test Mode
2. Micro-controller (80C31) Reference
DM6383 supports a bank switch control pin to switch
external program memory between lower 64K bytes
(bank 0) and upper 64K bytes (bank 1) of 27C010.
In this mode, two instructions must be included in
software to switch bank 0 to bank 1:
i.e.,
CLR
P1.3
JMP
BANK 1 ADDRESS
With the same way, it can also switch back to bank 0
by
SETB
P1.3
JMP
BANK 0 ADDRESS
* For detailed information about micro-controller,
please see Programmer's Guide to 8031.
3. Micro-controller Register Description
8
Bit 7: Not used.
b. UART Baud Generator Divisor Latch Register:
Address EC00H
Read only
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0
By reading this register, the micro-controller can
monitor the value of the low byte divisor latch of the
virtual UART baud generator (see DLL in next section)
and determine the baud rate clock itself.
c. Modem Status Controller Register (MSCR):
Address E000H
Write only
bit7 bit6
0
a. UART Clock Register :
Address D4000H Reset State: 06H
Write Only
bit7 bit6 bit5 bit4 bit3 bit2 bit1
X
dat6 dat5 dat4 dat3 dat2 dat1
Bit 6-1: B6 - B1 define the clock di vider range from 2
to 64 (even number).
bit0
0
0
bit5
bit4
0
0
bit3
bit2
bit1
bit
0
/CTS /DSR /DCD /RI
The advantage of this register is that the modem line
status information can be passed to the virtual UART
by the micro-controller. The resulting signals are Ring
Detect (/RI), Carrier Detect (/DCD), Data Set Ready
(/DSR) and Clear To Send (/CTS).
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
d. Modem Output Port Register: Address D000H
Write only
bit7 bit6
bit5
bit4
bit3 bit2 bit1 bit0
PO0 SEL2 SEL1 /POR
* When reset condition occurred, the I/O and Interrupt
configuration registers must be reset to default
value according to bit 0 - bit 5.
4. UART(16550A) Emulation Registers
These 4 bits work as output ports in response to the
88th, 89th, 90th and 47th pins of this chip (see pin
description).
a. Receiver Buffer (Read), Transmitter Holding
Register (Write)
e. PnP Isolation & Resource Data Port: Address
F800H
Address: 0 (DLAB=0) Reset State 00h
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0
Write only
The PnP isolation and resource data can be bytesequentially written to the corresponding memory
(built-in SRAM) through this register.
When this register address is read, it contains the
parallel received data. Data to be transmitted is
written to this register.
f. Auto-configuration Register: Address F400H
b. Interrupt Enable Register (IER): Address 1
bit2 bit1 bit0 IRQ bit5 bit4 bit3
0 0 0
3
0 0
0
0 0 1
4
0 0
1
0 1 0
5
0 1
0
0 1 1
7
0 1
1
1 0 0 10 1 0
0
1 0 1 11 1 0
1
1 1 0 12 1 1
0
1 1 1 15 1 1
1
Reset State 00h, Write Only
bit7 bit6 bit bit4 bit3
5
0
0
0
0 Enable
Mode
mStatu
s
Intr
I/O
03F8-03FF(COM1)
02F8-02FF(COM2)
03E8-03EF(COM3)
02E8-02EF(COM4)
03F0-03F7(COM5)
02F0-02F7(COM6)
03E0-03E7(COM7)
02E0-02E7(COM8)
The default I/O base and IRQ data stored in 94C46
should be loaded to this register by micro-controller,
and then enable the default configuration. Microcontroller can also get the current I/O base and IRQ
information by a read from this register.
The configuration determined by this register should
be disabled when the register detects the Initiation
Key described in the next section.
Bit 6: When this bit is set to inform micro-controller
that the current I/O base and IRQ data should
be stored to 93C46 as the default setting at the
next power-on reset through programming the
Auto-configuration Register, this bit should be
cleared by micro-controller.
Bit 7: When bit 7 is set, it enables hardware
configuration set according to bit 0-bit 5
(Jumper mode) and load the proper value of
PnP Registers including I/O and Interrupt
Configuration Registers. This bit will be reset,
when it receives PnP Initial Key sequence.
Final
Version: DM336P-DS-F02
August 15, 2000
bit2
bit1
bit0
Enable Enable Enable
Line
TX
RX
Status Holdin Data
Intr
g
Intr
Regist
er
Intr
This 8-bit register enables the four types of interrupts
as described below. Each interrupt source can
activate the INT output signal if enabled by this
register. Resetting bits 0 through 3 will disable all
UART interrupts.
Bit 0: This bit enables the Received Data Available
Interrupt (and timeout interrupts in the FIFO
mode) when set to logic 1.
Bit 1: This bit enables the Transmitter Holding
Register Empty Interrupt when set to logic 1.
Bit 2: This bit enables the Receiver Line Status
Interrupt when set to logic 1.
Bit 3: This bit enables the MODEM Status Interrupt
when set to logic 1.
Bit 4-7: Not used
9
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
c. Interrupt Identification Register (IIR): Address 2
Reset State 01h, Read only
bit7 bit6 bit5 bit4 bit3 bit2 bit1
FIFO 0 0 0
D3:
D2:
D1:
Enable
INTD2 INTD1 INTD0
bit0
D0:
int
Pending
In order to provide minimum software overhead
during data transfers, the virtual UART prioritizes
interrupts into four levels as followed: Receiver Line
Status (priority 1), Receiver Data Available (priority 2),
Character Timeout Indication (priority 2, FIFO mode
only), Transmitter Holding Register Empty (priority 3 ),
and Modem Status (priority 4).
The IIR register gives prioritized information as to the
status of interrupt conditions. When accessed, the IIR
indicates the highest priority interrupt that is pending,
as indicated by bits INTD(2-0).
D3 D2 D1 D0 Priority Level
0
0
0
1
0
1
1
0
Highest
Interrupt Type
Receiver Line
Status
0
1
0
0
Second
Receiver Data
Available
1
1
0
0
Second
Character
Timeout
Indication
0
0
1
0
Third
0
0
0
0
Fourth
10
Transmitter
Holding Register
Empty
Modem Status
Bit 0: This bit can be used in either a prioritized
interrupt or polled environment to indicate
whether an interrupt is pending. When this bit is
a logic 0, an interrupt is pending, and the IIR
contents may be used as a pointer to the
appropriate interrupt service routine. When bit 0
is a logic 1, no interrupt is pending, and polling
(if used) continues.
Bit 1-2: These two bits of the IIR are used to identify
the highest priority interrupt pending, as
indicated in the table below.
Bit 3: In character mode, this bit is 0. In FIFO mode,
this bit is set, along with bit 2, when a timeout
interrupt is pending.
Bit 4-6: Not used
Bit 7: This bit is set when FCR0 = 1.
Condition
Overrun Error, Parity
Error, Framing Error or
Break Interrupt
Receiver Data Available
or Trigger Level Reached
No characters have been
read from or written to the
Rx FIFO during
programming time
interval, and the Rx FIFO
is not empty
Transmitter Holding
Register Empty
Clear to Send, Data Set
Ready, Ring Indicator or
Data Carrier Detected
Reset
Reads the Line Status
Register
Reads the Receiver
Buffer Register or the
FIFO Drops Below The
Threshold Value
Reads The Receiver
Buffer Register
Reads the IIR Register or
(if source of interrupt)
Writes To The Transmitter
Holding Register
Reads the Modem Status
Register
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
d. FIFO Control Register (FCR): Address 2
Reset State 00h , write only
bit7 bit6 bit bit bit3
bit2
bit1
bit0
5 4
RCVR RCVR 0 0 DMA TxFIFO RxFIFO FIFO
Trig Trig
Mode Reset Reset Enabl
(MSB) (LSB)
e
This is a write only register at the same location as
the IIR, which is a read only register. This register is
used to enable the FIFOs, clear the the FIFOs, set the
RxFIFO trigger level, and select the type of DMA
signal.
Bit 0: Writing a 1 to FCR0 enables both transmit and
receive FIFOs. Resetting FCR0 will clear all
bytes in both FIFOs. When changing from FIFO
mode to Character mode (and vice versa), data
is automatically cleared from the FIFOs.
Bit 1: Writing a 1 to FCR1 clears all bytes in the
RxFIFO and resets its counter logic to 0.
Bit 2: Writing a 1 to FCR2 clears all bytes in the
TxFIFO and resets its counter logic to 0.
Bit 3: Setting FCR3 to 1 will cause the RXRDY and
TXRDY pins to change from mode 0 to mode 1
if FCR0 = 1.
Bit 4-5: Reserved
Bit 6-7: FCR6, FCR7 are used to set the trigger level
for the RxFIFO interrupt.
FCR6
0
0
1
FCR7
0
1
0
RxFIFO Trigger Level
01
04
08
e. Line Control Register (LCR): Address 3
Reset State 00h, Write Only
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DLAB SBRK STP EPS PEN STB WLS1 WLS0
Final
Version: DM336P-DS-F02
August 15, 2000
This register is available to maintain compatibility with
the standard 16550 register set, and provides
information to the internal hardware that is used to
determine the number of bits per character.
WLS1
0
0
1
1
WLS2
0
1
0
1
Word Length
5 bits
6 bits
7 bits
8 bits
Bit 0-1: WLS0-1 specifies the number of bits in each
transmitted and received serial character.
Bit 2: This bit specifies the number of stop bits in
each transmitted character. If bit 2 is a logic 0,
one stop bit is generated in the transmitted data.
If bit 2 is a logic 1 when a 5-bit word length is
selected via bits 0 and 1, one and a half stops
are generated. If bit 2 is a logic 1 when either a
6-, 7- or 8-bit word length is selected, two stop
bits are generated. The Receiver checks the
first Stop-bit only, regardless of the number of
Stop bits selected.
Bit 3: Logic 1 indicates that the PC has enabled the
parity generation and checking.
Bit 4: Logic 1 indicates that the PC is requesting an
even number of logic 1s to be transmitted or
checked. Logic 0 indicates that the PC is
requesting odd parity generation and checking.
Bit 5: When bit 3, 4 and 5 are logic 1, the parity bit is
transmitted and checked by the receiver as
logic 0. If bits 3 and 5 are 1 and bit 4 is logic 0,
then the parity is transmitted and checked as
logic 1.
Bit 6: This is a Break Control bit. When it is set to
logic 1, a break condition is indicated.
Bit 7: The Divisor Latch Access bit must be set to
logic 1 to access the Divisor Latches of the
baud generator during a read or write operation.
It must be set to logic 0 to access the Receiver
Buffer, the Transmitter Holding Register, or the
Interrupt Enable Register.
11
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
f. Modem Control Register (MCR): Address 4
Reset State 00h
bit7 bit6 bit5
0
0
0
bit4
0
bit3
0
bit2 bit1 bit0
0
RTS DTR
Bit 0: This bit asserts a Data Terminal Ready
condition that is readable via port P1.1 of microcontroller 8031. When bit 0 is set to logic 1, the
P1.1 is forced to logic 0. When bit 0 is reset to
logic 0, the P1.1 is forced to logic 1.
Bit 1: This bit asserts a Request To Send condition
that is readable via port P3.4 of the microcontroller 8031. Bit 1 affects P3.4 in a manner
identical to that described above for bit 0.
g. Line Status Register (LSR): Address 5
Reset State 60h, Read only
bit7
bit6
bit5 bit4 bit3 bit2 bit1 bit0
RCV ETEMT THRE BI
FE PE OE DR
This register provides status information to the host
PC concerning the data transfer. Bit 1-4 indicate the
error conditions that produce a Receiver Line Status
interrupt whenever any of the corresponding
conditions are detected. The Line Status Register is
intended for read operations only.
Bit 0: Set to logic 1 when a received character is
available in the RxFIFO. This bit is reset to logic
0 when the RxFIFO is empty.
Bit 1: An Overrun error will occur only after the
RxFIFO is full and the next character has
overwritten the unread FIFO data. This bit is
reset upon reading the Line Status Register.
Bit 2: A value of logic 1 indicates that a received
character does not have the correct even or
odd parity as selected by the Even Parity Select
bit. This error is set when the corresponding
character is at the top of the RxFIFO. It will
remain set until the CPU reads the LSR. This
Parity Error indication is associated with the
particular character in the FIFO to which it
applies. This error is revealed to the CPU when
its associated character is at the top of the
FIFO.
12
Bit 3: This bit is the Framing Error (FE) indicator. Bit 3
indicates that the received character did not
have a valid stop bit. Bit 3 is set to a logic 1
whenever the stop bit following the last data bit
or parity bit is detected as a zero bit (spacing
level). The FE bit is reset whenever the CPU
reads the contents of the Line Status Register.
The FE error condition is associated with the
particular character in the FIFO to which it
applies. This error is revealed to the CPU when
its associated character is at the top of the
FIFO.h. Modem Status Register (MSR):
Address 6 Reset State, bit 0-3: low, bit 4-7:
input signal.
Bit 4: This bit is a Break Interrupt (BI) indicator. Bit 4
is set to logic 1 whenever the received data
input is held in the Spacing (logic 0) state for
longer than a full word transmission time (that is,
the total time of Start bit + data bits + Parity +
Stop bits). The BI indicator is reset whenever
the CPU reads the contents of the Line Status
Register. The BI error condition is associated
with the particular character in the FIFO to
which it applies. This error is revealed to the
CPU when its associated character is at the top
of the FIFO.
Bit 5: This bit is a Transmitter Holding Register Empty
indicator. Bit 5 indicates that UART is ready to
accept a new character for transmission. In
addition, this bit causes UART to issue an
interrupt to the CPU when the Transmit Holding
Register Empty Interrupt Enable is set high. The
THRE bit is reset to logic 0 when the host CPU
loads a character into the Transmit Holding
register. In the FIFO mode, this bit is set when
the TxFIFO is empty, and is cleared when at
least 1 byte is written to the TxFIFO.
Bit 6: This bit is the Transmitter Empty indicator. Bit 6
is set to a logic 1 whenever the Transmitter
Holding Register (THR) is empty, and is reset to
a logic 0 whenever the THR contains a
character. In FIFO mode, this bit is set to 1
whenever the transmitter FIFO is empty.
Bit 7: In character mode, this bit is 0. In FIFO mode,
this bit is set when there is at least one parity
error, framing error, or break indication in the
FIFO. If there are no subsequent errors in the
FIFO, LSR7 is cleared when the CPU reads the
LSR.
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
h. Modem Status Register (MSR): Address 6
i. Scratch Register (SCR): Address 7
Reset State bit 0-3 : low , bit 4-7: Input Signal
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DCD RI DSR CTS DDCD TERI DDSR DCTS
Reset State 00h
This 8-bit Read/Write Register does not control the
UART in any way. It is intended as a Scratch Pad
Register to be used by the programmer to hold data
temporarily.
This 8-bit register provides the current state of the
control lines from the Modem to the CPU. In addition,
four bits of the Modem Status Register provide
change information. These bits are set to a logic 1
whenever a control input from the Modem changes
state. They are reset to logic 0 whenever the CPU
reads the Modem Status Register.
Bit 0: This bit is the Delta Clear to Send (DCTS)
indicator. Bit 0 indicates that the CTS (MSCR3)
has changed state since the last time it was
read by the CPU.
j. Divisor Latch (DLL): Address 0 (DLAB = 1)
Reset State 00h
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0
This register contains baud rate information from the
host PC. The PC sets the Divisor Latch Register
values.
k. Divisor Latch (DLM): Address 1 (DLAB = 1)
Bit 1: This bit is the Delta Data Set Ready (DDSR)
indicator. Bit 1 indicates that the DSR (MSCR2)
has changed state since the last time it was
read by the CPU.
Reset State 00h
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0
Bit 2: This bit is the Trailing Edge of Ring indicator. Bit
2 indicates that the RI (MSCR0) has changed
from a low to a high state.
This register contains baud rate information from the
host PC.
Bit 3: This bit is the Delta Data Carrier Detect (DDCD)
indicator. Bit 3 indicates that the DCD (MSCR1)
has changed state.
Note: Two 8-bit latches (DLL-DLM) store the divisor in
16-digit binary format. The desired baud rate
can be obtained by dividing the 115200Hz clock
by the divisor.
Note: Whenever bit 0, 1, 2 or 3 is set to a logic 1, a
Modem Status Interrupt is generated.
Bit 4: This bit reflects the value of MSCR3
(CTS).
Bit 5: This bit reflects the value of MSCR2
(DSR).
Bit 6: This bit reflects the value of MSCR0 (RI).
Bit 7: This bit reflects the value of MSCR1
(DCD).
Final
Version: DM336P-DS-F02
August 15, 2000
Desired Baud Rate
50
75
110
150
300
600
1200
2400
4800
9600
19200
38400
57600
115200
Divisor Value
2304
1536
1047
768
384
192
96
48
24
12
6
3
2
1
13
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
5. Plug and Play (PnP) Module
a. Auto-configuration Ports
Three 8-bit I/O ports are defined for the PnP
read/write operations. They are called Autoconfiguration ports as listed below.
Port
Type
ADDRESS W
WRITE_
DATA
READ_
DATA
W
R
Location
0279H
(Printer status port)
0A79H
(Printer status port + 0800H)
Relocatable in range
0203H to 03FFH
To access the Plug and Play Register, a host should
follow this procedure: Write a target register address
(Register Index), choose a port (WRITE_DATA or
READ_DATA), then enter data. But Plug & Play
Register could be directly accessed without the need
to write to the ADDRESS port before each access.
The ADDESS port is also the write destination of the
initiation key, which will be described later.
b.
Plug and Play Registers
The Plug and Play Registers may be divided into
Card Registers and Logical Device Registers.
According to the Plug & Play specification, if a PnP
card contains more than one logical device, there are
one more copies of Logical Device Registers in the
PnP card. However, the DM6383A contains only one
logical device, the Card Register and Logical Device
Registers are unique for each card. Those PnP
registers or bits not defined below are all read with
value = 0.
(1) Card Control Registers
Index
00H
01H
02H
03H
04H
05H
06H
14
Name
Type
Definition
Set RD_DATA port
W The location of the READ_DATA port is determined by writing to this
register. Bits [7:0] become ISA I/O read port address bits [9:2]. Address
bits [1:0] of the READ_DATA port are always 1.
Serial Isolation
R A read to this register causes a PnP card in the Isolation state to compare
one bit of the card serial ID. This process is described in more detail in the
next section.
Config Control
W Bit [0] - Reset Command Setting
This bit will reset all logical devices and restore configuration registers to
their power-up values. The CSN is preserved.
Bit [1] - Wait for Key Command Setting
This bit makes the PnP card return to the Wait for Key state. The CSN is
preserved.
Bit [2] - PnP Reset CSN Command Setting
This bit will reset the card CSN to 0. Note that the hardware will
automatically clear the bits without any need for software to clear them.
Wake [CSN]
W A write to this register will cause all cards that have a CSN that matches
the write data [7:0] to go from the Sleep state to either the 1) Isolation
state if the write data for this command is zero, or 2) Configuration state if
the write data is not zero.
Resource Data
R
A read from this register reads the next byte of resource data. The Status
Register must be polled until bit[0] is set before this register may be read.
Status
R Bit [0], when set, indicates it is ready to read the next data byte from the
Resource Data Register.
Card Select Number R/W A write to this register sets a card CSN. After a serial identification
(CSN)
process, the CSN value (CSN) is uniquely assigned to each ISA PnP card
so that each card may be individually selected during a Wake[CSN]
command.
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
(1) Card Control Registers (continued)
Index
07H
Name
Logical Device
Type
Definition
R 00H (Only one logical device in DM6383A)
(2) Logical Device Control Registers
Index
30H
Name
Activate
31H
I/O Range Check
Type
Definition
R/W For each logical device, there is one Activate register that controls
whether or not the device is active on the ISA bus. Bit[0], if set, activates
the logical device. Before a logical device is activated, I/O range check
must be disabled.
R/W This register is used to perform a conflict check on the I/O port range
programmed for use by a logical device.
Bit[1] - This bit, when set, enables I/O range check. I/O port range check
is only valid when the logical device is inactive.
Bit[0] - If set, this bit forces logical device to respond to I/O reads within
logical device assigned I/O range with a 55H when I/O range check is in
operation. If clear, the logical device drives AAH.
c. Logical Device Configuration Registers
(1) I/O Configuration Registers
Index
60H
Name
I/O base address
bits[15:8]
61H
I/O base address
bits[7:3]
Type
Definition
R/W Read/write value indicating the selected I/O Lower Limit Address Bits
[15:8] for I/O descriptor 0. If a logical device indicates it uses only 10
bits for decoding, then bits [15:10] need not to be supported.
R/W Read/write value indicating the selected I/O Lower Input Address Bits
[7:3] for I/O descriptor 0.
(2) Interrupt Configuration Registers
Index
70H
Name
IRQ level
Type
R/W
71H
IRQ type bits [7:0]
R
Definition
Read/write value indicating a selected Interrupt Level Bits[3:0] Select
which ISA interrupt level is used. A value of 1 selects IRQ1, 15 selects
IRQ15, etc. IRQ0 is not a valid interrupt selection.
Read/write value indicating which type of interrupt is used for the IRQ
selected above Bit[1] - Level, 1 = high, 0 = low Bit[0] - Type, 1= level, 0 =
edge for DM6383A, this register is read only with value = 02H.
(3) Vender Define Register
Index
F0H
Name
Auto Configuration
Type
R/W
F1H
IRQ Status Enable
W
F2H
IRQ Status
R
Final
Version: DM336P-DS-F02
August 15, 2000
Definition
The I/O base address and IRQ can be configured by CPU through this
register. (It can also be configured by micro-controller. See previous
section).
Before reading IRQ lines status, bit 0 must be set in order to load IRQ
lines status to IRQ Status register, bit 1 enable Pull Low resistor.
This register responds to IRQ lines status to determine which interrupt
has been used by PC system. bit 0: IRQ 3 bit 1: IRQ 4 bit 2: IRQ 5 bit 3:
IRQ 7 bit 4: IRQ 10 bit 5: IRQ11 bit 6: IRQ12 bit 7: IRQ15.
15
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
d. DM6383 Configuration Modes
The DM6383A is power-on in jumpless mode. The
default configuration is set by loading the default
value stored in 93C46 to Auto-configuration register.
These values can be modified by software via the
logical device configuration registers in DM Jumpless
mode. This update value of new configuration is only
valid temporarily and will be lost after an active PC
Hardware Reset. Permanent changes of default
configuration will be done by informing microcontroller to modify the content of 93C46 via Autoconfiguration Register.
The Plug and Play logic can operate through two
configuration modes: One is DM Jumpless mode, the
other, PnP mode. There are two operating methods
between the two modes: First, setting hard
configuration through Initiation Key sequences,
second, setting hard configuration according to the
register that is used, I/O Configuration Register or
Auto-configuration Register.
writes) to the Address port, which is called the
Initiation Key. The proper series of the I/O writes is
detected, then the Plug and Play read/write data ports
are enabled. The Write sequence will be reset and
must be issued from the beginning if any data
mismatch occurs. The exact sequence for Initiation
Key is listed below in hexadecimal notion.
(2) PnP Initiation Key
6A, B5, DA, ED, F6, FB, 7D, BE, DF, 6F, 37, 1B, 0D,
86, C3, 61, B0, 58, 2C, 16, 8B, 45, A2, D1, E8, 74,
3A, 9D, CE, E7, 73, 39
(3) DM Initiation Key
68, 34, 1A, 8D, CB, E3, 71, B8, 5C, 2E, 97, 4B, 25,
92, C9, E4, 72, B9, DC, 6E, B7, 5B, 2D, 96, CB, 65,
B2, D9, EC, 76, BB, 5D
(4) Isolation Protocol
(1) The Initiation Key for Plug and Play
The Plug and Play logical is in sequence on powering
up and must be enabled by softwares. This is
achieved by a predefined series of writes (32 I/O
A simple algorithm is used to isolate each Plug and
Play card. This algorithm uses the signals on the ISA
bus and requires lock-step operation between the
Plug and Play hardware and the isolation software.
STATE
ISOLATION
READ FROM SERIAL ISOLATION REGISTER
GET ONE BIT FROM SERIAL IDENTIFIER
YES
NO
ID BIT = "1H"
DRIVE "55H" ON SD[7:0]
LEAVE SD[7:0]
IN HIGH-IMPEDANCE
NO
SD[1:0] = "01"
YES
WAIT FOR NEXT READ FROM SERIAL ISOLATION REGISTER
DRIVE
"AAH" ON
SD[7:0]
LEAVE SD[7:0]
IN HIGH IMPEDANCE
NO
SD[1:0] = "10"
AFTER I/O READ COMPLETES
FETCH NEXT ID BIT FROM
SERIAL IDENTIFIER
NO
READ ALL 72 BITS
FROM SERIAL
IDENTIFIER
YES
ID = 0
OTHER CARD ID = 1
STATE
SLEEP
YES
ONE CARD
ISOLATED
16
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
(5) Serial Identifier
The key element of the Plug and Play isolation
protocol is that each card contains a unique number
called a serial identifier. The serial identifier is a 72-bit
unique, non-zero number composed of two 32 bit
fields and 8-bit checksum. The first 32-bit field is a
vendor identifier. The other 32-bits can be any value,
Checksum
BYTE
7:0
such as a serial number, part of a LAN address, or a
static number, as long as no two cards in a single
system will ever have the same 64-bit number. The
serial identifier is accessed bit-serially by isolation
logic, and is used to differentiate the cards.
Serial Number
Vendor ID
BYTE BYTE BYTE BYTE BYTE BYTE
BYTE
7:0
7:0
7:0
7:0
7:0
7:0
7:0
BYTE
7:0
SHIFT
Table 2. Shifting of Serial Identifier
The shift order for all Plug and Play serial isolation and resource data is defined as bit [0], bit [1], and so on
through bit [7].
(6) Hardware Protocol
The isolation protocol can be invoked by the Plug and
Play software at any time. The previously described
Initiation Key puts all cards into configuration mode.
The hardware on each card expects 72 pairs of I/O
read accesses to the READ_DATA port. The card ’s
response to these reads depends on the value of
each bit of the serial identifier, which is examined one
bit at a time, as shown in Table 2.
If the current bit of the serial identifier is a "1," then the
card will drive the data bus to 55H to complete the
first I/O read cycle. If the bit is a “0,” then the card puts
its data bus driver into high impedance. All cards in
high impedance will check the data bus during the I/O
read cycle to sense if another card is driving SD[1:0]
to "01." During the second I/O read, the card(s) that
drove the 55H will now drive a AAH. All high
impedance cards will check the data bus to sense if
another card is driving SD [1:0] to "10."
If a high impedance card senses another card driving
the data bus with the appropriate data during both
cycles, it ceases to participate in the current iteration
of card isolation. Such cards, which lose out, will
participate in future iterations of the isolation protocol.
Note: During each read cycle, the Plug and Play
hardware drives the entire 8-bit data bus, but
checks only the lower 2 bits.
If a card is driving the bus or is in high impedance
state and does not sense another card driving the
bus, then it should prepare for the next pair of I/O
reads. The card shifts the serial identifier by one bit,
using the shifted bit to decide its response. The above
sequence is repeated for the entire 72-bit serial
identifier.
At the end of this process, one card remains. This
card is assigned a handle referred to as the Card
Select Number (CSN) that will be used later to select
the card. Cards that have been assigned a CSN will
not participate in subsequent iterations of the isolation
protocol. Cards must be assigned a CSN before they
will respond to the other PnP commands.
(7) Software Protocol
The Plug and Play software sends the Initiation Key to
all Plug and Play cards to place them into
configuration mode. The software is then ready to
perform the isolation protocol.
The Plug and Play software generates 72 pairs of I/O
read cycles from the READ_DATA port. The software
checks the data returned from each pair of I/O reads
for the 55H or AAH driven by the hardware. If both
55H or AAH are read back, then the software
assumes that the hardware has a "1" bit in that
position. All other bits are assumed to be a "0."
During the first 64 bits, software generates a
checksum using the received data. The checksum is
compared with the checksum read back in the last 8
bits of the sequence.
Final
Version: DM336P-DS-F02
August 15, 2000
17
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
There are two other special considerations for
software protocol. During an iteration, it is possible
that the 55H and AAH combination is never detected.
It is also possible that the checksum does not match.
If either of these cases occurs on the first iteration, it
must be assumed that the READ_DATA port is in
conflict. If a conflict is detected, then the
READ_DATA port will be relocated. The above
process is repeated until a non-conflicting location for
the READ_DATA port is found. The entire range
between 203H and 3FFH is available; however, in
practice, it is expected that only a few locations will be
tried before software determines that no Plug and
Play cards are present.
During subsequent iterations, the occurrence of either
of these two special cases should be interpreted as
the absence of any further Plug and Play cards (i.e.
the last card was found in the previous iteration). This
terminates the isolation protocol.
Note: The software must delay 1 msec prior to
starting the first pair of isolation reads, and wait
250 msec between each sub-sequence pair of
isolation reads. This delay gives the ISA card
time to access information from very slow
storage devices.
(8) Plug and Play Isolation Sequence
The Plug and Play isolation sequence is divided into four states: Wait for Key, Sleep, Isolation, and Configuration.
The state transitions for the Plug and Play ISA card are shown below:
POWER UP
RETDRV OR
RESET COMMAND
STATE
ACTIVE COMMANDS
NO ACTIVE
COMMANDS
WAIT FOR KEY
STATE
ACTIVE COMMANDS
SLEEP
RESET
RESET CSN
WAIT FOR KEY
WAKE(CSN)
WAKE=0 & CSN=0
WAKE<>0 & WAKE=CSN
LOSE SERIAL ISOLATION OR
WAKE<>CSN
STATE
ISOLATION
WAKE<>CSN
ACTIVE COMMANDS
RESET
RESET CSN
WAIT FOR KEY
SET RD_DATA PORT
SERIAL ISOLATION
WAKE(CSN)
SET CSN
STATE
SET CSN
CONFIG
ACTIVE COMMANDS
RESET
RESET CSN
WAIT FOR KEY
WAKE(CSN)
RESOURCE DATA
STATUS
LOGICAL DIVICE
I/O RANGE CHECK
ACTIVATE
CONFIGURATION REGISTERS
Note: 1. CSN = Card Select Number.
2. RSTDRV causes a state transition from the current state to Wait for Key and sets all CSNs to zero.
3. The Wait for Key command causes a state transition from the current state to Wait for Key.
4. The Reset CSN commands include PnP Reset CSN and DM Reset CSN commands.
The former sets all ISA PnP cards CSNs to zero, while the latter only sets DM6383 PnP cards
CSNs to zero. command will cause a state transition.
Plug and Play ISA Card State Transitions
18
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
(9) Isolation and Resource Data
DM6383 built in 64-bytes SRAM that can be accessed
by micro-controller an PnP Isolation and Resource
Data Registers. Through port F800H, micro-controller
can load serial data and part of resource data to
SRAM byte by byte. It is important to note that the
length of the data frame to be programmed should be
loaded first, next, isolation data, and then resource
data port.
Resource Data Block ={ 30,
30,
30,
30,
30,
30,
30,
30,
30,
30,
30,
38,
47,
47,
47,
47,
47,
47,
47,
47,
47,
47,
47,
79}
01,
01,
01,
01,
01,
01,
01,
01,
01,
01,
01,
f8,
f8,
e8,
e8,
e8,
e8,
e8,
e8,
f8,
f8,
00,
02,
03,
03,
02,
03,
02,
03,
02,
03,
02,
02,
f8,
f8,
e8,
e8,
e8,
e8,
e8,
e8,
f8,
f8,
f8,
02,
03,
03,
02,
03,
02,
03,
02,
03,
02,
03,
When a read from PnP resource data register occurs,
the data stored in SRAM will be sent to ISA data bus,
and then the data pointer will be added by 1. Once the
data pointer is equivalent to the data length, the next
data read will change the pointer value to the
beginning of resource data block and describe the
other fixed resource data.
08, 08,
08, 08,
08, 08,
08, 08,
08, 08,
08, 08,
08, 08,
08, 08,
08, 08,
08, 08,
08, 08,
22, 08,
22, 10,
22, 10,
22, 08,
22, 20,
22, 20,
22, b8,
22, b8,
22, b8,
22, b8,
22, b8,
00
00
00
00
00
00
9c
9c
9c
9c
9c
* The data pointer will return to 1 when a Hardware Reset or Software Wake[CSN] is occurred.
On powering up, modem card detects RSTDRV, sets
CSN to 0, loads isolation data and resource data to
built-in 64-bytes SRAM, programs Auto-configuration
Register, configures hardware from Autoconfiguration Register, and then enters the Wait for
Key state. There is a required 2 msec delay from
either a RSTRDV or a PnP Reset command to any
Plug and Play access to allow a card to load these
information via internal micro-controller.
Cards in the Wait For Key state will not acknowledge
any access to their auto-configuration ports until the
Initiation Key is detected and they ignore all ISA
access to their Plug and Play interface. When the
cards have received the initiation key, they enter the
Sleep state. In this state, the cards listen for a Wake
[CSN] command with the write data set to 00H. This
Wake[CSN] command will send all cards to the
Isolation state and reset the serial identifier/resource
data pointer to the beginning.
Final
Version: DM336P-DS-F02
August 15, 2000
The first time the cards enter the Isolation state, it is
necessary to set the READ_DATA port address using
the Set RD_DATA port command. The software
should then use isolation protocol to check the
selected READ_DATA port address and to see if it is
in conflict with any other device.
Next, 72 pairs of reads are performed to the Serial
Isolation Register to isolate a card, as previously
described. When the checksum read from the card is
valid, it means the card is already isolated. The
isolated card remains in the Isolation state, while all
other cards fail the isolation protocol and are returned
to the Sleep state. The CSN on the isolated card is
set to a unique number, causing this card to change
to the Configuration state. Sending a Wake[0]
command causes this card to change back to Sleep
state, and all cards with a CSN value of zero to
change to the Isolation state. This entire process will
repeat until no Plug and Play cards are detected.
19
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
(10) Reading Resource Data
Each PnP card supports a resource data structure
stored in a non-volatile device (e.g. 9346) that
describes the resources requested by the card. The
Plug and Play resource management software will
arbitrate resources and setup the logical device
configuration registers according to the resource data.
resource data is accessed. Then the Vendor ID and
Unique Serial Number is valid. however, the
checksum byte, when read in this way, is not valid.
For a card that enters Configuration state / Isolation
state, the first read of the Resource Data Register will
report resource data.
Card resource data may only be read from cards in
the Configuration state. A card may get to the
Configuration state by one of two different methods:
1) A card enters the Configuration state in response
to the card "winning" the serial isolation protocol and
having a CSN assigned, or 2) the card receives a
Wake[CSN] command that matches the card CSN.
Card resource data is read by first polling the Status
register and waiting for bit[0] to be set. When this bit is
set, one byte of resource data is ready to be read
from the Resource Data Register. After the Resource
Data Register is read, the Status Register must be
polled before reading the next byte of resource data.
This process will repeat until all resource data is read.
As described above, all Plug and Play cards function
as if both of their serial identifiers and resource data
come from the same serial device. Similarly, the
pointer to the serial device is reset in response to any
Wake[CSN] command. This implies that if a card
enters the Configuration state directly from Sleep
state in response to a Wake[CSN] command, the 9byte serial identifier must be read first before the card
The above operation implies that the hardware is
responsible for accumulating 8 bits of data in the
Resource Data Register. When this operation is
complete, the status bit [0] is set. When a read is
performed on the Resource Data Register, status bit
[0] is cleared, eight more bits are shifted into the
Resource Data Register, and the status bit[0] is set
again.
DM6383 Absolute Maximum Ratings*
*Comments
Power Supply Voltage........................ -0.5V to +7.0V
o
o
Case Operating Temperature............... 0 C to 85 C
o
o
Storage Temperature ...................... -65 C to 150 C
Applied Voltage On Any Pin .....................................
......................................... - 0.5V ≤ VIN ≤ VDD+0.5V
Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
this device. These are stress ratings only. Functional
operation of this device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied or
intended. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
20
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6383 DC Electrical Characteristics (VDD = 5V, GND = 0V; Tc = 0 oC to 85 oC)
Symbol
VDD
IDD
VIH
VIL
ILI
VOH
VOL
CIN
VILRESET
VIHRESET
IOH
IOL
Parameter
Operating Voltage
Operating Current
Input High Voltage
Input Low Voltage
Input Leakage Current
Output High Voltage
Output Low Voltage
Input Capacitance
Reset Schmitt VIL
Reset Schmitt VIH
UD Data Bus Output High Current
UD Data Bus Output Low Current
Min.
4.75
Typ.
5.0
30
Max.
5.25
2.0
+0.8
10
-10
2.4
+0.4
10.0
0.8
2.8
-15.0
24.0
Unit
V
mA
V
V
• A
V
V
pF
V
V
mA
mA
Conditions
VIN = 0, 5.25V
IOH = -0.5mA
IOL = 1.5mA
VOH = 2.4V
VOL = 0.4V
DM6383 AC Electrical Characteristics (VDD = 5V, GND = 0V; Tc = 0 oC to 85 oC)
Symbol
tAW
tWC
tDOW
tDS
tDH
tAR
tRC
tDIW
tDDD
tHZ
Parameter
IOW Delay from Address
Write Cycle
IOW Strobe Width
Data Setup Time
Data Hold Time
IOR Delay from Address
Read Cycle
IOR Strobe Width
Delay from IOR to Data Valid
IOR to Floating Data Delay
Min.
30
280
100
30
30
30
280
125
Typ.
Max.
125
100
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
100pF loading
100pF loading
DM6383 Timing Waveforms
Write Cycle
VALID
A15 - A0
/IOW
tA W
tW C
tD O W
/IOR
t DS
DATA UD7-UD0
t DH
VALID
Read Cycle
VALID
A15 - A0
/IOR
t AR
t RC
t DIW
/IOW
t DDD
DATA UD7-UD0
Final
Version: DM336P-DS-F02
August 15, 2000
t HZ
VALID
21
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
• Chip 2: DM6381/DM6382 ITU-T V.34 TX and RX Digital Signal Processor (TX DSP and
RX DSP) Description
DM6381/82 Description
The DM6381/DM6382 are application specific Digital
Signal Processors (DSP) dedicated to V.34 modem
operation. They are used in pairs. The primary
component of these devices is a 22.43Mips DSP core
processor. The basic clock frequency of this device is
40.32MHz. An internal built PLL circuit is used to
boost the clock from 40.32MHz to 80.64MHz or
89.74MHz. This 80.64MHz/89.74MHz clock is used
as the clock source of DSP core processor. A 16-byte
dual port SRAM is utilized to provide the
communication between DSP and the DM6383.
There are two dedicated serial ports that provide the
link between the DSP and the DM6380. The
DM6381/DM6382 are bonded-out in a 100-pin QFP
package for mass production, and provide the most
economical package.
DM6381/82 Block Diagram
OSCI
OSCO
Timing
Logical & PLL
Program
RAM
ROM
PMA[0:13]
MSCLK
PMD[0:23]
CODEC_CLK
DSP Core
Serial Port
DMA[0:13]
DMD[0:15]
Dual Port
RAM
Data
RAM
DM6381/82 Features
• DM6381 for TX data-pump, DM6382 for RX datapump
• Build in program ROM
• 2 serial ports to interface with codec
22
• 16 byte dual port RAM
• Clock Generator for codec chip and controller chip
• Build in PLL
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
NC
DGND
NC
NC
NC
83
82
81
NC
84
NC
86
85
NC
87
TEST1
NC
TEST2
92
88
DGND
93
89
DGND
94
TEST
FR_SP1
95
V DD
TD_SP1
96
90
RD_SP1
97
91
SCLK
98
TD_SP2
100
99
DM6381/82 Pin Configuration
RD_SP2
1
80
NC
FR_SP2
2
79
NC
A V DD
3
78
NC
OSCO
4
77
NC
OSCI
5
76
/IRQ3
AGND
6
75
/IRQ2
TXDCLK
7
74
/IRQ1
DGND
8
73
/IRQ0
RXDCLK
9
72
NC
CODEC_CLK
10
71
DGND
RXD
11
70
NC
V DD
12
69
/RESET
TXD
13
68
DGND
NC
/URD
14
67
/UWR
15
66
NC
UAR3
16
65
NC
DM6381F/6382F
30
51
NC
Final
Version: DM336P-DS-F02
August 15, 2000
NC
NC
NC
50
NC
MSCLK
49
52
48
29
NC
NC
DGND
NC
53
47
28
46
NC
UD7
NC
54
45
27
NC
NC
UD6
44
55
43
26
42
NC
UD5
NC
56
NC
25
V DD
V DD
UD4
41
57
NC
24
40
NC
UD3
39
58
NC
23
38
NC
UD2
NC
DGND
59
37
60
22
NC
21
UD1
36
UD0
NC
NC
NC
61
35
20
34
NC
/UCS
NC
62
33
19
P0.D
NC
UAR0
32
NC
63
31
64
18
P0.E
17
PO.F
UAR2
UAR1
23
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6381/82 Pin Description
Pin No.
1
Pin Name
RD_SP2
I/O
I
2
FR_SP2
I/O
3
4
5
AVDD
OSCO
OSCI
P
O
I
6
7
AGND
TXDCLK
P
I
8, 29, 60, 68, 71,
84, 94, 95
9
DGND
P
RXDCLK
I
10
11
CODEC_CLK
RXD
O
O
12, 42, 57, 90, 93
13
VDD
TXD
P
I
14
15
16 - 19
/URD
/UWR
UAR3 - UAR0
I
I
I
20
21 - 28
30
/UCS
UD0 - UD7
MSCLK
I
I/O
O
31
32
33
34
35 - 41, 43 - 56,
58, 59, 61 - 67,
70, 72, 77 - 83,
85 - 89
P0.F
P0.E
P0.D
P0.C
NC
O
O
O
O
-
24
Description
Data Input Pin Of Serial Port 2:
The serial data is sampled at the falling edge of the SCLK. The
MSB is coming immediately after falling of FR_SP2 signal.
Frame Signal For Serial Port 2:
This pin keeps at the low state normally and changes it's state
according to the rising edge of the SCLK clock. A high to low
transition initiates a data transfer.
Analog Power For PLL Circuit
Oscillator Output Pin
Oscillator Input Pin:
A 40.32MHz crystal and feedback resister should be connected
between OCSI and OSCO.
Analog Ground For PLL Circuit
Transmit Data Rate Clock:
This pin is used as reference clock of TXD pin.
Digital Ground
Receive Data Rate Clock:
This pin is used as reference clock of RXD pin.
20.16MHz Clock Output For DM6380 Chip
Modem Received Data
Shifted out to the EIA port through this pin according to the rising
edge of RXDCLK.
Digital Power
Modem Transmit Data
Shifted into DM6381/DM6382 from EIA port through this pin at
the rising edge of TXDCLK.
Read Indication Of Dual Port RAM, low active.
Write Indication Of Dual Port RAM, low active.
Dual Port RAM Address Bus Input
This address bus can access 16 bytes dual port RAM.
Dual Port RAM Chip Select Pin, low active.
Data Bus Of The Dual Port RAM
Clock Output Pin For DM6383
The frequency of this clock can be programmed to be either
22.43MHz or 44.87MHz.
Output Port Bit F
Output Port Bit E
Output Port Bit D
Output Port Bit C
No Connection
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6381/82 Pin Description (continued)
Pin No.
69
73
74
75
76
91 - 92
Pin Name
/RESET
/IRQ0
/IRQ1
/IRQ2
/IRQ3
TEST, TEST1
I/O
I
I
I
I
I
I
96
97
FR_SP1
TD_SP1
I/O
O
98
RD_SP1
I
99
100
SCLK
TD_SP2
I
O
Final
Version: DM336P-DS-F02
August 15, 2000
Description
Reset Pin Of DSP Chip, low active.
Interrupt 0 Input
Interrupt 1 Input
Interrupt 2 Input
Interrupt 3 Input
These three pins define the testing mode operation of
DM6381/DM6382 as followed:
When Test=0
Test1
0, PLL output clock is 89.74MHz.
1, PLL output clock is 80.64MHz.
When Test=1:
Reserved for mass production testing mode.
All these 2 pins are pulled low internally.
Frame Signal Of Serial Port 1
Data Output Pin Of Serial Port 1
The serial data is clocked out through this pin according to the rising
edge of SCLK. The MSB is sent immediately after the falling edge of the
FR_SP1 signal.
Data Input Pin Of The Serial Port 1
The serial data is sampled at the falling edge of the SCLK. The MSB is
coming immediately after the falling of FR_SP1 signal.
Reference Clock For Serial Port 1 And Serial Port 2
Data Output Pin Of Serial Port 2
The serial data is clocked out through this pin according to the rising
edge of SCLK. The MSB is sent immediately after the falling edge of the
FR_SP2 signal.
25
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6381/82 Functional Description
1. System Clock
2. Serial Port
a. Reference Oscillator Clock
There are two serial ports to provide the interface with
CODEC chip. The serial port 1 (SP1) transfer 32 bits
in each frame while the serial port 2 can transfer 64
bits in each frame. The frame signal of each serial
port can be configured as either input signal or output
signal by the Serial Port Control Register (SPC).
The reference oscillator is provided by an external
40.32 MHz crystal, this is the clock source of the Data
Pump chipset.
b. DSP Clock
3. Dual Port RAM
This DSP clock is the output of the PLL frequency
synthesizer and its frequency can be selected by
Test1 pin. (see pin description )
This clock is output via the CODEC_CLK Pin as the
reference clock of the codec chip. This clock is
derived from dividing reference oscillator clock by
two.
The 16 X 8 dual port RAM allows easy system
expansion by adding another DSP or micro-processor.
Address 2000h ~ 200Fh are reserved for this dual
port RAM. The 8 bits dual port RAM data correspond
to the MSBs of the data bus (bit 15 ~ bit 8) of the DSP
core. Upon reading the dual port RAM, the 8 lsb
contents (bit 7 to bit 0) are all 0. For the convenience
of description, the micro-controller port is referred to
as B port and the DSP port is referred to as A port.
d. MSCLK Clock
4. Interrupt
This clock is derived from dividing the DSP clock by 2
or 4, the divider is programmed by DIV bit
(configuration register bit 14 ) as followed:
The DSP core provides 4 nested interrupt inputs:
IRQ3, IRQ2, IRQ1, IRQ0. IRQ3 is the highest priority
input and IRQ0, the lowest. In the V.34 and V.32
application, the IRQ3, IRQ2 and IRQ1 are defined as
external interrupt triggered from the pin IRQ3B,
IRQ2B, IRQ1B respectively.
c. CODEC Clock
Config Reg bit 14
0
1
Divider
2
4
DM6381/82 Absolute Maximum Ratings*
*Comments
Power supply voltage ......................... -0.5V to +7.0V
o
o
Case operating temperature.................. 0 C to 85 C
o
o
Storage temperature ........................ -65 C to 150 C
Applied voltage on any pin .......................................
.......................................... -0.5V ≤ VIN ≤ VDD+0.5V
Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
this device. These are stress ratings only. Functional
operation of this device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied or
intended. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
26
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6381/82 DC Electrical Characteristics (VDD = 5V, GND = 0V; Tc = 0 oC to 85 oC)
Symbol
VDD
IDD
VIH
VIL
ILI
VOH
VOL
Parameter
Operating Voltage
Operating Current
Input High Voltage
Input Low Voltage
Input Leakage Current
Output High Voltage
Output Low Voltage
Min.
4.75
Typ.
5.0
85
Max.
5.25
100
Unit
V
mA
V
V
uA
V
V
2.2
+0.8
10
-10
2.4
+0.4
Conditions
VIN = 0, 5.25V
IOH = 2.5mA
IOL = 2.5mA
DM6381/82 AC Electrical Characteristics
(VDD = 5V, GND = 0V; Tc = 0 oC to 85 oC, PLL out frequency = 90MHz, CL = 50pF)
a. Serial Port Timing
Symbol
1
2
3
4
5
6
7
8
9
10
Parameter
SCLK Period
SCLK Low Width
SCLK High Width
SCLK Rise Time
SCLK Fall Time
Frame Delay Time
Frame To SCLK Hold
RD Valid Before SCLK Low
RD Hold Time
TD Delay Time
Min.
49
20
20
Typ.
Max.
5
5
20
17
5
15
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
4
5
1
2
3
SCLK
6
7
FR_SP1
FR_SP2
RD_SP1
RD_SP2
TD_SP1
TD_SP2
Final
Version: DM336P-DS-F02
August 15, 2000
8
First Bus
10
First Bus
9
Last Bus
11
Last Bus
Hiz
27
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
b. Dual Port RAM Timing
Symbol
1
2
3
4
5
6
7
8
9
10
11
Parameter
/URD Read Period
Address Valid Before /URD Low
/URD to /UCS Delay Time
Data Hold Time After /URD High
Data Bus High Z After /URD High
/URD Low To Data Valid
/UWR Period
Data Setup Time /UWR High
Address Valid Before /UWR Low
/UWR To /UCS Delay
Data Hold Time After /UWR High
Min.
100
50
Typ.
Max.
7
4
20
25
100
50
50
7
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
UAR[3..0]
/UCS
/URD
2
3
1
4
UD[0..7]
6
28
5
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
• Chip 3 : DM6380 Analog Front End (AFE) Description
DM6380 Description
The DM6380 is a single chip Analog Front End (AFE)
designed to implement voice grade modem up to
33600bps. It is used as a portion of a complete
modem device set. The AFE converts the analog
signal into digital form and transfers the digital data to
the DSP through the serial port. All the clock
information needed in a modem device is also
generated in this device. The differential analog
outputs are provided to acquire the maximum output
signal level. An audio monitor whose volume is
programmable is built in to monitor the on-line signal.
Inside the device, a 16-bit ADC and a 16-bit DAC with
over-sampling and noise-shaping techniques is
implemented to maximize performance for high speed
modem. It offers wide-band transmit and receive
filters so that the voice band signal is transmitted or
received without amplitude distortion and with
minimum group delay. In order to support the multimode modem standards, such as V.34, V.32bis, V.32,
V.22bis, V.22, V.23, V.21, Bell 212A, Bell 103, V.17,
V.29, V.27ter, the programmable baud and data rate
clock generators are provided. For the asymmetric
channel usage, the transmit and receive clock
generators are independent. In order to provide the
echo-cancel capability, the receive clock is
synchronized with the transmit clock and the best
receive timing sample is reconstructed by a
reconstruction filter. Transmit Digital Phase Lock
Loop (DPLL) is self-tuning to provide the master,
slave or free-running mode for the data terminal
interface. A software programmable receive DPLL
that is step-controllable by the host DSP is
implemented to get the best samples for the relevant
signal processing.
DM6380 Block Diagram
RxSCLK
Rx Clock
System
RxDCLK
TxSCLK*2
Tx Clock
System
TxDCLK
ExtCLK
CLKIN
SCLK
Divider
Control
Registers
RFS
DOR
Digital
Interface
DIR
Tx Filter &
DAC
LPF &
Attenuator
TFS
DOT
Voltage Reference
DIT
Rx Filter &
ADC
0/-6 dB
Audio Amplifier
Digital
Reconstruction
Filter
Final
Version: DM336P-DS-F02
August 15, 2000
TxA1
TxA2
VREFP
VCM
VREFN
RxIN
SPKR
Power-on
Detector
29
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6380 Features
•
•
•
•
•
• Dual synchronous serial interface to host Digital
Signal Processor (DSP)
• Separate transmit digital phase lock loop and
receive digital phase lock loop
• Full echo cancellation capability
• Differential analog output
• Single-ended analog input
• Single power supply voltage : +5V
• Low power consumption
16-bit • - A/D and D/A converters
Dynamic range : 86dB
Total harmonic distortion : -86dB
Separate transmit and receive clocks
Symbol rate : 75, 300, 600, 1200, 1600, 2400,
2743, 2800, 3000, 3200, 3429Hz
• Data rate : 75, 300, 600, 1200, 2400, 4800, 7200,
9600, 12000, 14400, 16800, 19200, 21600, 24000,
26400, 28800, 33600bits per second
30
RFS
RXSCLK
VDD
RXDCLK
SPKR
AVDDR
RXIN
4
3
2
1
28
27
26
DM6380 Pin Configuration
DOR
5
25
AGNDT
DIR
6
24
VREFP
DGND
7
23
VCM
22
VREFN
DM6380L
18
TXA2
AVDDT
19
17
11
Vr
TFS
16
TXA1
EXTCLK
20
15
10
/RESET
DIT
14
AGNDR
CLKIN
21
TXDCLK
9
13
DOT
12
8
TXSCLK*2
SCLK
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6380 Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin Name
RXDCLK
VDD
RXSCLK
RFS
DOR
DIR
DGND
SCLK
DOT
DIT
TFS
TXSCLK*2
TXDCLK
CLKIN
/RESET
EXTCLK
Vr
AVDDT
TXA2
TXA1
AGNDR
VREFN
VCM
VREFP
AGNDT
RXIN
AVDDR
SPKR
I/O
O
P
O
I
O
I
P
O
O
I
I
O
O
I
I
I
O
I
O
O
P
O
O
O
P
I
I
O
Description
Receive Data Clock
Digital Power
Receive Sample Clock
Receive Frame Synchronization
Data Output For Receiver
Data Input For Receiver
Digital Ground
Serial Clock Synchronized With All Serial Data
Data Output For Transmitter
Data Input For Transmitter
Transmit Frame Synchronization
Transmit Sample Clock * 2
Transmit Data Clock
Master Clock Input (20.16MHz = 40.32MHz / 2 )
Codec Reset Input
External Transmit Data Clock
Internal Reference Voltage. Connect 0.1uF to DGND
Analog VDD For The Transmitter Analog Circuitry (+5VDC)
Transmit Negative Analog Output
Transmit Positive Analog Output
Analog Receiver Circuitry Signal Return Path
Negative Reference Voltage, VCM - 1V
Common Mode Voltage Output, 2.5V
Positive Reference Voltage, VCM + 1V
Analog Transmitter Circuitry Signal Return Path
Receive Analog Input
Analog VDD For The Receiver Analog Circuitry (+5VDC)
Speaker Driver
DM6380 Functional Description
In this chip, we could roughly divide it into two major
parts : digital portion and analog portion. The
functional blocks are described separately in this
section. The analog circuits include a sigma-delta
modulator/demodulator, decimation/interpolation
filters, a speaker driver, low-pass filter and certain
logic circuits. The digital circuits is composed of Tx/Rx
clock generator/PLL, serial port, serial/parallel
conversions and control registers. All the clock
information the analog circuits need should be
provided by the digital clock system since the best
sampling instant of A/D and D/A depends on the
received signal and transmit signals. The data format
of A/D and D/A is 2's complement.
Final
Version: DM336P-DS-F02
August 15, 2000
Master clock (FQ) is obtained from an external signal
connected to CLKIN. The different transmit and
receive clocks are obtained by master clock
frequency division in several programmable counters.
The Tx and Rx clocks can be synchronized on
external signals by performing the phase shifts in the
frequency division process. Two independent digital
phase locked loops are implemented using this
principle, one for transmit clock system, the other,
receive clock. The tracking of the transmit clock is
automatically done by the transmit DPLL circuit. The
receive DPLL circuit is controlled by the host
processor and it is actually an adjustable phase
shifter.
31
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6380 Absolute Maximum Ratings*
*Comments
Power supply voltage ......................... -0.5V to +7.0V
o
o
Case operating temperature.................. 0 C to 85 C
o
o
Storage temperature ........................ -65 C to 150 C
Applied voltage on any pin .......................................
.......................................... -0.5V ≤ VIN ≤ VDD+0.5V
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only. Functional
operation of this device at these or any other
conditions above those indicated in the operational
section of this specification is not implied or intended.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
DM6380 DC Electrical Characteristics (VDD = 5V, Tc = 0 oC to 85 oC)
Symbol
VDD
VCM
IDD
VIL
VIH
VOL
VOH
II
CIN
VREF
VCMD_OU
T
VDIF_OUT
VOFF_OU
T
RIN
ROUT
RL
CL
32
Parameter
Operating Voltage
Output Common Mode Voltage
Supply Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Current
Input Capacitance
Differential Reference Voltage
Output
Output Common Mode Offset
Differential Output Voltage
Differential Output DC Offset
Voltage
Input Resistance RxIN
Output Resistance TxA1, TxA2,
SPKR
Load Resistance TxA1, TxA2,
SPKR
Load Capacitance TxA1, TxA2,
SPKR
Min.
4.75
Typ.
5
2.5
25
Max.
5.25
2.1
Unit
V
V
mA
V
V
V
V
µA
pF
V
-200
200
mV
=(TxA1+TxA2)/2-VCM
3
*VREF
-100
3
*VREF
100
V
TxA1-TxA2 ≤ 3*VREF
mV
2
kΩ
kΩ
0.8
2.2
0.4
2.4
-10
1.9
±1
5
2
10
100
1
20
Conditions
VI=VDD or VI=GND
VDC (TXA1)-VDC (TXA2)
kΩ
50
pF
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6380 AC Characteristics (VDD = 5V, Tc= 0 oC to 85 oC)
Serial Port Timing
Symbol
1
2
3
4
5
6
7
8
9
10
11
Parameter
SCLK Period
SCLK Low Width
SCLK High Width
SCLK Rise Time
SCLK Fall Time
FS To SCLK Setup
FS To SCLK Hold
DI To SCLK Setup
DI To SCLK Hold
SCLK High To DO Valid
SCLK To DO Hiz
Min.
49
24
24
Typ.
Max.
5
5
17
17
5
5
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
4
5
1
SCLK
2
3
6
7
FS
DI
DO
8
9
First Bus
10
Last Bus
11
First Bus
Last Bus
Hiz
DM6380 Performance
o
o
(VDD= 5V, Tc= 0 C to 85 C, FQ= 20.16MHz, Measurement Band= 220Hz to 3.6KHz, RX DPLL Free Running)
Symbol
Gabs
THD
DR
PSRR
CTxRx
Parameter
Absolute Gain At 1KHz
Total Harmonic Distortion
Dynamic Range
Power Supply Rejection
Ratio
Crosstalk
Final
Version: DM336P-DS-F02
August 15, 2000
Min.
-0.5
Typ.
Max.
0.5
-84
Unit
dB
dB
86
50
dB
dB
Conditions
RX signal: VIN= 2.5 VPP, f = 1KHz
Tx signal: VOUT (diff)= 5 VPP, f =
1KHz
f = 1KHz
f = 1KHz, VAC = 200m VPP
95
dB
Transmit channel to receive channel
33
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
Application Circuit (For Reference Only)
34
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
Application Circuit (For Reference Only)
Final
Version: DM336P-DS-F02
August 15, 2000
35
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
Application Circuit (For Reference Only)
36
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
Application Circuit (For Reference Only)
Final
Version: DM336P-DS-F02
August 15, 2000
37
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
Package Information
QFP 100L Outline Dimensions
unit: inches/mm
HD
D
80
30
51
F
E
1
31
e
GE
81
HE
100
b 50
GD
c
~~
D
See Detail F
Seating Plane
y
A
A1
A2
GD
L
L1
Symbol
Dimensions In Inches
Dimensions In mm
3.30 Max.
A
0.130 Max.
A1
0.004 Min.
0.10 Min.
A2
0.112Ř 0.005
2.85Ř 0.13
b
0.012 +0.004
-0.002
0.31 +0.10
-0.05
c
0.006 +0.004
-0.002
0.15 +0.10
-0.05
D
0.551Ř 0.005
14.00Ř 0.13
E
0.787Ř 0.005
20.00Ř 0.13
e
0.026 Ř 0.006
0.65Ř 0.15
F
0.742 NOM.
18.85 NOM.
GD
0.693 NOM.
17.60 NOM.
GE
0.929 NOM.
23.60 NOM.
HD
0.740Ř 0.012
18.80Ř 0.31
HE
0.976Ř 0.012
24.79Ř 0.31
L
0.047Ř 0.008
1.19Ř 0.20
L1
0.095Ř 0.008
2.41Ř 0.20
y
0.006 Max.
0.15 Max.
θ
0° ~ 12°
0° ~ 12°
Detail F
Note:
1. Dimensions D&E do not include resin fins.
2. Dimensions GD & GE are for PC Board surface mount pad pitch
design reference only.
3. All dimensions are based on metric system.
38
Final
Version: DM336P-DS-F02
August 15, 2000
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
PLCC 28L Outline Dimensions
unit: inches/mm
HD
D
1 28
26
25
11
19
GE
E
5
HE
4
c
18
e
A1
b
A
A2
L
12
D
b1
Seating Plane
GD
y
Symbol
Dimensions In Inches
Dimensions In mm
A
0.185 Max.
4.70 Max.
A1
0.020 Min.
0.51 Min.
A2
0.150Ř 0.005
3.81Ř 0.13
b1
0.028 +0.004
-0.002
0.71 +0.10
-0.05
b
0.018 +0.004
-0.002
0.46 +0.10
-0.05
c
0.010 +0.004
-0.002
0.25 +0.10
-0.05
D
0.453Ř 0.010
11.51Ř 0.25
E
0.453Ř 0.010
11.51Ř 0.25
e
0.050Ř 0.006
1.27Ř 0.15
GD
0.410Ř 0.020
10.41Ř 0.51
GE
0.410Ř 0.020
10.41Ř 0.51
HD
0.490Ř 0.010
12.45Ř 0.25
HE
0.490Ř 0.010
12.45Ř 0.25
L
0.100Ř 0.010
2.54Ř 0.25
y
0.006 Max.
0.15 Max.
Note:
1. Dimensions D and E do not include resin fins.
2. Dimensions GD & GE are for PC Board surface mount pad pitch
design reference only.
3. All dimensions are based on metric system.
Final
Version: DM336P-DS-F02
August 15, 2000
39
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
application circuits illustrated in this document are for
reference purposes only.
Ordering Information
Part Number
DM6380L
DM6381F
DM6382F
DM6383F
Pin Count
28
100
100
100
Package
PLCC
QFP
QFP
QFP
Disclaimer
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
DAVICOM Semiconductor are covered by the
warranty and patent indemnification provisions
stipulated in the terms of sale only. DAVICOM makes
no warranty, express, statutory, implied or by
description regarding the information in this
publication or regarding the information in this
publication or regarding the freedom of the described
chip(s) from patent infringement. FURTHER,
DAVICOM MAKES NO WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE. DAVICOM deserves the right to halt
production or alter the specifications and prices at any
time without notice. Accordingly, the reader is
cautioned to verify that the data sheets and other
information in this publication are current before
placing orders. Products described herein are
intended for use in normal commercial applications.
Applications involving unusual environmental or
reliability requirements, e.g. military equipment or
medical life support equipment, are specifically not
recommended without additional processing by
DAVICOM for such applications. Please note that
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acknowledgment govern all sales by DAVICOM.
DAVICOM will not be bound by any terms
inconsistent with these unless DAVICOM agrees
otherwise in writing. Acceptance of the buyer’s
orders shall be based on these terms.
Company Overview
DAVICOM Semiconductor, Inc. develops and
manufactures integrated circuits for integration into
data communication products. Our mission is to
design and produce IC products that re the industry’s
best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal, we
have built an organization that is able to develop
chipsets in response to the evolving technology
requirements of our customers while still delivering
products that meet their cost requirements.
Products
We offer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards. Our currently
available and soon to be released products are based
on our proprietary designs and deliver high quality,
high performance chipsets that comply with modem
communication standards and Ethernet networking
standards.
Contact Windows
For additional information about DAVICOM products, contact the sales department at:
Headquarters
Hsin-chu Office:
3F, No. 7-2, Industry E. Rd. IX,
Science-Based Industrial Park,
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TEL: 886-3-579-8797
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Office:
8F, No. 3, Lane 235, Bao-chiao
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1135 Kern Ave.
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TEL: 408-736-8600
FAX: 408-736-8688
Email: [email protected]
WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for
sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage
structure, performance and/or function.
Final
Version: DM336P-DS-F02
August 15, 2000
40