Fairchild DM74ALS652 Octal 3-state bus transceiver and register Datasheet

Revised June 2001
DM74ALS652
Octal 3-STATE Bus Transceiver and Register
General Description
Features
This device incorporates an octal transceiver and an octal
D-type register configured to enable transmission of data
from bus to bus or internal register to bus.
■ Switching specifications at 50 pF
This bus transceiver features totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and
increased high level logic drive provide this device with the
capability of being connected directly to and driving the bus
lines in a bus organized system without need for interface
or pull-up components. They are particularly attractive for
implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ Switching specifications guaranteed over full temperature and VCC range
■ 3-STATE buffer-type outputs drive bus lines directly
■ Independent registers and enables for A and B buses
■ Multiplexed real-time and stored data
The registers in the DM74ALS652 are edge-triggered
D-type flip-flops. On the positive transition of the clock
(CAB or CBA), the input data is stored into the appropriate
register. The CAB input controls the transfer of data into
the A register and the CBA input controls the B register.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A LOW
input level selects real-time data and a HIGH level selects
stored data. The select controls have a “make before
break” configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition
between stored and real-time data.
The enable (GAB and GBA) control pins provide four
modes of operation: real-time data transfer from bus A to
B, real-time data transfer from bus B to A, real-time bus A
and/or B data transfer to internal storage, or internal stored
data transfer to bus A and/or B.
Ordering Code:
Order Number
Package Number
DM74ALS652WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Description
DM74ALS652NT
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2001 Fairchild Semiconductor Corporation
DS009174
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DM74ALS652 Octal 3-STATE Bus Transceiver and Register
October 1986
DM74ALS652
Function Table
Inputs
Data I/O (Note 1)
Operation or Function
GAB
GBA
X
L
CAB
CBA
SAB
SBA
A1 thru A8
B1 thru B8
H
↑
H/L
X
X
Input
X
H/L
↑
X
X
Not Specified
Input
Store B, Hold A
L
H
↑
↑
X
X
Input
Input
Store A and B Data
L
H
H/L
H/L
X
X
Input
Input
Isolation, Hold Storage
L
L
X
X
X
L
Output
Input
Real-Time B Data to A Bus
L
L
X
H/L
X
H
Output
Input
Stored B Data to A Bus
H
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
H
H
↑
↑
X
X
Input
Output
Stored A Data to B Bus
H
H
↑
↑
X
(Note 2)
X
Input
Output
Store A in both Registers
L
L
↑
↑
X
X
(Note 2)
Output
Input
Store B in both Registers
H
L
H or L
H or L
H
H
Output
Output
Not Specified Store A, Hold B
Stored A Data to B Bus and
Stored B Data to A Bus
H = HIGH Logic Level
L = LOW Logic Level
X = Don’t Care (Either LOW or HIGH Logic Levels, including transitions)
H/L = Either LOW or HIGH Logic Level excluding transitions
↑ = Positive-going edge of pulse
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Note 2: Select control = L; clocks can occur simultaneously
Select control = H; clocks must be staggered in order to load both registers.
Logic Diagram
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2
Supply Voltage
7V
Input Voltage
Control Inputs
7V
I/O Ports
5.5V
Note 3: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
0°C to +70°C
Operating Free-Air Temperature Range
−65°C to +150°C
Storage Temperature Range
Typical θJA
N Package
44.5°C/W
M Package
80.5°C/W
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
4.5
5
5.5
Units
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
0.8
V
IOH
HIGH Level Output Current
−15
mA
V
2
V
IOL
LOW Level Output Current
fCLK
Clock Frequency
tW
Pulse Duration, Clocks LOW or HIGH
12.5
ns
tSU
Data Setup Time, A before CAB or
10↑
ns
0↑
ns
0
24
mA
40
MHz
B before CBA (Note 4)
tH
Data Hold Time, A after CAB or
B after CBA (Note 4)
TA
Free Air Operating Temperature
0
°C
70
Note 4: ↑ = with reference to the LOW-to-HIGH transition of the respective clock.
Electrical Characteristics
over recommended free air temperature range
Symbol
Parameter
Test Conditions
VIK
Input Clamp Voltage
VCC = Min, II = −18 mA
VOH
HIGH Level
VCC = 4.5V to 5.5V
IOH = −0.4 mA
Output Voltage
VCC = Min
IOH = −3 mA
IOH = Max
VOL
LOW Level
VCC = Min
Output Voltage
II
Input Current at Maximum
VCC = Max
Input Voltage
Min
Typ
Max
Units
−1.2
V
VCC − 2
2.4
3.2
V
2
IOL = 12 mA
0.25
0.4
IOL = 24 mA
0.35
0.5
IOL = 48 mA
0.35
0.5
I/O Ports, VI = 5.5V
100
Control Inputs, VI = 7V
100
IIH
HIGH Level Input Current
VCC = Max, VI = 2.7V, (Note 5)
IIL
LOW Level
VCC = Max,
Control Inputs
−200
Input Current
VI = 0.4V (Note 5)
I/O Ports
−200
IO
Output Drive Current
VCC = Max, VO = 2.25V
ICC
Supply Current
VCC = Max
20
−30
−112
Outputs HIGH
47
76
Outputs LOW
55
88
Outputs Disabled
55
88
V
µA
µA
µA
mA
mA
Note 5: For I/O ports the 3-STATE output currents (IOZH and IOZL ) are included in the IIH and IIL parameters.
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DM74ALS652
Absolute Maximum Ratings(Note 3)
DM74ALS652
Switching Characteristics
over recommended operating free air temperature range (Note 6)
Symbol
tPLH
tPHL
tPLH
Parameter
Conditions
VCC = 4.5V to 5.5V,
LOW-to-HIGH Level Output
CL = 50 pF,
Propagation Delay Time
R1 = R2 = 500Ω,
CBA or CAB
HIGH-to-LOW Level Output
TA = Min to Max
to A or B
tPHL
tPLH
tPHL
tPZH
Propagation Delay Time
A or B to
B or A
Propagation Delay Time
A or B to
B or A
tPHZ
LOW-to-HIGH Level Output
SBA or SAB
(with A or B LOW) (Note 6)
to A or B
HIGH-to-LOW Level Output
SBA or SAB
(with A or B LOW) (Note 6)
to A or B
LOW-to-HIGH Level Output
SBA or SAB
(with A or B HIGH) (Note 6)
to A or B
tPHZ
HIGH-to-LOW Level Output
SBA or SAB
(with A or B HIGH) (Note 6)
to A or B
Output Enable Time
GBA to
A
Output Enable Time
GBA to
to LOW Level Output
A
Output Disable Time
GBA to
A
Output Disable Time
GBA to
A
Output Enable Time
GAB to
B
Output Enable Time
GAB to
to LOW Level Output
B
Output Disable Time
GAB to
from HIGH Level Output
tPLZ
10
30
ns
5
17
ns
5
18
ns
3
12
ns
12
35
ns
6
20
ns
6
25
ns
5
20
ns
3
17
ns
5
18
ns
1
10
ns
2
16
ns
6
22
ns
6
18
ns
1
10
ns
2
16
ns
Propagation Delay Time
to HIGH Level Output
tPZL
Units
Propagation Delay Time
from LOW Level Output
tPZH
Max
Propagation Delay Time
from HIGH Level Output
tPLZ
Min
Propagation Delay Time
to HIGH Level Output
tPZL
CBA or CAB
to A or B
HIGH-to-LOW Level Output
tPLH
To (Output)
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
From (Input)
B
Output Disable Time
GAB to
from LOW Level Output
B
Note 6: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
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DM74ALS652
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M24B
5
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DM74ALS652 Octal 3-STATE Bus Transceiver and Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
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1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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