Fairchild DM74ALS74 Dual d positive-edge-triggered flip-flop with preset and clear Datasheet

Revised February 2000
DM74ALS74A
Dual D Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
Features
The DM74ALS74A contains two independent positive
edge-triggered flip-flops. Each flip-flop has individual D,
clock, clear and preset inputs, and also complementary Q
and Q outputs.
■ Switching specifications at 50 pF
Information at input D is transferred to the Q output on the
positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the HIGH or LOW
level, the D input signal has no effect.
■ Switching specifications guaranteed over full temperature and VCC range
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ Functionally and pin-for-pin compatible with Schottky
and LS TTL counterpart
■ Improved AC performance over LS74 at approximately
half the power
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
Ordering Code:
Order Number
Package Number Package Description
DM74ALS74AM
M14A
DM74ALS74ASJ
M14D
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS74AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
PR
CLR
CLK
D
Q
L
H
X
X
H
Q
L
H
L
X
X
L
H
H (Note 1)
L
L
X
X
H (Note 1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
L = LOW State
H = HIGH State
X = Don't Care
↑ = Positive Edge Transition
Q0 = Previous Condition of Q
Note 1: This condition is nonstable; it will not persist when preset and clear
inputs return to their inactive (HIGH) level. The output levels in this condition are not guaranteed to meet the VOH specification.
© 2000 Fairchild Semiconductor Corporation
DS006109
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DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
September 1986
DM74ALS74A
Logic Diagram
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Supply Voltage
7V
Input Voltage
7V
0°C to +70°C
Operating Free Air Temperature Range
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
−65°C to +150°C
Storage Temperature Range
Typical θJA
N Package
87.0°C/W
M Package
117.0°C/W
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
4.5
5
5.5
V
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
0.8
V
mA
2
V
IOH
HIGH Level Output Current
−0.4
IOL
LOW Level Output Current
8
mA
fCLK
Clock Frequency
34
MHz
tW(CLK)
Width of Clock Pulse
tW
Pulse Width
Preset & Clear
tSU
Data Setup Time
0
HIGH
14.5
ns
LOW
14.5
ns
LOW
14.5
ns
Data
15↑ (Note 3)
PRE or CLR
tH
Data Hold Time
TA
Free Air Operating Temperature
ns
10↑ (Note 3)
Inactive
0↑ (Note 3)
0
ns
70
°C
Note 3: The (↑) arrow indicates the positive edge of the Clock is used for reference.
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DM74ALS74A
Absolute Maximum Ratings(Note 2)
DM74ALS74A
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.
Symbol
Parameter
Conditions
VIK
Input Clamp Voltage
VCC = 4.5V, II = −18 mA
VOH
HIGH Level
IOH = −0.4 mA
Output Voltage
VCC = 4.5V to 5.5V
LOW Level
VCC = 4.5V
Output Voltage
VIH = 2V
VOL
II
IIH
IIL
Min
Typ
Max
Units
−1.5
V
VCC − 2
IOL = 8 mA
V
0.35
0.5
Input Current @
VCC = 5.5V,
Clock, D
0.1
Max Input Voltage
VIH = 7V
Preset, Clear
0.2
HIGH Level
VCC = 5.5V,
Clock, D
20
Input Current
VIH = 2.7V
Preset, Clear
40
LOW Level
VCC = 5.5V,
Clock, D
−0.2
Input Current
VIL = 0.4V
Preset, Clear (Note 5)
−0.4
IO
Output Drive Current
VCC = 5.5V, VO = 2.25V
ICC
Supply Current
VCC = 5.5V (Note 4)
−30
2.4
V
mA
µA
mA
−112
mA
4
mA
Note 4: ICC is measured with D, CLK and PRESET grounded, then with D, CLK and CLEAR grounded.
Note 5: IIL PRE and CLR pins not guaranteed to meet specifications with both PRE and CLK LOW.
Switching Characteristics
over recommended operating free air temperature range.
Parameter
Conditions
From
To
Min
Max
Units
fMAX
VCC = 4.5V to 5.5V
34
tPLH
RL = 500Ω
3
13
ns
tPHL
CL = 50 pF
5
15
ns
5
16
ns
5
18
ns
tPLH
tPHL
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Preset or Clear
Clock
Q or Q
Q or Q
4
MHz
DM74ALS74A
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M14A
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DM74ALS74A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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