Fairchild DM74AS161N Synchronous 4-bit counter with asynchronous clear . synchronous 4-bit counter Datasheet

Revised March 2000
DM74AS161 • DM74AS163
Synchronous 4-Bit Counter with Asynchronous Clear •
Synchronous 4-Bit Counter
General Description
These synchronous presettable counters feature an internal carry look ahead for application in high speed counting
designs. The DM74AS161 and DM74AS163 are 4-bit
binary counters. The DM74AS161 clear asynchronously,
while the DM74AS163 clear synchronously. The carry output is decoded to prevent spikes during normal counting
mode of operation. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that outputs
change coincident with each other when so instructed by
count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock)
counters. A buffered clock input triggers the four flip-flops
on the rising (positive-going) edge of the clock input waveform.
These counters are fully programmable, that is, the outputs
may each be preset to either level. As presetting is synchronous, setting up a low level at the LOAD input disables
the counter and causes the outputs to agree with set up
data after the next clock pulse regardless of the levels of
enable input. LOW-to-HIGH transitions at the LOAD input
are perfectly acceptable regardless of the logic levels on
the clock or enable inputs.
The DM74AS161 clear function is asynchronous. A low
level at the clear input sets all four of the flip-flop outputs
LOW regardless of the levels of clock, load or enable
inputs. This counter is provided with a clear on power-up
feature. The DM74AS163 clear function is synchronous;
and a low level at the clear input sets all four of the flip-flop
outputs LOW after the next clock pulse, regardless of the
levels of enable inputs. This synchronous clear allows the
count length to be modified easily, as decoding the maximum count desired can be accomplished with one external
NAND gate. The gate output is connected to the clear input
to synchronously clear the counter to all LOW outputs.
LOW-to-HIGH transitions at the clear input of the
DM74AS163 is also permissible regardless of the levels of
logic on the clock, enable or load inputs.
The carry look ahead circuitry provides for cascading
counters for n bit synchronous application without additional gating. Instrumental in accomplishing this function
are two count-enable inputs (P and T) and a ripple carry
output. Both count-enable inputs must be HIGH to count.
The T input is fed forward to enable the ripple carry output.
The ripple carry output thus enabled will produce a high
level output pulse with a duration approximately equal to
the high level portion of QA output. This high level overflow
ripple carry pulse can be used to enable successive cascaded stages. HIGH-to-LOW level transitions at the enable
P or T inputs of the DM74AS161 and DM74AS163, may
occur regardless of the logic level on the clock.
The DM74AS161 and DM74AS163 feature a fully independent clock circuit. Changes made to control inputs (enable
P or T, or load) that will modify the operating mode will
have no effect until clocking occurs. The function of the
counter (whether enabled, disabled, loading or counting)
will be dictated solely by the conditions meeting the stable
set-up and hold times.
Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full temperature and VCC range
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
■ Improved AC performance over Schottky and low power
Schottky counterparts
■ Synchronously programmable
■ Internal look ahead for fast counting
■ Carry output for n-bit cascading
■ Synchronous counting
■ Load control line
■ ESD inputs
Ordering Code:
Order Number
DM74AS161M
Package Number
Package Description
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74AS161N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74AS163M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74AS163N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation
DS006291
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DM74AS161 • DM74AS163 Synchronous 4-Bit Counter with Asynchronous Clear • Synchronous 4-Bit Counter
April 1984
DM74AS161 • DM74AS163
Connection Diagram
Logic Diagrams
DM74AS161
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2
DM74AS161 • DM74AS163
DM74AS163
3
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DM74AS161 • DM74AS163
Absolute Maximum Ratings(Note 1)
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
0°C to +70°C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
−65°C to +150°C
Typical θJA
N Package
71.5°C/W
M Package
101.0°C/W
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
4.5
5
5.5
Units
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
0.8
V
IOH
HIGH Level Output Current
−2
mA
IOL
LOW Level Output Current
fCLK
Clock Frequency
tSU
tSETUP, Set-Up Time
Set-up 1
2
0
V
V
20
mA
75
MHz
Data; A, B, C, D
8
En P, En T
8
ns
LOAD
8
ns
CLEAR (Only for
LOW
12
DM74AS163)
HIGH
9
8
CLEAR
ns
ns
ns
(Only for DM74AS161)
tH
tHOLD, Hold Time
Hold 0
Data; A, B, C, D
0
ns
En P, En T
0
ns
LOAD
0
ns
CLEAR (Only for DM74AS163)
0
ns
CLEAR
0
ns
(Only for DM74AS161)
tWCLK
Width of Clock Pulse
tWCLR
Width of Clear Pulse, (DM74ASAS161 LOW)
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4
6.7
ns
8
ns
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C
Symbol
Parameter
Conditions
VIK
Input Clamp Voltage
VCC = 4.5V, II = −18 mA
VOH
HIGH Level
IOH = −2 mA,
Output Voltage
VCC = 4.5 to 5.5V
VOL
II
IIH
IIL
Min
Typ
Max
Units
−1.2
V
VCC − 2
V
LOW Level
VCC = 4.5V,
Output Voltage
IOL = 20 mA
Input Current @ Max
VCC = 5.5V,
LOAD
0.3
Input Voltage
VIH = 7V
ENT
0.2
Others
0.1
HIGH Level Input Current
LOW Level Input Current
0.35
0.5
VCC = 5.5V,
LOAD
60
VIH = 2.7V
ENT
40
Others
20
VCC = 5.5V,
LOAD
−0.5
VIL = 0.4V
ENT
−1
IO (Note 2)
Output Drive Current
VCC = 5.5V, VO = 2.25V
Supply Current
VCC = 5.5V
mA
µA
mA
−0.5
Others
ICC
V
−30
35
−112
mA
53
mA
Note 2: The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit output current, I OS.
Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
fMAX
Maximum Clock Frequency
VCC = 4.5V to 5.5V
tPHL
Propagation Delay Time
RL = 500Ω
HIGH-to-LOW Level Output
CL = 50 pF
tPLH
From
To
Min
Max
75
Units
MHz
Clock
Ripple Carry
2
12.5
ns
Clock
Ripple Carry
1
8
ns
Clock
Ripple Carry
3
16.5
ns
Clock
Any Q
1
7
ns
Clock
Any Q
2
13
ns
En T
Ripple Carry
1.5
9
ns
En T
Ripple Carry
1
8.5
ns
Any Q
2
13
ns
Ripple Carry
2
12.5
ns
Propagation Delay Time
LOW-to-HIGH Level Output
with Load HIGH
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
with Load LOW
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPHL
Propagation Delay Time
CLEAR
HIGH-to-LOW Level Output
tPHL
(DM74AS161)
Propagation Delay Time
CLEAR
HIGH-to-LOW Level Output
(DM74AS161)
5
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DM74AS161 • DM74AS163
Electrical Characteristics
DM74AS161 • DM74AS163
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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6
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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DM74AS161 • DM74AS163 Synchronous 4-Bit Counter with Asynchronous Clear • Synchronous 4-Bit Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
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