Fairchild DM74AS74SJX Dual d-type positive-edge-triggered flip-flop with preset and clear Datasheet

Revised March 2000
DM74AS74
Dual D-Type Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
Features
The AS74 is a dual edge-triggered flip-flops. Each flip-flop
has individual D, clock, clear and preset inputs, and also
complementary Q and Q outputs.
■ Switching specifications at 50 pF
Information at input D is transferred to the Q output on the
positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the HIGH or LOW
level, the D input signal has no effect.
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of LOW level signal.
■ Switching specifications guaranteed over full temperature and VCC range
■ Functionally and pin-for-pin compatible with Schottky
and LS TTL counterpart
■ Improved AC performance over S74 at approximately
half the power
Ordering Code:
Order Number
Package Number
Package Description
DM74AS74M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74AS74SJX
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74AS74N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
PR
CLR CLK
Outputs
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
H (Note 1)
L
L
X
X
H (Note 1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
L = LOW State
H = HIGH State
X = Don't Care
↑ = Positive Edge Transition
Q0 = Previous Condition of Q
Note 1: This condition is nonstable; it will not persist when preset and clear
inputs return to their inactive (HIGH) level. The output levels in this condition are not guaranteed to meet the VOH specification.
© 2000 Fairchild Semiconductor Corporation
DS006282
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DM74AS74 Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear
April 1984
DM74AS74
Logic Diagram
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2
Supply Voltage
7V
Input Voltage
7V
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
0°C to +70°C
Operating Free Air Temperature Range
−65°C to +150°C
Storage Temperature Range
Typical θJA
N Package
76.0°C/W
M Package
107.0°C/W
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
4.5
5
5.5
Units
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
0.8
V
IOH
HIGH Level Output Current
−2
mA
IOL
LOW Level Output Current
fCLK
Clock Frequency
tW(CLK)
Width of Clock Pulse
V
2
V
0
20
mA
105
MHz
HIGH
4
LOW
5.5
ns
4
ns
tW
Pulse Width Preset & Clear LOW
ns
tSU
Data Setup Time (Note 3)
4.5↑
ns
tSU
PRE or CLR Setup-Time (Note 3)
2↑
ns
tH
Data Hold Time (Note 3)
0↑
TA
Free Air Operating Temperature
ns
0
°C
70
Note 3: The (↑) arrow indicates the positive edge of the Clock is used for reference.
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.
Symbol
Parameter
Conditions
VIK
Input Clamp Voltage
VCC = 4.5V, II = −18 mA
VOH
HIGH Level
VCC = 4.5V to 5.5V,
Output Voltage
IOH = −2 mA
VOL
LOW Level
VCC = 4.5V, VIH = Max,
IOL = 20 mA
Input Current @ Max Input Voltage VCC = 5.5V, VIH = 7V
IIH
HIGH Level Input Current
Typ
Max
Units
−1.2
V
VCC − 2
Output Voltage
II
Min
V
0.35
0.5
V
0.1
mA
VCC = 5.5V,
Clock, D
20
µA
VIH = 2.7V
Preset, Clear
40
µA
VCC = 5.5V,
Clock, D
−0.5
mA
VIL = 0.4V
Preset, Clear
IIL
LOW Level Input Current
IO
Output Drive Current
VCC = 5.5V, VO = 2.25V
ICC
Supply Current
VCC = 5.5V
−30
10.5
3
−1.8
mA
−112
mA
16
mA
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DM74AS74
Absolute Maximum Ratings(Note 2)
DM74AS74
Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
From
fMAX
Maximum Clock Frequency
VCC = 4.5V to 5.5V
tPLH
Propagation Delay Time
RL = 500Ω
LOW-to-HIGH Level Output
CL = 50 pF
tPHL
Propagation Delay Time
Preset
HIGH-to-LOW Level Output
or Clear
Propagation Delay Time
Clock
tPLH
Preset
or Clear
Q or
Q
Q or
Q
Q or
Q
Propagation Delay Time
Clock
HIGH-to-LOW Level Output
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Min
Max
105
LOW-to-HIGH Level Output
tPHL
To
Q or
Q
4
Units
MHz
3
7.5
ns
3.5
10.5
ns
3.5
8
ns
4.5
9
ns
DM74AS74
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M14A
5
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DM74AS74
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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6
DM74AS74 Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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