Fairchild DM74LS240SJ Octal 3-state buffer/line driver/line receiver Datasheet

Revised March 2000
DM74LS240 • DM74LS241
Octal 3-STATE Buffer/Line Driver/Line Receiver
General Description
Features
These buffers/line drivers are designed to improve both the
performance and PC board density of 3-STATE buffers/
drivers employed as memory-address drivers, clock drivers, and bus-oriented transmitters/receivers. Featuring
400 mV of hysteresis at each low current PNP data line
input, they provide improved noise rejection and high
fanout outputs and can be used to drive terminated lines
down to 133Ω.
■ 3-STATE outputs drive bus lines directly
■ PNP inputs reduce DC loading on bus lines
■ Hysteresis at data inputs improves noise margins
■ Typical IOL (sink current)
24 mA
■ Typical IOH (source current)
−15 mA
■ Typical propagation delay times
Inverting
Noninverting
10.5 ns
12 ns
■ Typical enable/disable time 18 ns
■ Typical power dissipation (enabled)
Inverting
Noninverting
130 mW
135 mW
Ordering Code:
Order Number
Package Number
Package Description
DM74LS240WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS240SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS240N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74LS241WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS241N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
DM74LS240
© 2000 Fairchild Semiconductor Corporation
DM74LS241
DS006411
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DM74LS240 • DM74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver
August 1986
DM74LS240 • DM74LS241
Function Tables
DM74LS240
Inputs
DM74LS241
Output
Inputs
Outputs
G
A
Y
G
G
1A
2A
1Y
L
L
H
X
L
L
X
L
L
H
L
X
L
H
X
H
H
X
Z
X
H
X
X
Z
H
X
X
L
L
H
X
X
H
H
L
X
X
X
Z
L = LOW Logic Level
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
Z = High Impedance
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2
2Y
Supply Voltage
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
7V
Input Voltage
7V
0°C to +70°C
Operating Free Air Temperature Range
−65°C to +150°C
Storage Temperature Range
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
4.75
5
5.25
Units
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
V
VIL
LOW Level Input Voltage
0.8
V
IOH
HIGH Level Output Current
−15
mA
IOL
LOW Level Output Current
24
mA
TA
Free Air Operating Temperature
70
°C
2
V
0
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
HYS
Hysteresis (VT+ − VT−)
Data Inputs Only
VOH
HIGH Level Output Voltage
Conditions
VCC = Min
VCC = Min, VIH = Min
VIL = Max, IOH = −3 mA
VCC = Min, VIH = Min
VIL = Max
VIH = Min
IOZH
IOZL
Off-State Output Current,
VCC = Max
HIGH Level Voltage Applied
VIL = Max
Off-State Output Current,
VIH = Min
LOW Level Voltage Applied
II
Input Current at Maximum
VCC = Max
Input Voltage
VI = 7V
Units
V
0.4
V
3.4
V
2.7
2.4
2
VIL = 0.5V, IOH = Max
VCC = Min
Max
−1.5
0.2
VCC = Min, VIH = Min
LOW Level Output Voltage
Typ
(Note 2)
VCC = Min, II = −18 mA
VIL = Max, IOH = −1 mA
VOL
Min
IOL = 12 mA
0.4
IOL = Max
0.5
VO = 2.7V
20
µA
VO = 0.4V
−20
µA
0.1
mA
V
IIH
HIGH Level Input Current
VCC = Max, VI = 2.7V
20
µA
IIL
LOW Level Input Current
VCC = Max, VI = 0.4V
−0.2
mA
IOS
Short Circuit Output Current
VCC = Max (Note 3)
−225
mA
ICC
Supply Current
VCC = Max,
−40
Outputs HIGH
Outputs OPEN
Outputs LOW
Outputs Disabled
13
23
26
44
27
46
29
50
32
54
mA
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
3
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DM74LS240 • DM74LS241
Absolute Maximum Ratings(Note 1)
DM74LS240 • DM74LS241
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
tPLH
tPHL
tPZL
tPZH
tPLZ
tPHZ
tPLH
tPHL
tPZL
tPZH
Parameter
Conditions
Max
Propagation Delay Time
CL = 45 pF
DM74LS240
14
LOW-to-HIGH Level Output
RL = 667Ω
DM74LS241
18
Propagation Delay Time
CL = 45 pF
DM74LS240
18
HIGH-to-LOW Level Output
RL = 667Ω
DM74LS241
18
Output Enable Time
CL = 45 pF
DM74LS240
30
to LOW Level
RL = 667Ω
DM74LS241
30
Output Enable Time
CL = 45 pF
DM74LS240
23
to HIGH Level
RL = 667Ω
DM74LS241
23
Output Disable Time
CL = 5 pF
DM74LS240
25
from LOW Level
RL = 667Ω
DM74LS241
25
Output Disable Time
CL = 5 pF
DM74LS240
18
from HIGH Level
RL = 667Ω
DM74LS241
18
Propagation Delay Time
CL = 150 pF
DM74LS240
18
LOW-to-HIGH Level Output
RL = 667Ω
DM74LS241
21
Propagation Delay Time
CL = 150 pF
DM74LS240
22
HIGH-to-LOW Level Output
RL = 667Ω
DM74LS241
22
Output Enable Time
CL = 150 pF
DM74LS240
33
to LOW Level
RL = 667Ω
DM74LS241
33
Output Enable Time
CL = 150 pF
DM74LS240
26
to HIGH Level
RL = 667Ω
DM74LS241
26
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4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DM74LS240 • DM74LS241
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5
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DM74LS240 • DM74LS241
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Description M20D
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6
DM74LS240 • DM74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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7
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