Revised March 2000 DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins General Description Features The DM74LS299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register. ■ Common I/O for reduced pin count ■ Four operation modes: shift left, shift right, load and store ■ Separate shift right serial input and shift left serial input for easy cascading ■ 3-STATE outputs for bus oriented applications Ordering Code: Order Number Package Number Package Description DM74LS299WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS299N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Symbol VCC = Pin 20 GND = Pin 10 Pin Descriptions Pin Names Description CP Clock Pulse Input (Active Rising Edge) DS0 Serial Data Input for Right Shift DS7 Serial Data Input for Left Shift S0, S1 Mode Select Inputs MR Asynchronous Master Reset Input (Active LOW) OE1, OE2 3-STATE Output Enable Inputs (Active LOW) I/O0–I/O7 Parallel Data Inputs or 3-STATE Parallel Outputs Q0–Q7 Serial Outputs © 2000 Fairchild Semiconductor Corporation DS009827 www.fairchildsemi.com DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins October 1988 DM74LS299 Functional Description Mode Select Table The DM74LS299 contains eight edge-triggered D-type flipflops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by the S0 and S1, as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. Inputs Response MR S1 S0 CP X X H H H L H H H L H L L X X Asynchronous Reset; Q0–Q7 = LOW Parallel Load; I/On→Qn Shift Right; DS0→Q0, Q0→Q1, etc. Shift Left; DS7→Q7, Q7→Q6, etc. Hold H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock (CP) Transition A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. Logic Diagram www.fairchildsemi.com L H 2 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage IOH HIGH Level Output Current IOL LOW Level Output Current Min Nom Max Units 4.75 5 5.25 V 0.8 V Q0, Q7 −0.4 mA I/O0–I/O7 −2.6 mA Q0, Q7 8 mA I/O0–I/O7 24 mA 70 °C 2 TA Free Air Operating Temperature 0 tS(H) Setup Time HIGH or LOW 24 tS(L) S0 or S1 to CP 24 tH(H) Hold Time HIGH or LOW 0 tH(L) S0 or S1 to CP 0 tS(H) Setup Time HIGH or LOW 10 tS(L) I/On, DS0, DS7 to CP 10 tH(H) Hold Time HIGH or LOW 0 tH(L) I/On, DS0, DS7 to CP 0 tW(H) CP Pulse Width HIGH or LOW 15 tW(L) 15 tW(L) MR Pulse Width LOW tREC Recovery Time MR to CP 3 V ns ns ns ns ns 15 ns 10 ns www.fairchildsemi.com DM74LS299 Absolute Maximum Ratings(Note 1) DM74LS299 Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Q0, Q7 2.7 Output Voltage VIL = Max I/O0–I/O7 2.4 VOL LOW Level VCC = Min, IOL = Max Output Voltage VIH = Min IOL = 4 mA, VCC = Min II IIH Max Units −1.5 V 3.4 V 0.35 0.5 0.25 0.4 Input Current @ Max VCC = Max Inputs 0.1 mA VI = 7V Sn 0.2 mA HIGH Level VCC = Max, VI = 2.7V Sn 40 µA Inputs 20 µA −0.8 mA −0.4 mA VCC = Max, VI = 0.4V LOW Level Sn Input Current Inputs Short Circuit VCC = Max Q0, Q7 −20 −100 Output Current (Note 3) I/O0–I/O7 −30 −130 ICC Supply Current VCC = Max, OE = 4.5V IOZH 3-STATE Output Off VCC = Max Current HIGH VO = 2.7V IOS IOZL V Input Voltage Input Current IIL Typ (Note 2) 3-STATE Output Off VCC = Max Current Low VO = 0.4V mA 60 mA 40 µA −400 µA Note 2: All typicals are at VCC = 5V, TA = 25°C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics VCC = +5.0V, TA = +25°C RL = 2 kΩ Symbol CL = 15 pF Parameter Min Units Max fMAX Maximum Input Frequency tPLH Propagation Delay 35 26 tPHL CP to Q0 or Q7 28 tPLH Propagation Delay 25 tPHL CP to I/On 35 tPHL Propagation Delay MR to Q0 or Q7 tPHL Propagation Delay MR to I/On tPZH Output Enable Time Output Disable Time www.fairchildsemi.com 35 ns 15 20 4 ns ns 25 tPLZ ns 28 18 tPZL tPHZ MHz ns ns DM74LS299 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6