NSC DM74LS73AW Dual negative-edge-triggered master-slave j-k flip-flops with clear and complementary output Datasheet

DM54LS73A/DM74LS73A Dual Negative-Edge-Triggered
Master-Slave J-K Flip-Flops with Clear
and Complementary Outputs
General Description
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. The data on the J
and K inputs is allowed to change while the clock is high or
low without affecting the outputs as long as setup and hold
times are not violated. A low logic level on the clear input
will reset the outputs regardless of the levels of the other
inputs.
Connection Diagram
Dual-In-Line Package
TL/F/6372 – 1
Order Number DM54LS73AJ, DM54LS73AW, DM74LS73AM or DM74LS73AN
See NS Package Number J14A, M14A, N14A or W14B
Function Table
Inputs
Outputs
CLR
CLK
J
K
Q
Q
L
H
H
H
H
H
X
v
v
v
v
X
L
H
L
H
X
X
L
L
H
H
X
L
Q0
H
L
H
Q0
L
H
H
Toggle
Q0
Q0
H e High Logic Level
L e Low Logic Level
X e Either Low or High Logic Level
v e Negative going edge of pulse.
Q0 e The output logic level before the indicated input conditions were established.
Toggle e Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
C1995 National Semiconductor Corporation
TL/F/6372
RRD-B30M105/Printed in U. S. A.
DM54LS73A/DM74LS73A Dual Negative-Edge-Triggered
Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
June 1989
Absolute Maximum Ratings (Note)
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
b 55§ C to a 125§ C
DM54LS
DM74LS
0§ C to a 70§ C
b 65§ C to a 150§ C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM54LS73A
Parameter
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
DM74LS73A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.8
V
High Level Output Current
b 0.4
b 0.4
mA
IOL
Low Level Output Current
4
8
mA
fCLK
Clock Frequency (Note 2)
0
30
0
30
MHz
fCLK
Clock Frequency (Note 3)
0
25
0
25
MHz
tW
Pulse Width
(Note 2)
Clock High
20
20
Preset Low
25
25
Clear Low
25
25
Clock High
25
25
Preset Low
30
30
Clear Low
30
30
tW
Pulse Width
(Note 3)
ns
ns
tSU
Setup Time (Notes 1 and 2)
20v
20v
ns
tSU
Setup Time (Notes 1 and 3)
25v
25v
ns
tH
Hold Time (Notes 1 and 2)
0v
0v
ns
tH
Hold Time (Notes 1 and 3)
5v
5v
TA
Free Air Operating Temperature
b 55
Note 1: The symbol (
125
v) indicates the falling edge of the clock pulse is used for reference.
Note 2: CL e 15 pF, RL e 2 kX, TA e 25§ C and VCC e 5V.
Note 3: CL e 50 pF, RL e 2 kX, TA e 25§ C and VCC e 5V.
2
0
ns
70
§C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Max
Units
b 1.5
V
VI
Input Clamp Voltage
VCC e Min, II e b18 mA
VOH
High Level Output
Voltage
VCC e Min, IOH e Max
VIL e Max, VIH e Min
Low Level Output
Voltage
VCC e Min, IOL e Max
VIL e Max, VIH e Min
DM54
0.25
0.4
DM74
0.35
0.5
IOL e 4 mA, VCC e Min
DM74
0.25
0.4
VCC e Max
VI e 7V
J, K
VOL
II
IIH
IIL
IOS
ICC
Input Current @ Max
Input Voltage
High Level Input
Current
Low Level Input
Current
VCC e Max
VI e 2.7V
VCC e Max
VI e 0.4V
Short Circuit
Output Current
VCC e Max
(Note 2)
Supply Current
VCC e Max (Note 3)
V
V
0.1
Clear
0.3
Clock
0.4
J, K
20
Clear
60
Clock
80
J, K
b 0.4
Clear
b 0.8
Clock
b 0.8
DM54
b 20
b 100
DM74
b 20
b 100
4
6
mA
mA
mA
mA
mA
Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
RL e 2 kX
From (Input)
To (Output)
CL e 15 pF
Min
Max
CL e 50 pF
Min
Units
Max
fMAX
Maximum Clock
Frequency
tPHL
Propagation Delay Time
High to Low Level Output
Clear
to Q
20
28
ns
tPLH
Propagation Delay Time
Low to High Level Output
Clear
to Q
20
24
ns
tPLH
Propagation Delay Time
Low to High Level Output
Clock to
Q or Q
20
24
ns
tPHL
Propagation Delay Time
High to Low Level Output
Clock to
Q or Q
20
28
ns
30
25
MHz
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where
shorting the outputs to ground may cause the outputs to change logic state, an equivalent test may be performed where VO e 2.25V and 2.125V for DM54 and
DM74 series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test
equipment.
Note 3: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock is grounded.
3
Physical Dimensions inches (millimeters)
14-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54LS73AJ
NS Package Number J14A
4
Physical Dimensions inches (millimeters) (Continued)
14-Lead Small Outline Molded Package (M)
Order Number DM74LS73AM
NS Package Number M14A
14-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS73AN
NS Package Number N14A
5
DM54LS73A/DM74LS73A Dual Negative-Edge-Triggered
Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
Physical Dimensions inches (millimeters) (Continued)
14-Lead Ceramic Flat Package (W)
Order Number DM54LS73AW
NS Package Number W14B
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