Fairchild DM74LS90 Decade and binary counter Datasheet

DM74LS90 Decade and Binary Counters
August 1986
Revised March 2000
DM74LS90
Decade and Binary Counters
General Description
Features
Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the
count cycle length is divide-by-five for the DM74LS90.
■ Typical power dissipation 45 mW
■ Count frequency 42 MHz
All of these counters have a gated zero reset and the
DM74LS90 also has gated set-to-nine inputs for use in
BCD nine’s complement applications.
To use their maximum count length (decade or four bit
binary), the B input is connected to the QA output. The
input count pulses are applied to input A and the outputs
are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the
DM74LS90 counters by connecting the QD output to the A
input and applying the input count to the B input which
gives a divide-by-ten square wave at output QA.
Ordering Code:
Order Number
Package Number
Package Description
DM74LS90M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS90N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Reset/Count Truth Table
Reset Inputs
© 2000 Fairchild Semiconductor Corporation
DS006381
Output
R0(1)
R0(2)
R9(1)
R9(2)
QD
QC
QB
QA
H
H
L
X
L
L
L
L
H
H
X
L
L
L
L
L
X
X
H
H
H
L
L
H
X
L
X
L
L
X
L
X
COUNT
L
X
X
L
COUNT
X
L
L
X
COUNT
COUNT
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DM74LS90
Function Tables
Logic Diagram
BCD Count Sequence (Note 1)
Count
Output
QD
QC
QB
0
L
L
L
QA
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
L
H
H
L
7
L
H
H
H
8
H
L
L
L
9
H
L
L
H
Bi-Quinary (5-2) (Note 2)
Count
Output
QA
QD
QC
0
L
L
L
QB
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
H
L
L
L
6
H
L
L
H
7
H
L
H
L
8
H
L
H
H
9
H
H
L
L
H = HIGH Level
L = LOW Level
X = Don’t Care
The J and K inputs shown without connection are for reference only and
are functionally at a high level.
Note 1: Output QA is connected to input B for BCD count.
Note 2: Output QD is connected to input A for bi-quinary count.
Note 3: Output QA is connected to input B.
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2
Supply Voltage
7V
Input Voltage (Reset)
7V
Input Voltage (A or B)
Note 4: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the “Electrical
Characteristics” table are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
5.5V
0°C to +70°C
Operating Free Air Temperature Range
−65°C to +150°C
Storage Temperature Range
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
4.75
5
5.25
V
LOW Level Input Voltage
0.8
V
IOH
HIGH Level Output Current
−0.4
mA
IOL
LOW Level Output Current
8
mA
fCLK
Clock Frequency (Note 5)
MHz
fCLK
Clock Frequency (Note 6)
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
VIL
tW
tW
Pulse Width (Note 5)
Pulse Width (Note 6)
2
V
A to QA
0
32
B to QB
0
16
A to QA
0
20
B to QB
0
10
A
15
B
30
Reset
15
A
25
B
50
Reset
25
tREL
Reset Release Time (Note 5)
25
tREL
Reset Release Time (Note 6)
35
TA
Free Air Operating Temperature
0
MHz
ns
ns
ns
ns
°C
70
Note 5: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.
Note 6: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VCC = Min, II = −18 mA
VOH
HIGH Level
VCC = Min, IOH = Max
Output Voltage
VIL = Max, VIH = Min
VOL
LOW Level
VCC = Min, IOL = Max
Output Voltage
VIL = Max, VIH = Min
Min
2.7
(Note 8)
IOL = 4 mA, VCC = Min
II
IIH
Max
Units
−1.5
V
3.4
V
0.35
0.5
0.25
0.4
Input Current @ Max
VCC = Max, VI = 7V
Reset
0.1
Input Voltage
VCC = Max
A
0.2
VI = 5.5V
B
0.4
VCC = Max, VI = 2.7V
Reset
20
A
40
B
80
HIGH Level
Input Current
IIL
Typ
(Note 7)
LOW Level
VCC = Max, VI = 0.4V
Input Current
IOS
Short Circuit Output Current
VCC = Max (Note 9)
ICC
Supply Current
VCC = Max (Note 7)
Reset
−0.4
A
−2.4
B
−3.2
−20
9
V
mA
µA
mA
−100
mA
15
mA
Note 7: All typicals are at VCC = 5V, TA = 25°C.
3
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DM74LS90
Absolute Maximum Ratings(Note 4)
DM74LS90
Electrical Characteristics
(Continued)
Note 8: QA outputs are tested at IOL = Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.
Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 10: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.
Switching Characteristics at VCC = 5V and TA = 25°C
RL = 2 kΩ
From (Input)
Symbol
Parameter
CL = 15 pF
To (Output)
Min
fMAX
tPLH
A to QA
32
20
Frequency
B to QB
16
10
Propagation Delay Time
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPHL
CL = 50 pF
Min
Maximum Clock
LOW-to-HIGH Level Output
tPHL
Max
Propagation Delay Time
HIGH-to-LOW Level Output
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Units
Max
MHz
A to QA
16
20
ns
A to QA
18
24
ns
A to QD
48
52
ns
A to QD
50
60
ns
B to QB
16
23
ns
B to QB
21
30
ns
B to QC
32
37
ns
B to QC
35
44
ns
B to QD
32
36
ns
B to QD
35
44
ns
SET-9 to QA, QD
30
35
ns
SET-9 to QB, QC
40
48
ns
SET-0 to Any Q
40
52
ns
4
DM74LS90
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
5
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DM74LS90 Decade and Binary Counters
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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