NSC DM74LS93 Decade and binary counter Datasheet

DM74LS90/DM74LS93
Decade and Binary Counters
General Description
Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the
count cycle length is divide-by-five for the ’LS90 and divideby-eight for the ’LS93.
All of these counters have a gated zero reset and the LS90
also has gated set-to-nine inputs for use in BCD nine’s complement applications.
To use their maximum count length (decade or four bit binary), the B input is connected to the QA output. The input
count pulses are applied to input A and the outputs are as
described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the ’LS90 counters
by connecting the QD output to the A input and applying the
input count to the B input which gives a divide-by-ten square
wave at output QA.
Features
Y
Y
Typical power dissipation 45 mW
Count frequency 42 MHz
Connection Diagrams (Dual-In-Line Packages)
TL/F/6381 – 1
Order Number DM74LS90M or DM74LS90N
See NS Package Number M14A or N14A
C1995 National Semiconductor Corporation
TL/F/6381
TL/F/6381 – 2
Order Number DM74LS93M or DM74LS93N
See NS Package Number M14A or N14A
RRD-B30M105/Printed in U. S. A.
DM74LS90/DM74LS93 Decade and Binary Counters
June 1989
Absolute Maximum Ratings (Note)
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage (Reset)
Input Voltage (A or B)
Operating Free Air Temperature Range
DM74LS
7V
7V
5.5V
0§ C to a 70§ C
b 65§ C to a 150§ C
Storage Temperature Range
Recommended Operating Conditions
Symbol
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
IOL
Low Level Output Current
fCLK
Clock Frequency (Note 1)
fCLK
tW
tW
DM74LS90
Parameter
Clock Frequency (Note 2)
Pulse Width (Note 1)
Pulse Width (Note 2)
Units
Min
Nom
Max
4.75
5
5.25
V
2
V
0.8
V
b 0.4
mA
8
mA
A to QA
0
32
B to QB
0
16
A to QA
0
20
B to QB
0
10
A
15
B
30
Reset
15
A
25
B
50
Reset
25
tREL
Reset Release Time (Note 1)
25
tREL
Reset Release Time (Note 2)
35
TA
Free Air Operating Temperature
0
MHz
MHz
ns
ns
ns
ns
§C
70
Note 1: CL e 15 pF, RL e 2 kX, TA e 25§ C and VCC e 5V.
Note 2: CL e 50 pF, RL e 2 kX, TA e 25§ C and VCC e 5V.
’LS90 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VCC e Min, II e b18 mA
VOH
High Level Output
Voltage
VCC e Min, IOH e Max
VIL e Max, VIH e Min
VOL
Low Level Output
Voltage
VCC e Min, IOL e Max
VIL e Max, VIH e Min
(Note 4)
Min
2.7
Input Current @ Max
Input Voltage
VCC e Max, VI e 7V
VCC e Max
VI e 5.5V
2
Max
Units
b 1.5
V
3.4
0.35
IOL e 4 mA, VCC e Min
II
Typ
(Note 1)
0.25
V
0.5
V
0.4
Reset
0.1
A
0.2
B
0.4
mA
’LS90 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
IIH
IIL
Parameter
Conditions
High Level Input
Current
VCC e Max, VI e 2.7V
Low Level Input
Current
VCC e Max, VI e 0.4V
IOS
Short Circuit
Output Current
VCC e Max (Note 2)
ICC
Supply Current
VCC e Max (Note 3)
Min
Typ
(Note 1)
Max
Reset
Units
20
A
40
B
80
Reset
b 0.4
A
b 2.4
B
b 3.2
b 20
mA
mA
b 100
mA
15
mA
9
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.
Note 4: QA outputs are tested at IOL e Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.
’LS90 Switching Characteristics
at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
RL e 2 kX
From (Input)
To (Output)
CL e 15 pF
Min
fMAX
Maximum Clock
Frequency
Max
CL e 50 pF
Min
A to QA
32
20
B to QB
16
10
Units
Max
MHz
tPLH
Propagation Delay Time
Low to High Level Output
A to QA
16
20
ns
tPHL
Propagation Delay Time
High to Low Level Output
A to QA
18
24
ns
tPLH
Propagation Delay Time
Low to High Level Output
A to QD
48
52
ns
tPHL
Propagation Delay Time
High to Low Level Output
A to QD
50
60
ns
tPLH
Propagation Delay Time
Low to High Level Output
B to QB
16
23
ns
tPHL
Propagation Delay Time
High to Low Level Output
B to QB
21
30
ns
tPLH
Propagation Delay Time
Low to High Level Output
B to QC
32
37
ns
tPHL
Propagation Delay Time
High to Low Level Output
B to QC
35
44
ns
tPLH
Propagation Delay Time
Low to High Level Output
B to QD
32
36
ns
tPHL
Propagation Delay Time
High to Low Level Output
B to QD
35
44
ns
tPLH
Propagation Delay Time
Low to High Level Output
SET-9 to
QA, QD
30
35
ns
tPHL
Propagation Delay Time
High to Low Level Output
SET-9 to
QB, QC
40
48
ns
tPHL
Propagation Delay Time
High to Low Level Output
SET-0 to
Any Q
40
52
ns
3
Recommended Operating Conditions
Symbol
DM74LS93
Parameter
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
Units
Min
Nom
Max
4.75
5
5.25
V
2
V
0.8
V
mA
mA
IOH
High Level Output Current
b 0.4
IOL
Low Level Output Current
8
fCLK
Clock Frequency (Note 1)
fCLK
Clock Frequency (Note 2)
tW
Pulse Width (Note 1)
tW
Pulse Width (Note 2)
A to QA
0
32
B to QB
0
16
A to QA
0
20
B to QB
0
10
A
15
B
30
Reset
15
A
25
B
50
Reset
25
tREL
Reset Release Time (Note 1)
25
tREL
Reset Release Time (Note 2)
35
TA
Free Air Operating Temperature
0
MHz
ns
ns
ns
ns
70
§C
Note 1: CL e 15 pF, RL e 2 kX, TA e 25§ C and VCC e 5V.
Note 2: CL e 50 pF, RL e 2 kX, TA e 25§ C and VCC e 5V.
’LS93 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
b 1.5
V
VI
Input Clamp Voltage
VCC e Min, II e b18 mA
VOH
High Level Output
Voltage
VCC e Min, IOH e Max
VIL e Max, VIH e Min
VOL
Low Level Output
Voltage
VCC e Min, IOL e Max
VIL e Max, VIH e Min
(Note 4)
Input Current @ Max
Input Voltage
VCC e Max, VI e 7V
Reset
0.1
VCC e Max
VI e 5.5V
A
0.2
B
0.4
VCC e Max
VI e 2.7V
Reset
20
2.7
0.35
IOL e 4 mA, VCC e Min
II
IIH
High Level Input
Current
4
3.4
0.25
V
0.5
V
0.4
A
40
B
80
mA
mA
’LS93 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
IIL
Parameter
Conditions
Low Level Input
Current
VCC e Max, VI e 0.4V
IOS
Short Circuit
Output Current
VCC e Max (Note 2)
ICC
Supply Current
VCC e Max (Note 3)
Min
Typ
(Note 1)
Max
Reset
b 0.4
A
b 2.4
B
b 1.6
b 20
Units
mA
b 100
mA
15
mA
9
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.
Note 4: QA outputs are tested at IOL e max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.
’LS93 Switching Characteristics
at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
RL e 2 kX
From (Input)
To (Output)
CL e 15 pF
Min
fMAX
Maximum Clock
Frequency
Max
CL e 50 pF
Min
A to QA
32
20
B to QB
16
10
Units
Max
MHz
tPLH
Propagation Delay Time
Low to High Level Output
A to QA
16
20
ns
tPHL
Propagation Delay Time
High to Low Level Output
A to QA
18
24
ns
tPLH
Propagation Delay Time
Low to High Level Output
A to QD
70
85
ns
tPHL
Propagation Delay Time
High to Low Level Output
A to QD
70
90
ns
tPLH
Propagation Delay Time
Low to High Level Output
B to QB
16
23
ns
tPHL
Propagation Delay Time
High to Low Level Output
B to QB
21
30
ns
tPLH
Propagation Delay Time
Low to High Level Output
B to QC
32
37
ns
tPHL
Propagation Delay Time
High to Low Level Output
B to QC
35
44
ns
tPLH
Propagation Delay Time
Low to High Level Output
B to QD
51
60
ns
tPHL
Propagation Delay Time
High to Low Level Output
B to QD
51
70
ns
tPHL
Propagation Delay Time
High to Low Level Output
SET-0 to
Any Q
40
52
ns
5
Function Tables
LS90
BCD Count Sequence
(See Note A)
LS90
Bi-Quinary (5-2)
(See Note B)
Output
Count
0
1
2
3
4
5
6
7
8
9
QC
QB
QA
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
8
9
LS93
Count Sequence
(See Note C)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
QA
QD
QC
QB
L
L
L
L
L
H
H
H
H
H
L
L
L
L
H
L
L
L
L
H
L
L
H
H
L
L
L
H
H
L
L
H
L
H
L
L
H
L
H
L
LS90
Reset/Count Truth Table
Reset Inputs
Output
Count
Output
Count
QD
QD
QC
QB
QA
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Output
R0(1)
R0(2)
R9(1)
R9(2)
QD
H
H
X
X
L
L
X
H
H
X
L
X
X
L
L
X
H
X
L
X
L
X
L
H
L
X
L
X
L
L
H
QC
QB
L
L
L
L
L
L
COUNT
COUNT
COUNT
COUNT
QA
L
L
H
LS93
Reset/Count Truth Table
Reset Inputs
Output
R0(1)
R0(2)
QD
H
L
X
H
X
L
L
Note A: Output QA is connected to input B for BCD count.
Note B: Output QD is connected to input A for bi-quinary count.
Note C: Output QA is connected to input B.
Note D: H e High Level, L e Low Level, X e Don’t Care.
6
QC
QB
L
L
COUNT
COUNT
QA
L
Logic Diagrams
LS90
LS93
TL/F/6381 – 4
TL/F/6381 – 3
The J and K inputs shown without connection are for reference only and are functionally at a high level.
7
8
Physical Dimensions inches (millimeters)
14-Lead Small Outline Molded Package (M)
Order Number DM74LS90M or DM74LS93M
NS Package Number M14A
9
DM74LS90/DM74LS93 Decade and Binary Counters
Physical Dimensions inches (millimeters) (Continued)
14-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS90N or DM74LS93N
NS Package Number N14A
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