NSC DM8334 8-bit addressable latch Datasheet

9334/DM9334 8-Bit Addressable Latch
General Description
The DM9334 is a high speed 8-bit Addressable Latch designed for general purpose storage applications in digital
systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and being a oneof-eight decoder and demultiplexer with active level high
outputs. The device also incorporates an active level low
common clear for resetting all latches, as well as an active
level low enable.
The DM9334 has four modes of operation which are shown
in the mode selection table. In the addressable latch mode,
data on the data line (D) is written into the addressed latch.
The addressed latch will follow the data input with all nonaddressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous state and
are unaffected by the data or address inputs.
In the one-of-eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
other inputs in the low state. In the clear mode all outputs
are low and unaffected by the address and data inputs.
When operating the device as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done
while in the memory mode.
The function tables summarize the operation of the product.
Features
Y
Y
Y
Y
Y
Y
Y
Common clear
Easily expandable
Random (addressable) data entry
Serial to parallel capability
8 bits of storage/output of each bit available
Active high demultiplexing/decoding capability
Alternate Military/Aerospace device (9334) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6609 – 1
Order Number 9334DMQB, 9334FMQB, DM9334J or DM9334N
See NS Package Number J16A, N16E or W16A
C1995 National Semiconductor Corporation
TL/F/6609
RRD-B30M105/Printed in U. S. A.
9334/DM9334 8-Bit Addressable Latch
June 1989
Absolute Maximum Ratings (Note)
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
b 55§ C to a 125§ C
Military
Commercial
0§ to a 70§ C
Storage Temperature Range
b 65§ C to a 150§ C
Recommended Operating Conditions
Symbol
Military
Parameter
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
Commercial
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.8
0.8
V
High Level Output Current
b 0.8
b 0.8
mA
IOL
Low Level Output Current
16
16
mA
tW
ENABLE Pulse Width
(Fig. 1) (Note 4)
tSU
Setup Time
(Note 4)
tH
TA
Hold Time
(Note 4)
19
13
19
13
Data 1 (Fig. 4)
20
13
20
13
Data 0 (Fig. 4)
20
14
20
14
Address (Fig. 6)
(Note 1)
10
5
10
5
Data 1 (Fig. 4)
0
b 10
0
b 10
Data 0 (Fig. 4)
0
b 13
0
b 13
Free Air Operating Temperature
b 55
125
ns
ns
ns
0
70
§C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 2)
Max
Units
b 1.5
V
VI
Input Clamp Voltage
VCC e Min, II e b12 mA
VOH
High Level Output
Voltage
VCC e Min, IOH e Max
VIL e Max, VIH e Min
VOL
Low Level Output
Voltage
VCC e Min, IOL e Max
VIH e Min, VIL e Max
II
Input Current @ Max
Input Voltage
VCC e Max, VI e 5.5V
IIH
High Level Input
Current
VCC e Max
VI e 2.4V
E Input
60
Others
40
Low Level Input
Current
VCC e Max
VI e 0.4V
E Input
b 2.4
Others
b 1.6
Short Circuit
Output Current
VCC e Max
(Note 3)
Supply Current
VCC e Max
IIL
IOS
ICC
2.4
3.6
0.2
V
0.4
V
1
mA
MIL
b 30
b 100
COM
b 30
b 100
56
86
mA
mA
mA
mA
Note 1: The ADDRESS setup time is the time before the negative ENABLE transition that the ADDRESS must be stable so that the correct latch is addressed
without affecting the other latches.
Note 2: All typicals are at VCC e 5V, TA e 25§ C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4: TA e 25§ C and VCC e 5V.
2
Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load)
Symbol
From (Input)
To (Output)
Parameter
RL e 400X, CL e 15 pF
Min
Units
Max
tPLH
Propagation Delay Time
Low to High Level Output
Enable to
Output, Fig. 1
28
ns
tPHL
Propagation Delay Time
High to Low Level Output
Enable to
Output, Fig. 1
27
ns
tPLH
Propagation Delay Time
Low to High Level Output
Data to
Output, Fig. 2
35
ns
tPHL
Propagation Delay Time
High to Low Level Output
Data to
Output, Fig. 2
28
ns
tPLH
Propagation Delay Time
Low to High Level Output
Address to
Output, Fig. 3
35
ns
tPHL
Propagation Delay Time
High to Low Level Output
Address to
Output, Fig. 3
35
ns
tPHL
Propagation Delay Time
High to Low Level Output
Clear to
Output, Fig. 5
31
ns
Function Tables
E
C
Mode
L
H
L
H
H
L
H
L
Addressable Latch
Memory
Active High Eight
Channel Demultiplexer
Clear
Inputs
Present Output States
Mode
C
E
D
A0
A1
A2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
L
H
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
L
L
H
H
H
H
L
H
H
X
X
X
X
QN b 1
H
H
H
H
L
L
L
L
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
L
H
#
#
#
#
#
#
#
#
#
H
H
L
L
L
H
QN b 1
QN b 1
#
#
#
H
H
H
H
L
L
L
Demultiplex
L
L
L
H
Memory
QN b 1
QN b 1
L
H
QNb1
QNb1
QN b 1
QN b 1
QN b 1
Addressable
Latch
#
#
#
H
H
Clear
QN b 1
QN b 1
QNb1
QNb1
X e Don’t Care Condition
L e Low Voltage Level
H e High Voltage Level
QNb1 e Previous Output State
3
L
H
Logic Diagram
9334
TL/F/6609 – 2
Switching Time Waveforms
TL/F/6609 – 4
Other Conditions: E e L, C e H, A e Stable
Figure 2
TL/F/6609 – 3
Other Conditions: C e H, A e Stable
Figure 1
TL/F/6609 – 6
TL/F/6609 – 5
Other Conditions: C e H, A e Stable
Other Conditions: E e L, C e L, D e H
Figure 4
Figure 3
TL/F/6609 – 8
TL/F/6609 – 7
Other Conditions: C e H
Other Conditons: E e H
Figure 6
Figure 5
Note: The shaded areas indicate when the inputs are permitted to change for predictable output performance.
4
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 9334DMQB or DM9334J
NS Package Number J16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM9334N
NS Package Number N16E
5
9334/DM9334 8-Bit Addressable Latch
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 9334FMQB
NS Package Number W16A
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