TI1 DM9338N 9338/dm9338 8-bit multiple port register Datasheet

9338,DM9338
9338/DM9338 8-Bit Multiple Port Register
Literature Number: SNOS383A
9338/DM9338 8-Bit Multiple Port Register
General Description
The DM9338 is an 8-bit multiple port register designed for
high speed random access memory applications where the
ability to simultaneously read and write is desirable. A common use would be as a register bank in a three address
computer. Data can be written into any one of the eight bits
and read from any two of the eight bits simultaneously.
Connection Diagrams
et
e
Dual-In-Line Package
TL/F/9794 – 1
ol
Order Number 9338DMQB, 9338FMQB or DM9338N
See NS Package Number J16A, N16E or W16A
Pin Names
Description
Write Address Inputs
Data Input
B Read Address Inputs
C Read Address Inputs
Clock Pulse Input (Active Rising Edge)
Slave Enable Input (Active LOW)
B Output
C Output
O
bs
A0–A2
DA
B0–B2
C0–C2
CP
SLE
ZB
ZC
FASTÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/9794
RRD-B30M115/Printed in U. S. A.
9338/DM9338 8-Bit Multiple Port Register
June 1989
Absolute Maximum Ratings (Note)
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
b 55§ C to a 125§ C
Military
Commercial
0§ C to a 70§ C
Storage Temperature Range
b 65§ C to a 150§ C
Recommended Operating Conditions
Military
Parameter
Units
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
IOL
Low Level Output Current
TA
Free Air Operating Temperature
ts (H)
ts (L)
Setup Time HIGH or LOW
DA to CP
20
12
th (H)
th (L)
Hold Time HIGH or LOW
DA to CP
b 8.0
ts (H)
ts (L)
Setup Time HIGH or LOW
An to CP
10
10
th (H)
th (L)
Hold Time HIGH or LOW
An to CP
0
0
tw (H)
tw (L)
CP Pulse Width HIGH or LOW
2
2
0.8
V
b 0.8
mA
16
mA
70
§C
e
0.8
16
b 55
V
V
b 0.8
125
0
20
12
0
ns
0
ns
b 8.0
10
10
ns
0
0
ns
23
13
ns
ol
23
13
bs
Electrical Characteristics
Commercial
Min
et
Symbol
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Conditions
Input Clamp Voltage
VCC e Min, II e b12 mA
VOH
High Level Output Voltage
VCC e Min, IOH e Max
VIL e Max
VOL
Low Level Output Voltage
VCC e Min, IOL e Max
VIH e Min
II
Input Current @ Max
Input Voltage
VCC e Max, VI e 5.5V
IIH
High Level Input Current
IIL
IOS
O
VI
Parameter
ICC
Min
2.4
Typ
(Note 1)
Max
Units
b 1.5
V
3.4
0.2
V
0.4
V
1
mA
VCC e Max, VI e 2.4V
27
mA
Low Level Input Current
VCC e Max, VI e 0.4V
b 1.1
mA
Short Circuit
Output Current
VCC e Max
(Note 2)
Supply Current
VCC e Max
MIL
b 10
b 70
COM
b 10
b 70
135
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time.
2
mA
mA
Switching Characteristics
VCC e a 5.0V, TA e a 25§ C (See Section 1 for waveforms and load configurations)
CL e 15 pF
Symbol
Parameter
9338 (MIL)
Min
DM9338 (COM)
Max
Min
Max
Units
tPLH
tPHL
Propagation Delay
Bn or Cn to Zn
40
35
13
18
40
35
ns
tPLH
tPHL
Propagation Delay
DA to Zn
45
50
25
25
45
50
ns
tPLH
tPHL
Propagation Delay
CP to Zn
35
30
18
13
35
30
ns
Functional Description
data during the read operation. The state of each slave is
determined by the state of the master selected by its associated set of read address inputs.
The method of parallel expansion is shown in Figure a . One
9338 is needed for each bit of the required word length. The
read and write input lines should be connected in common
on all of the devices. This register configuration provides
two words of n-bits each at one time, where n devices are
connected in parallel.
et
e
The 9338 8-bit multiple port register can be considered a 1bit slice of eight high speed working registers. Data can be
written into any one and read from any two of the eight
locations simultaneously. Master/slave operation eliminates
all race problems associated with simultaneous read/write
activity from the same location. When the clock input (CP) is
LOW data applied to the data input line (DA) enters the
selected master. This selection is accomplished by coding
the three write input select lines (A0–A2) appropriately.
Data is stored synchronously with the rising edge of the
clock pulse.
The information for each of the two slaved (output) latches
is selected by two sets of read address inputs (B0 – B2 and
C0 – C2). The information enters the slave while the clock is
HIGH and is stored while the clock is LOW. If Slave Enable
is LOW (SLE), the slave latches are continuously enabled.
The signals are available on the output pins (ZB and ZC).
The input bit selection and the two output bit selections can
be accomplished independently or simultaneously. The data
flows into the device, is demultiplexed according to the state
of the write address lines and is clocked into the selected
latch. The eight latches function as masters and store the
input data. The two output latches are slaves and hold the
ol
Logic Symbol
TL/F/9794 – 2
O
bs
VCC e Pin 16
GND e Pin 8
TL/F/9794 – 4
FIGURE a. Parallel Expansion
3
et
e
Logic Diagram
O
bs
ol
TL/F/9794 – 3
4
e
Physical Dimensions inches (millimeters)
O
bs
ol
et
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 9338DMQB
NS Package Number J16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM9338N
NS Package Number N16E
5
e
et
16-Lead Ceramic Flat Package (W)
Order Number 9338FMQB
NS Package Number W16A
bs
ol
9338/DM9338 8-Bit Multiple Port Register
Physical Dimensions inches (millimeters) (Continued)
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