DAVICOM DM9620EP

DM9620
USB2.0 to Fast Ethernet Controller
DAVICOM Semiconductor, Inc.
DM9620
USB2.0 to 10/100M Fast Ethernet Controller
DATA SHEET
Preliminary
Version: DM9620-DS-P02
February 20, 2012
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
1
DM9620
USB2.0 to Fast Ethernet Controller
CONTENT
1. Features:................................................................................................................................................ 7
1.1 System Description ..................................................................................................................... 8
2. Block Diagram and Block Description ................................................................................................. 9
3. Pin Configuration:............................................................................................................................... 10
3.1 64- Pin LQFP with MII Interface Mode ................................................................................... 10
3.2 64-pin Description .................................................................................................................... 11
3.2.1 MII Interfaces................................................................................................................. 11
3.2.2 RMII Interfaces.............................................................................................................. 11
3.2.3 Reverse MII Interfaces................................................................................................... 11
3.2.3 EEPROM Interface ........................................................................................................ 12
3.2.4 USB Interface................................................................................................................. 12
3.2.5 Clock Interface............................................................................................................... 12
3.2.6 LED Interface................................................................................................................. 12
3.2.7 10/100 PHY ................................................................................................................... 13
3.2.8 Miscellaneous ................................................................................................................ 13
3.2.9 Power ............................................................................................................................. 13
3.2.10 GPIO (TEST1 set to 1) ................................................................................................ 13
3.3 strap pins table .......................................................................................................................... 14
4. Vendor Control and Status Register Set ............................................................................................. 15
4.1 Network Control Register (00H) .............................................................................................. 16
4.2 Network Status Register (01H)................................................................................................. 17
4.3 TX Control Register (02H) ....................................................................................................... 18
4.4 RX Control Register ( 05H )..................................................................................................... 18
4.5 RX Status Register ( 06H ) ....................................................................................................... 19
4.6 Receive Overflow Counter Register ( 07H )............................................................................. 19
4.7 Back Pressure Threshold Register (08H).................................................................................. 20
4.8 Flow Control Threshold Register ( 09H ) ................................................................................. 20
4.9 RX/TX Flow Control Register ( 0AH ) .................................................................................... 21
4.10 EEPROM & PHY Control Register ( 0BH ) .......................................................................... 21
4.11 EEPROM & PHY Address Register ( 0CH ) ......................................................................... 22
4.12 EEPROM & PHY Data Register ( EE_PHY_L:0DH EE_PHY_H:0EH ) ............ 22
4.13 Wake Up Control Register ( 0FH ) ......................................................................................... 22
4.14 Physical Address Register ( 10H~15H )................................................................................. 22
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
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DM9620
USB2.0 to Fast Ethernet Controller
4.15 Multicast Address Register ( 16H~1DH ) .............................................................................. 23
4.16 General purpose control Register ( 1EH )............................................................................ 23
4.17 General purpose Register ( 1FH ) ........................................................................................... 23
4.18 Vendor ID Register (28H~29H) ............................................................................................. 23
4.19 Product ID Register (2AH~2BH) ........................................................................................... 23
4.20 Chip Revision Register (2CH) ................................................................................................ 23
4.21 TX Special Control Register (2DH) ....................................................................................... 24
4.22 External PHY Force Mode Control Register (2EH) ............................................................... 24
4.23 Transmit Check Sum Control Register (31H) ........................................................................ 24
4.24 Receive Check Sum Control Status Register (32H) ............................................................... 25
4.25 External PHYceiver Address Register (33H) ......................................................................... 25
4.26 General Purpose Control Register 2 (34H)............................................................................. 25
4.27 General Purpose Register 2 (35H) .......................................................................................... 25
4.28 General Purpose Control Register 3 (36H)............................................................................. 26
4.29 General Purpose Register 3 (37H) .......................................................................................... 26
4.30 EEPROM and PHY Control Register (3AH).......................................................................... 26
4.31 Pause Packet Control/Status Register (3DH).......................................................................... 26
4.32 Transmit Packet Counter (81H) .............................................................................................. 26
4.33 USB Packet Error Counter (82H) ........................................................................................... 27
4.34 Ethernet Receive Packet CRC Error Counter (83H)............................................................... 27
4.35 Ethernet Transmit Excessive Collision Counter (84H) .......................................................... 27
4.36 Ethernet Transmit Collision Counter (85H) ........................................................................... 27
4.37 Ethernet Transmit Late Collision Counter (86H) ................................................................... 27
4.38 RX Header Control/Status Register (91H) ............................................................................. 27
4.39 USB Squelch Control (95H) ................................................................................................... 28
4.40 USB Address (96H) ................................................................................................................ 28
4.41 USB Device Address Register (F0H) ..................................................................................... 28
4.42 Receive Packet Counter Register (F1H) ................................................................................. 28
4.43 Transmit Packet Counter/USB Status Register (F2H)............................................................ 28
4.44 USB Control Register (F4H) .................................................................................................. 28
5. EEPROM Format:............................................................................................................................... 29
6. MII Register Description .................................................................................................................... 30
6.1 Basic Mode Control Register (BMCR) – 00H.......................................................................... 31
6.2 Basic Mode Status Register (BMSR) – 01H............................................................................. 32
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
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DM9620
USB2.0 to Fast Ethernet Controller
6.3 PHY ID Identifier Register #1 (PHYID1) – 02H ..................................................................... 33
6.4 PHY Identifier Register #2 (PHYID2) – 03H........................................................................... 33
6.5 Auto-negotiation Advertisement Register(ANAR) – 04H ....................................................... 33
6.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05H......................................... 34
6.7 Auto-negotiation Expansion Register (ANER)- 06H ............................................................... 35
6.8 DAVICOM Specified Configuration Register (DSCR) – 10H................................................. 35
6.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H............................. 37
6.10 10BASE-T Configuration/Status (10BTCSR) – 12H ............................................................. 38
6.11 Power down Control Register (PWDOR) – 13H.................................................................... 38
6.12 (Specified config) Register – 14H .......................................................................................... 39
6.13 DSP Control (DSP_CTRL) – 1BH ......................................................................................... 40
6.14 Power Saving Control Register (PSCR) – 1DH ..................................................................... 40
7. Functional description......................................................................................................................... 41
7.1 USB Functional description...................................................................................................... 41
7.1.1 USB Standard Command............................................................................................... 41
7.1.2 Vendor commands ......................................................................................................... 42
7.1.2.1 Register Type .............................................................................................................. 42
7.1.2.2 Memory Type.............................................................................................................. 43
7.1.3 Interface 0 Configuration............................................................................................... 44
7.1.4 Descriptor Values........................................................................................................... 45
7.1.5 Descriptors of string/1/2/3 are loaded from EEPROM.................................................. 50
7.2 Ethernet Functional Description ............................................................................................... 52
7.2.1 Serial Management Interface ......................................................................................... 52
7.2.2 100Base-TX Operation .................................................................................................. 52
7.2.3 4B5B Encoder................................................................................................................ 52
7.2.4 Scrambler ....................................................................................................................... 53
7.2.5 Parallel to Serial Converter............................................................................................ 53
7.2.6 NRZ to NRZI Encoder................................................................................................... 53
7.2.7 MLT-3 Converter........................................................................................................... 53
7.2.8 MLT-3 Driver ................................................................................................................ 53
7.2.9 4B5B Code Group.......................................................................................................... 54
7.2.10 100Base-TX Receiver.................................................................................................. 55
7.2.11 Signal Detect................................................................................................................ 55
7.2.12 Adaptive Equalization.................................................................................................. 55
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
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DM9620
USB2.0 to Fast Ethernet Controller
7.2.13 MLT-3 to NRZI Decoder............................................................................................. 55
7.2.14 Clock Recovery Module .............................................................................................. 55
7.2.15 NRZI to NRZ ............................................................................................................... 55
7.2.16 Serial to Parallel........................................................................................................... 55
7.2.17 Descrambler ................................................................................................................. 55
7.2.18 Code Group Alignment................................................................................................ 56
7.2.19 4B5B Decoder.............................................................................................................. 56
7.2.20 10Base-T Operation ..................................................................................................... 56
7.2.21 Collision Detection ...................................................................................................... 56
7.2.22 Carrier Sense................................................................................................................ 56
7.2.23 Auto-Negotiation ......................................................................................................... 56
7.2.24 Auto-Negotiation (continued)...................................................................................... 56
8. DC and AC Electrical Characteristics................................................................................................. 57
8.1 Absolute Maximum Ratings ( 25°C ) ....................................................................................... 57
8.1.1 Operating Conditions ..................................................................................................... 57
8.2 DC Electrical Characteristics (VDD = 3.3V) ........................................................................... 58
8.3 AC Electrical Characteristics & Timing Waveforms ............................................................... 58
8.3.1 TP Interface.................................................................................................................... 58
8.3.2 Oscillator/Crystal Timing ( 25°C ) ................................................................................ 59
9. AC Timing waveform:........................................................................................................................ 60
9.1 Power On Reset Timing............................................................................................................ 60
9.2 EEPROM timing....................................................................................................................... 61
9.3 MII Management Timing.......................................................................................................... 62
9.4 MII TX timing........................................................................................................................... 63
9.5 MII RX timing .......................................................................................................................... 63
9.6 RMII TX timing........................................................................................................................ 64
9.7 RMII RX timing........................................................................................................................ 64
9.8 RevMII TX timing .................................................................................................................... 65
9.9 RevMII RX timing.................................................................................................................... 65
10 Magnetic and Crystal Selection Guide .............................................................................................. 66
10.1 Magnetic Selection Guide....................................................................................................... 66
10.2 Crystal Selection Guide .......................................................................................................... 66
11. Application circuit ............................................................................................................................ 68
12. Package Information ......................................................................................................................... 70
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
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DM9620
USB2.0 to Fast Ethernet Controller
13. Ordering Information ........................................................................................................................ 71
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
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DM9620
USB2.0 to Fast Ethernet Controller
1. Features:
z
USB Interface
ƒ
USB2.0 Device
ƒ
Supports 12Mbps Full-Speed operation
ƒ
Supports 480Mbps High-Speed operation
ƒ
Supports suspend mode and remote wake-up Resume
ƒ
Supports USB standard commands
ƒ
Supports vendor specific commands
ƒ
Efficient TX/RX FIFO auto management.
ƒ
Supports 4 endpoints (Control, Interrupt, Bulk_IN, Bulk_OUT)
ƒ
Supported Classes: USB Common Class / USB Communications Class –
z
Ethernet
ƒ
Support IEEE802.3u 100BASE-TX and with IEEE802.3 10BASE-T standards
ƒ
Support IEEE802.3x flow control function for 100BASE-TX and 10BASET.
ƒ
Built-in 10/100Mbps Fast-Ethernet PHY with Auto-MDIX
ƒ
Supports MII, RMII and Reverse MII interface or 16 pins GPIO
ƒ
Support Auto-negotiation function
ƒ
Back Pressure Mode for half-duplex mode flow Control
ƒ
PAUSE frame for full-duplex flow control
ƒ
Supports GPIO, wakeup frame, link status change and Magic packet events for
remote wake-up
ƒ
Support TCP / UDP / IP v4 checksum offload checking and generating
z
EEPROM Interface
ƒ
Supports 128/256/512 bytes (93C06/93C46/93C56/93C66) of serial
EEPROM(for storing USB Descriptors)
ƒ
93C06/93C46/93C56/93C66 auto-detection
z
LED Indications
ƒ
Ethernet – Link / Act indication
ƒ
Ethernet – Speed (10M / 100M) indication
ƒ
Ethernet – Duplex (half / full) indication
ƒ
USB speed indication (full / high speed + traffic modes)
z
Clock
ƒ
Single 25MHz / 30 ppm crystal or oscillator
ƒ
Optional 12MHz crystal for USB
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
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DM9620
USB2.0 to Fast Ethernet Controller
z
Power Input
ƒ
Low-Power, Single-Supply 3.3V, 0.18um CMOS Technology
ƒ
Built in 3.3V to 1.8V regulator
z
Miscellaneous
ƒ
ƒ
ƒ
Very Low Power Consumption in suspend mode
Power Reduced mode (cable detection), and Power Down mode
Compatible with 5.0V tolerant I/O
1.1 System Description
The DM9620 USB to 10/100Mbps Fast Ethernet controller is a high performance and highly
integrated ASIC with embedded SSRAM for packet buffering. It enables low cost and
affordable Fast Ethernet network connection to desktop, notebook PC, and embedded
system using popular USB ports.
It has an USB interface to communicate with USB host controller and is compliant with USB
specification V1.0, V1.1 and V2.0. It implements 10/100Mbps Ethernet LAN function based on
IEEE802.3, and IEEE802.3u standards.
DM9620 integrates an on-chip 10/100Mbps Ethernet PHY to simplify system design and
provides an optional media-independent interface (MII/Reverse MII/RMII).
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
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DM9620
USB2.0 to Fast Ethernet Controller
2. Block Diagram and Block Description
EP1
Bulk
RX
IN
FIFO
FIFO
MII
SIE
USB
PHY
SRAM
Ethernet
Bulk
TX
OUT
FIFO
MAC
PHY
UTMI
FIFO
EP2
Register
Control table data
EEPROM interface
EEPROM
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
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DM9620
USB2.0 to Fast Ethernet Controller
3. Pin Configuration:
SMI_CK
SMI_D
COL
CRS
34
33
FDX_LED
39
38
36
35
SPD_LED
40
GND
TEST1
LNK_LED
42
USB_LED
VCC3
43
37
TEST2
44
41
GND
VUSB_IN
45
46
WOL
47
48
RSTB
3.1 64- Pin LQFP with MII Interface Mode
X1_12M
49
X2_12M
AVCC3
50
51
30
GND
52
29
RREF
53
28
DM
54
27
DP
VCC33_PLL
55
26
56
MDC
25
GNDPLL
VCC18
57
RXER
24
RXDV
DM9620EP
32
VCC3
31
RXC
EECS
EECK
EEDIO
MDIO
SD
63
18
RXGND
64
17
Version: DM9620 -15-DS-P02
February 20, 2012
RXD2
16
RXD3
TXC
GND
TXD0
TXD1
VCC3
TXD2
TXD3
TXE
AVCC18
TX-
TX+
TXGND
RXGND
RX+
RX-
AVCC18
BGRES
BGGND
Preliminary
15
19
14
62
13
RXD1
12
21
20
10
11
61
9
X1
GND
8
60
7
X2
RXD0
6
GND
22
5
59
3
4
VCC3
23
1
2
58
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DM9620
USB2.0 to Fast Ethernet Controller
3.2 64-pin Description
I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power, PD=internal pull-low (about 50K Ohm)
3.2.1 MII Interfaces
Pin No.
Pin Name
26
MDC
27
MDIO
12,13,15,16
11
18
33
34
25
31
24
19,20,21,22
TXD[3:0]
TXEN
TXC
CRS
COL
RXER
RXC
RXDV
RXD[3:0]
3.2.2 RMII Interfaces
Pin No.
Pin Name
26
MDC
27
MDIO
12,13
TXD3~2
15,16
TXD1~0
11
TXEN
18
TXC
33
CRS
34
COL
25
RXER
31
RXC
24
RXDV
19,20
RXD3~2
21,22
RXD1~0
3.2.3 Reverse MII Interfaces
Pin No.
Pin Name
26
MDC
27
MDIO
12,13,15,16
11
18
33
34
TXD[3:0]
TXEN
TXC
CRS
COL
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Type
O,PD
I/O
O,PD
O,PD
I,PD
I
I
I
I
I
I
Description
MII Serial Management Data Clock
MII Serial Management Data
MII Transmit Data
4-bit nibble data outputs (synchronous to the TXC)
MII Transmit Enable
MII Transmit Clock
MII Carrier Sense
MII Collision Detect
MII Receive Error
MII Receive Clock
MII Receive Data Valid
MII Receive Data
4-bit nibble data input (synchronous to RXC)
Type
O,PD
I/O
O,PD
O,PD
O,PD
I,PD
I
I
I
I
I
I
I
Description
MII Serial Management Data Clock
MII Serial Management Data
Reserved
RMII Transmit Data
RMII Transmit Enable
Reserved
RMII CRS_DV
Reserved, tie to ground in application.
Reserved, tie to ground in application.
50MHz reference clock.
Reserved, tie to ground in application.
Reserved, tie to ground in application.
RMII Receive Data
I/O
O,PD
I/O
O,PD
Description
Reserved
Reserved
MII Transmit Data
4-bit nibble data outputs (synchronous to the TXC)
MII Transmit Enable
25MHz clock output
carrier sense output when TXE or RXDV asserted
collision output when TXE and RXDV asserted
O,PD
O
O
O
11
DM9620
USB2.0 to Fast Ethernet Controller
25
31
24
19,20,21,22
RXER
RXC
RXDV
RXD[3:0]
Pin No.
Pin Name
I
I
I
I
MII Receive Error
MII Receive Clock
MII Receive Data Valid
MII Receive Data
4-bit nibble data input (synchronous to RXC)
Type
Description
3.2.3 EEPROM Interface
28
EEDIO
I/O
Data from EEPROM
29
EECK
O
Clock to EEPROM
30
EECS
O
Chip Select to EEPROM
3.2.4 USB Interface
51
VCC3A
P
3.3V for USB
52
GND
P
Ground for USB
53
RREF
I
Reference resistor to analog USB ground (12K 1% for USB)
54
DM (D-)
I/O
USB Data Minus
55
DP (D+)
I/O
USB Data Plus
56
VCC33_PLL
P
3.3V for USB PLL
57
GND_PLL
P
Ground for USB PLL
58
VCC18
O
1.8V power out for USB
3.2.5 Clock Interface
60
X2
O
Crystal 25MHz Out for Ethernet
61
X1
I
49
X1_12M
I
50
X2_12M
O
Crystal 25MHz In for Ethernet
Crystal 12MHz In for USB (Option, used when strap pin 30 EECS
pull-high), Normal N.C. * Note1
Crystal 12MHz out for USB (Option, used when strap pin 30 EECS
pull-high), Normal N.C. * Note1
* Note1: When strap pin 30 EECS pull-low, 12MHz clock from
internal PLL, detail see 3.3 strap pins table
3.2.6 LED Interface
38
USB_LED
O/D
39
FDX_LED
O/D
40
SPD_LED
O/D
41
LNK_LED
O/D
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
USB LED
Active low for USB HS mode
Floating for USB FS mode
Flash if traffic on USB
Full Duplex LED
Active low for Full Duplex
Floating for Half Duplex
SPEED LED
Active low for Ethernet 100M
Floating for Ethernet 10M
Link LED
Active low for Ethernet link
Floating for Ethernet non-link
12
DM9620
USB2.0 to Fast Ethernet Controller
Flash if traffic on Ethernet
3.2.7 10/100 PHY
63
SD
I
Fiber Signal Detection
64
RXGND
P
RX ground.
65
BGGND
P
Bandgap ground.
2
BGRES
I/O
Bandgap pin. Connect 6.98K 1% resister to BGGND
3
AVCC18
O
1.8V power out for RX power
4
RX+
I/O
TP RX input
5
RX-
I/O
TP RX input
6
RXGND
P
RX ground
7
TXGND
P
TX ground
8
TX+
I/O
TP TX output
9
TX-
I/O
TP TX output
10
AVCC18
O
1.8V power out for TX power
3.2.8 Miscellaneous
35
SMI_D
I
36
SMI_CK
I
45
VBUS_IN
I
47
WOL
O
48
RSTB
I
44
TEST2
I
42
TEST1
I
Serial Management Interface Data
Tie to ground in application.
Serial Management Interface Clock
Tie to ground in application..
This pin can also as a GPIO wakeup event defined in register 0FH.
VBUS input (Connect to USB5V, USB connector)
Tie to high in bus power mode
Issue a wake-up signal when wake-up event happens.
Hardware Reset
Active low signal to initiate the DM9620.
Test Mode 2, tie to ground in application.
Test Mode 1
0: pins 11-13,15-16,18-22,24-27,33-34 as MII, RMII, Reverse MII
interface
1: pins 11-13,15-16,18-22,24-27,33-34 as GPIO controlled by
registers 34H~37H
3.2.9 Power
14,32,43,
VCC3
59
17,23,37,
GND
46,62
3.2.10 GPIO (TEST1 set to 1)
Pin No.
11
12,13,15,16
18
Pin Name
P
Digital VCC 3.3V
P
Digital GND
Type
Description
GPIO2_0
I/O
GPIO2_0 in GPIO mode
GPIO2_1~4
I/O
GPIO2_1~4 in GPIO mode
GPIO2_5
I/O
GPIO2_5 in GPIO mode
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
13
DM9620
USB2.0 to Fast Ethernet Controller
19,20
GPIO2_6~7
I/O
GPIO2_6~7 in GPIO mode
21,22
GPIO3_0~1
I/O
GPIO3_0~1 in GPIO mode
24
GPIO3_2
I/O
GPIO3_2 in GPIO mode
25
GPIO3_3
I
I/O
GPIO3_3 in GPIO mode
27
GPIO3_4
I/O
GPIO3_4 in GPIO mode
31
GPIO3_5
I/O
GPIO3_5 in GPIO mode
33
GPIO3_6
I/O
GPIO3_6 in GPIO mode
34
GPIO3_7
I/O
GPIO3_7 in GPIO mode
3.3 strap pins table
1: pull-high 1K~10K, 0: default floating.
Pin No.
Pin Name
12,
13
TXD3
TXD2
15
TXD1
16
TXD0
30
EECS
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Description
TXD3 TXD2 in external PHY mode
0
0
MII mode
0
1
Reverse MII
1
0
RMII mode
1
1
Reserved
1: EEPROM force to 93C46 type
0: EEPROM type auto-detection
Ethernet RX packet header format
1= 4 header bytes include flag byte
0= 3 header bytes exclude flag byte
0: 12MHz clock from internal PLL
1: 12MHz clock from external crystal
14
DM9620
USB2.0 to Fast Ethernet Controller
4. Vendor Control and Status Register Set
The DM9620 implements several control and status registers, which can be accessed by the USB vendor register type
commands. All CRs are set to their default values by hardware or software reset unless otherwise specified.
Register
NCR
NSR
TCR
RCR
RSR
ROCR
BPTR
FCTR
FCR
EPCR
EPAR
EPDRL
EPDRH
WCR
PAR
MAR
GPCR
GPR
VID
PID
CHIPR
TSCR
FEPHY
TCSCR
RCSCSR
EPADR
GPCR2
GPR2
GPCR3
GPR3
EEP_CTRL
PPCSR
TX_CTR
UPERR
CRC_CTR
EXCOL_CTR
COL_CTR
LCOL_CTR
Description
Offset
Network Control Register
Network Status Register
TX Control Register
RX Control Register
RX Status Register
Receive Overflow Counter Register
Back Pressure Threshold Register
Flow Control Threshold Register
RX Flow Control Register
EEPROM & PHY Control Register
EEPROM & PHY Address Register
EEPROM & PHY Low Byte Data Register
EEPROM & PHY High Byte Data Register
Wake Up Control Register
Physical Address Register
00H
01H
02H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H-15H
Multicast Address Register
16H-1DH
General Purpose Control Register
General Purpose Register
Vendor ID
Product ID
CHIP revision
TX Special Control Register
Force External PHY Mode Control Register
Transmit Check Sum Control Register
Receive Check Sum Control Status Register
External PHY address
General Purpose Control Register 2
General Purpose Register 2
General Purpose Control Register 3
General Purpose Register 3
EEPROM and PHY Control Register
Pause Packet Control Status Register
Transmit Packet Counter
USB Packet Error Counter
Ethernet Receive Packet CRC Error Counter
Ethernet Transmit Excessive Collision Counter
Ethernet Transmit Collision Counter
Ethernet Transmit Late Collision Counter
1EH
1FH
28H-29H
2AH-2BH
2CH
2DH
2EH
31H
32H
33H
34H
35H
36H
37H
3AH
3DH
81H
82H
83H
84H
85H
86H
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Default value
after reset
00H
00H
00H
00H
00H
00H
37H
38H
00H
00H
40H
Unknown
Unknown
00H
Determined by
EEPROM
0000000000000
080
01H
Unknown
0A46H
9620H
01H
00H
00H
00H
00H
01H
00H
00H
00H
00H
00H
04H
00H
00H
00H
00H
00H
00H
15
DM9620
USB2.0 to Fast Ethernet Controller
MODE_CTL
SQUELCH
USB_ADR
USBDA
RXC
TXC/USBS
USBC
Mode Control
USB squelch Control
USB Address
USB device address register
Received packet counter register
Transmit packet counter/USB status register
USB control register
91H
95H
96H
F0H
F1H
F2H
F4H
00H
04H
00H
00H
00H
10H
00H
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where:
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
P = power on reset default value
H = hardware reset command default value
S = software reset default value
E = default value from EEPROM
T = default value from strap pin
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
4.1 Network Control Register (00H)
Bit
Name
Default
Description
7
EXT_PHY
PT0,RW External PHY mode (valid when pin TEST1 tie to ground)
1: Select external PHY
0: select Internal PHY.
This bit can be forced by register 2EH bit 5.
6
WAKEEN
PE0,RW Wakeup event enable
When set, it enables the wakeup function.
Clearing this bit will also clear all wakeup event status.
5
WCR_MODE
PHS,RW Write To Clear Mode
When set, the following register bits are cleared by write ‘1” .
Register 1 bit 2 and 3
Register 7
Register 0AH bit 2
Register 82H ~ 86H
4
FCOL
PHS0,RW Force Collision in Loopback Mode
Used for testing only.
3
FDX
PHS0,RW Full-Duplex mode.
1: Full-Duplex mode
0: Half-Duplex mode
Read only in Internal PHY mode.
This bit can be written only in External PHY mode.
This bit can also be forced by register 2EH bit 5 and 1.
2:1
LBK
PH00,RW Loopback mode
Bit 2 1
0 0
normal
0 1
MAC internal loopback
1 0
internal PHY digital loopback
1 1
internal PHY analog loopback
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
16
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USB2.0 to Fast Ethernet Controller
0
RST
PH0,RW
Software Reset
When write “1” to this bit, DM9620 enters software reset mode and will be
automatically cleared after 10us.
Write “0” to this bit can end the software reset mode.
4.2 Network Status Register (01H)
Bit
Name
Default
Description
7
SPEED
PHS0,RW Media Speed Status
0:100Mbps
1:10Mbps
This bit is no meaning when LINKST=0.
This bit read only in internal PHY mode and it can be written in external PHY
mode.
This bit can also be forced by register 2EH bit 5 and 2.
6
LINKST
PHS0,RO Link status
0:link failed
1:link OK
This bit read only in internal PHY mode and it can be written in external PHY
mode.
This bit can also be forced by register 2EH bit 5 and 0.
5
WAKEST
P0,W/C1 Wakeup event status.
This bit is set when wakeup event status asserted.
This bit is cleared by write “1” or when wakeup mode disabled.
4
RESERVED
PHS0,RO Reserved
3
RESERVED
PHS0,
Reserved
RW/C1
2
RESERVED
PHS0,
Reserved
RW/C1
1
RXOV
PHS0,RO RX FIFO Overflow Status
This bit is set when RX FIFO free space is less than 544-byte
This bit be cleared when RX FIFO free space is more than 2K.
0
RXRDY
PHS0,RO RX Packet Ready
This bit is set when there are one or more packets in RX FIFO.
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
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4.3 TX Control Register (02H)
Bit
Name
Default
7
RESERVED
0,RO
6
TJDIS
PHS0,RW
5
EXCECM
PHS0,RW
4:3
RESERVED
PHS0,RW
2
PAD_DIS1
PHS0,RW
1
CRC_DIS1
PHS0,RW
0
RESERVED
PHS0,RW
Description
Reserved
Transmit Jabber Disable
When set, the transmit Jabber Timer(2048 bytes) is disabled. Otherwise the
transmit packet size can more than 2048-byte.
Excessive Collision Mode Control :
0:abort this packet when excessive collision count more than 15,
1: still try to transmit this packet
Reserved
TX Packet PAD Append Control:
0: the transmit packet size is appended to at least 64-byte.
1: the transmit packet size is unchanged from original setting.
TX Packet Index II CRC Appends Control:
0: the CRC field is appended automatically.
1: the CRC field is not appended.
Reserved
4.4 RX Control Register ( 05H )
Bit
Name
Default
Description
7
HASHALL
PHS0,RW Filter All address in Hash Table
WTDIS
PHS0,RW Watchdog Timer Disable
6
When set, the Watchdog Timer(2048 bytes) is disabled and the RX packet may
more than 2048-byte.
When cleared, the Watchdog Timer(2048 bytes) is enabled and he RX packet is
truncated after the data more than 2048-byte
5
DIS_LONG
PHS0,RW Discard Long Packet
When set, the packets with length over 1522-byte are discarded from RX memory.
4
DIS_CRC
PHS0,RW Discard CRC Error Packet
When set, the packets with CRC error are discarded from RX memory.
3
ALL
PHS0,RW Pass All Multicast
When set, the packets with multicast destination address are stored to RX memory.
2
RUNT
PHS0,RW Pass Runt Packet
When set, the packets with size less than 64-byte are stored to RX memory.
1
PRMSC
PHS0,RW Promiscuous Mode
When set, the destination address is do not be checked.
0
RXEN
PHS0,RW RX Enable
When set, the received accepted packets can be stored to RX memory.
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
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4.5 RX Status Register ( 06H )
Bit
7
Name
RF
Default
PHS0,RO
6
MF
PHS0,RO
5
LCS
PHS0,RO
4
RWTO
PHS0,RO
3
PLE
PHS0,RO
2
AE
PHS0,RO
1
CE
PHS0,RO
0
FOE
PHS0,RO
Description
Runt Frame
It is set to indicate the received frame has the size smaller than 64 bytes.
Multicast Frame
It is set to indicate the received frame has a multicast address.
Late Collision Seen
It is set to indicate a late collision found during the frame reception.
Receive Watchdog Time-Out
It is set to indicate receive more than 2048 bytes.
Physical Layer Error
It is set to indicate a physical layer error found during the frame reception.
Alignment Error
It is set to indicate the received frame ends with a non-byte boundary.
CRC Error
It is set to indicate the received frame ends with a CRC error.
FIFO Overflow Error
It is set to indicate a FIFO Overflow error happens during the frame reception.
4.6 Receive Overflow Counter Register ( 07H )
This register can be cleared by writing any data this byte. Or they also can be cleared by read this byte if register 0H bit 5 is 0”.
Bit
7
Name
RXFU
6:0
ROC
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Default
PHS0,RW
/C
PHS0,RW
/C
Description
Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition.
Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO
overflow.
19
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USB2.0 to Fast Ethernet Controller
4.7 Back Pressure Threshold Register (08H)
Bit
Name
Default
Description
7:4
BPHW
PHS3h, RW Back Pressure High Water Overflow Threshold. MAC will generate the jam
pattern when RX SRAM free space is lower than this threshold value.
Default is 3K-byte free space. Please don’t exceed SRAM size.
(1 unit=1K bytes)
3:0
JPT
PHS7h, RW Jam Pattern Time. Default is 100us.
bit3 bit2 bit1 bit0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
time
2.5us
5us
7.5us
12.5us
25us
50us
75us
100us
125us
150us
175us
200us
2250us
250us
275us
300us
4.8 Flow Control Threshold Register ( 09H )
Bit
Name
Default
Description
7:4
HWOT
PHS3h, RW RX FIFO High Water Overflow Threshold
Send a pause packet with pause_time=FFFFH when the RX RAM free space is
less than this value., If this value is zero, its meaning is no free RX SARM space.
Default is 3K-byte free space. Please don’t exceed SRAM size.
(1 unit=1K bytes)
3:0
LWOT
PHS8h, RW RX FIFO Low Water Overflow Threshold
Send a pause packet with pause_time=0000 when RX SARM free space is
larger than this value. This pause packet is enabled after high water pause
packet transmitted. Default SRAM free space is 8K-byte. Please don’t exceed
SRAM size.
(1 unit=1K bytes)
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
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4.9 RX/TX Flow Control Register ( 0AH )
Bit
Name
Default
Description
7
TXP0
PHS0,RW
Force to TX Pause Packet with Time 0000H,:
This bit will be automatically cleared after pause packet transmission
completion.
Set to TX pause packet with time = 0000H
6
TXPF
PHS0,RW
Force to TX Pause Packet with Time FFFFH:
This bit will be automatically cleared after pause packet transmission
completion.
Set to TX pause packet with time = FFFFH.
5
TXPEN
PHS0,RW
TX Pause Packet Enable
Enable the pause packet for high/low water threshold of register 09H in
full-duplex mode.
4
BKPA
PHS0,RW
Back Pressure Packet Mode Enable:
Generate a jam pattern when any packet coming and RX SRAM over BPHW
of register 8H in half-duplex mode.
3
BKPM
PHS0,RW
Back Pressure DA Mode.
Generate a jam pattern when a packet’s DA match and RX SRAM over
BPHW of register 8H in half-duplex mode.
2
RXPS
PHS0,RW/C RX Pause Packet Status:
This bit latched the RX pause packet in full-duplex mode.
This bit can be cleared by write “1” to this bit or cleared automatically after
read if register 0H bit 5 is “0”.
1
RXPCS
PHS0,RO
RX Pause Packet Current Status:
When set, it indicated that the pause timer is not down count to “0” yet.
0
FLCE
PHS0,RW
Flow Control Enable
When set, it enable the flow control mode(i.e. can to disable TX function).
4.10 EEPROM & PHY Control Register ( 0BH )
Bit
Name
Default
Description
7
NO_EEP
P0,RO
EEPROM Absent
When set, it indicates the EEPROM 93C46 or 93C56/66 is not detected.
6
EE_TYPE
P0,RO
EEPROM type
0: 93C46
1: 93C56/66
5
REEP
PH0,RW
Reload EEPROM.
When set, the EEPROM is re-loaded.
Driver needs to clear it after operation complete.
4
WEP
PH0,RW
Write EEPROM enable
The written ability of EEPROM is enabled.
3
EPOS
PH0,RW
EEPROM or PHY Operation Select
When reset, select EEPROM;
when set, select PHY.
2
ERPRR
PH0,RW
EEPROM Read or PHY Register Read Command.
Write “1” to start EEPROM or PHY read operation.
This bit will be cleared after the completion of read operation.
1
ERPRW
PH0,RW
EEPROM Write or PHY Register Write Command.
Write “1” to start EEPROM or PHY write operation.
This bit will be cleared after the completion of write operation
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
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0
ERRE
PH0,RO
EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress.
4.11 EEPROM & PHY Address Register ( 0CH )
Bit
Name
Default
Description
7:6
PHY_ADR
PH01,RW
PHY Address bit [1:0] or EEPROM Word Address[7:6]:
If it is in PHY mode operation , the PHY address bit [4:2] is force to 0.
Force to 01 if internal PHY is selected.
Or EEPROM Word Address[7:6] if EEPROM 93C56/66 is used
5:0
EROA
PH0,RW
EEPROM Word Address[5:0] or PHY Register Number
4.12 EEPROM & PHY Data Register (
Bit
Name
Default
7:0
EE_PHY_L
X,RW
7:0
EE_PHY_H
X,RW
EE_PHY_L:0DH EE_PHY_H:0EH )
Description
EEPROM or PHY Low Byte Data
EEPROM or PHY High Byte Data
4.13 Wake Up Control Register ( 0FH )
Bit
Name
Type
Description
7
SMI_EN
P0,RW
SMI_C Event Enable
When set, enable SMI_C as GPIO Wake-up Event.
This event occurred in 100ms low state and then 100ms high state in SMI_CK
pin
6
SMI_ST
P0,RO
SMI_C Even Status
When set, indicates SMI_C Event occurred.
5
LINKEN
PE0,RW
Link Change Event Enable
When set, enable Link Status Change Wake-up Event.
4
SAMPLEEN
PE0,RW
Sample Frame Match Event Enable
When set, enable Sample Frame Wake-up Event.
3
MAGICEN
PE0,RW
Magic Packet Event Enable
When set, enable Magic Packet Wake-up Event.
2
LINKST
P0,RO
Link change Event Status
When set, indicates link change and Link Status Change Event occurred.
1
SAMPLEST
P0,RO
Sample Frame Mtach Event Status
When set, indicates the sample frame is received and Sample Frame Event
occurred. This bit will not be affected after a software reset.
0
MAGICST
P0,RO
Magic Packet Event Status
When set, indicates the Magic Packet is received and Magic packet Event
occurred. This bit will not be affected after a software reset.
4.14 Physical Address Register ( 10H~15H )
Bit
Name
Default
7:0
PAB5
E,RW
Physical Address Byte 5
7:0
PAB4
E,RW
Physical Address Byte 4
7:0
PAB3
E,RW
Physical Address Byte 3
7:0
PAB2
E,RW
Physical Address Byte 2
7:0
PAB1
E,RW
Physical Address Byte 1
7:0
PAB0
E,RW
Physical Address Byte 0
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Description
(15H)
(14H)
(13H)
(12H)
(11H)
(10H)
22
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USB2.0 to Fast Ethernet Controller
4.15 Multicast Address Register ( 16H~1DH )
Bit
Name
Default
7:0
MAB7
P80,RW
Multicast Address Byte 7
7:0
MAB6
P00,RW
Multicast Address Byte 6
7:0
MAB5
P00,RW
Multicast Address Byte 5
7:0
MAB4
P00,RW
Multicast Address Byte 4
7:0
MAB3
P00,RW
Multicast Address Byte 3
7:0
MAB2
P00,RW
Multicast Address Byte 2
7:0
MAB1
P00,RW
Multicast Address Byte 1
7:0
MAB0
P00RW
Multicast Address Byte 0
Description
(1DH)
(1CH)
(1BH)
(1AH)
(19H)
(18H)
(17H)
(16H)
4.16 General purpose control Register ( 1EH )
Bit
Name
Default
7:4
RESERVED
P0,RO
Reserved
3:0
RESERVED
P0111,RW
Reserved
Description
4.17 General purpose Register ( 1FH )
Bit
Name
Default
Description
7:4
RESERVED
P0,RO
Reserved
3:1
RESERVED
P0,RW
Reserved
0
GEPIO0
PE1,RW
General purpose :
When the correspondent bit of General Purpose Control Register is 1, the
value of the bit is output to pin GEPIO0.
When the correspondent bit of General Purpose Control Register is 0, the
value of the bit be read is reflected from pin GEPIO0.
GEPIO0 default output 1 to POWER_DOWN internal PHY. Driver need to
clear this POWER_DOWN signal by write “0” when it wants PHY active. If
other device need, it also can refer this signal. This default value can be
programmed by EEPROM. Please refer EEPROM description.
4.18 Vendor ID Register (28H~29H)
Bit
Name
Default
7:0
VIDH
0AH,RO
7:0
VIDL
46H.RO
Description
Vendor ID high byte (29H)
Vendor ID low byte (28H)
4.19 Product ID Register (2AH~2BH)
Bit
Name
Default
7:0
PIDH
96H,R
Product ID high byte (2BH)
7:0
PIDL
20H.R
Product ID low byte (2AH)
4.20 Chip Revision Register (2CH)
Bit
Name
Default
7:0
CHIPR
01H,RO
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Description
Description
CHIP revision
23
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4.21 TX Special Control Register (2DH)
Bit
Name
Default
7
RESERVED
PH0,RW
Reserved
6
LCOL_TRY
PH0,RW
Late Collision Retry
5
RESERVED
PH0,RW
Reserved
3
RESERVED
PH0,RW
Reserved
3:0
TX_GAP
PH0,RW
TX Inter frame Gap
0XXX: 96-bit
1000: 64-bit
1001: 72-bit
1010: 80-bit
1011: 88-bit
1100: 96-bit
1101: 104-bit
1110:112-bit
1111: 120-bit
Description
4.22 External PHY Force Mode Control Register (2EH)
Bit
Name
Default
Description
7~6
RESERVED
0,RO
Reserved
5
EXTERNAL
HP0,RW
Force to external PHY mode
4
RESERVED
0,RO
Reserved
3
RESERVED
PH0,RW
Reserved
2
SPEED
HP0,RW
Force external PHY speed mode in MAC register 1 bit 7
0: force to 100Mbps mode
1: force to 10Mbps mode
1
DUPLEX
HP0,RW
Force external PHY duplex mode in MAC register 0 bit 3
0: force to full-duplex
1: force to half-duplex
0
LINK
HP0,RW
Force external PHY link mode in MAC register 1 bit 6
0: force to link ON
1: force to link OFF
4.23 Transmit Check Sum Control Register (31H)
Bit
Name
Default
Description
7~3
RESERVED
0,RO
Reserved
2
UDPCSE
HPS0,RW
UDP Checksum Generation Enable
1
TCPCSE
HPS0,RW
TCP Checksum Generation Enable
0
IPCSE
HPS0,RW
IP Checksum Generation Enable
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
24
DM9620
USB2.0 to Fast Ethernet Controller
4.24 Receive Check Sum Control Status Register (32H)
Bit
Name
Default
Description
7
UDPS
HPS0,RO
UDP Checksum Status
0: UDP packet checksum OK, or this is not UDP packet
1: UDP packet checksum error
6
TCPS
HPS0,RO
TCP Checksum Status
0: TCP packet checksum OK, or this is not TCP packet
1: TCP packet checksum error
5
IPS
HPS0,RO
IP Checksum Status
0: IP packet checksum OK, this is not IP packet
1: IP packet checksum error
4
UDPP
HPS0,RO
UDP Packet
3
TCPP
HPS0,RO
TCP Packet
2
IPP
HPS0,RO
IP Packet
1
RCSEN
HPS0,RW
Receive Checksum Checking Enable
When set, the checksum status will store in packet first byte of status header
in RX DM9620 mode.
0
DCSE
HPS0,RW
Discard Checksum Error Packet
When set, if IP/TCP/UDP checksum field is error, this packet will be
discarded.
4.25 External PHYceiver Address Register (33H)
Bit
Name
Default
Description
7
ADR_EN
HPS0,RW
External PHY Address Enabled
When set in external MII mode, the external PHYceiver address is defined at
bit 4~0.
6~5
Reserved
HPS0,RO
Reserved
4~0
EPHYADR
HPS01,RW External PHY Address Bit 4~0
The PHY address in external MII mode.
4.26 General Purpose Control Register 2 (34H)
Bit
Name
Default
Description
7~0
GPC2
HP0,RW
General Purpose Control 2
Define the input mode (“0”,) or output mode (“1”) of pins GP_GRP2.
Where the GP_GRP2 are pins GPIO2 listed in pin description
4.27 General Purpose Register 2 (35H)
Bit
Name
Default
Description
7~0
GPD2
HP0,RW
General Purpose Register 2 Data
When the correspondent bit of General Purpose Control Register 2 is set, i.e.
output mode, the value of the bit is reflected to pins GP_GPR2
When the correspondent bit of General Purpose Control Register 2 is 0, i.e.
input mode, the value of the bit to be read is reflected from correspondent pins
GP_GPR2
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
25
DM9620
USB2.0 to Fast Ethernet Controller
4.28 General Purpose Control Register 3 (36H)
Bit
Name
Default
Description
7~0
GPC3
HP0,RW
General Purpose Control 3
Define the input mode (“0”,) or output mode (“1”) of pins GP_GRP3.
Where the GP_GRP3 are pins GPIO3 listed in pin description
4.29 General Purpose Register 3 (37H)
Bit
Name
Default
Description
7~0
GPD3
HP0,RW
General Purpose Register 3 Data
When the correspondent bit of General Purpose Control Register 3 is set, i.e.
output mode, the value of the bit is reflected to pin GP_GRP3
When the correspondent bit of General Purpose Control Register 3 is 0, i.e.
input mode, the value of the bit to be read is reflected from correspondent pins
GP_GRP3
4.30 EEPROM and PHY Control Register (3AH)
Bit
Name
Default
Description
7
FORCE_46
PT0,RW
Force EEPROM to 93C46 type
6
DET_46
P0,RO
Auto-detect EEPROM as 93C46
5
DET_56
P0,RO
Auto-detect EEPROM as 93C56
4~3
EECK_SPD
P0,RW
Re-define EEPROM EECK speed
00=0.2Mhz, 01=0.5MHz, 10=1MHz, 11=2MHz
2
NO_PRE
P0,RW
Do no generate Ethernet PHY preamble in MDIO
1~0
MDC_SPD
P0,RW
Re-define Ethernet PHY MDC speed
00=1Mhz, 01=3.1MHz, 10=12.5MHz, 11=0.25MHz
4.31 Pause Packet Control/Status Register (3DH)
Bit
Name
Default
Description
7~4
PAUSE_CTR
P0,RO
Pause Packet Counter
The Pause packet counter before RX SRAM flow control low threshold
reached.
3~0
PAUSE_MAX
PHS4,RW
Max. Pause Packet Count
The maximum pause packet with timer FFFFH is transmit, when the RX
SRAM is still in high threshold when pause timer timeout.
4.32 Transmit Packet Counter (81H)
Bit
Name
Default
7-0
TX_CTR
PS0,RO
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Description
TX Packet Count
The TX packet count in TX SRAM.
26
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USB2.0 to Fast Ethernet Controller
4.33 USB Packet Error Counter (82H)
Bit
Name
Default
Description
7-0
USB_ERR
PHS0,RW/C USB Data Error Count
This counter is increased when there has been data CRC error in USB
packet. This counter can be cleared by read if register 5 is “0” or by write to
this register with any data.
4.34 Ethernet Receive Packet CRC Error Counter (83H)
Bit
Name
Default
Description
7-0
RX_ERR
PHS0,RW/C Ethernet RX Packet CRC Error Count
This counter is increased when there has been CRC error in Ethernet receive
packet. This counter can be cleared by read if register 5 is “0” or by write to
this register with any data.
4.35 Ethernet Transmit Excessive Collision Counter (84H)
Bit
Name
Default
Description
7-0
ECOL_CTR
PHS0,RW/C Ethernet TX Packet Excessive Collision Count
This counter is increased when there has been excessive collision, i.e.
continued 16 collisions, in Ethernet transmit packet. This counter can be
cleared by read if register 5 is “0” or by write to this register with any data.
4.36 Ethernet Transmit Collision Counter (85H)
Bit
Name
Default
Description
7-0
COL_CTR
PHS0,RW/C Ethernet TX Packet Collision Count
This counter is increased when there has been collision in Ethernet transmit
packet. This counter can be cleared by read if register 5 is “0” or by write to
this register with any data.
4.37 Ethernet Transmit Late Collision Counter (86H)
Bit
Name
Default
Description
7-0
LCOL_CTR
PHS0,RW/C Ethernet TX Packet Late Collision Count
This counter is increased when there has been late collision in Ethernet
transmit packet. This counter can be cleared by read if register 5 is “0” or by
write to this register with any data.
4.38 RX Header Control/Status Register (91H)
Bit
Name
Default
Description
7
RX header
PT,RW
RX header mode
MODE
0: 3-byte RX header : RX_status, byte_ctr_low, byte_ctr_high
1: 4-byte RX header : RX _flag, RX_status, byte_ctr_low, byte_ctr_high
6~1
RESERVED
P,RO
Reserved
1:0
RESERVED
P0,RW
Reserved
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
27
DM9620
USB2.0 to Fast Ethernet Controller
4.39 USB Squelch Control (95H)
Bit
Name
Default
7~2
RESERVED
P0,RO
2~0
SQUELCH
P101,RW
4.40 USB Address (96H)
Bit
Name
7~0
USB_ADR
Default
P0,RO
Description
Reserved
Reference voltage for USB squelch circuit
000 for Reference voltage = 27.5mV
100 for Reference voltage = 137.5mV (default)
111 for Reference voltage = 220mV
Description
USB Address
4.41 USB Device Address Register (F0H)
Bit
Name
Default
7
RESERVED
0,RO
Reserved
6:0
USBFA
0,RO
USB device address
Description
4.42 Receive Packet Counter Register (F1H)
Bit
Name
Default
Description
7:0
RXC
0,RO
RXC is the packet counter received in SRAM
4.43 Transmit Packet Counter/USB Status Register (F2H)
Bit
Name
Default
Description
7
RXFAULT
0,RC
Indicate RX has unexpected condition
6
SUSFLAG
0,RC
Indicate device has suspend condition
5
EP1RDY
0,RO
Indicate there are data ready for read from EP1 pipe
4
RESERVED
0,RO
Reserved
3
BOFAULT
0,RO
Indicate Bulk Out has unexpected condition
2
TXC2
0,RO
Represent there is full in transmit buffer
1
TXC1
0,RO
Represent there is almost full in transmit buffer
0
TXC0
0,RO
Represent there have packets in transmit buffer.
4.44 USB Control Register (F4H)
Bit
Name
Default
7:6
Reserved
0,RW
5
EP3ACK
0,RW
4
3:1
0
EP3NAK
Reserved
MEMTST
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
0,RW
0,RW
0,RW
Description
Reserved
When set and EP3_NAK=0, EP3 will always return 8-byte data to host per
interrupt-interval
When set, EP3 will always return NAK.
Reserved
Before any memory-command, this bit must be set to 1. When in MEM_TST,
TX/RX fifo controller will be flushed.
28
DM9620
USB2.0 to Fast Ethernet Controller
5. EEPROM Format:
name
MAC address
Auto Load Control
Word
0
3
Vendor ID
Product ID
Reserved
Wake-UP mode
control
4
5
6
7
String1 address
String1 length
String2 address
String2 length
String3 address
String3 length
USB control
8
8
9
9
10
10
11
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
offset
description
0~5 6 byte ethernet address
6-7
Bit 1:0=01: Update vendor ID and product ID
Bit 5:2 reserved
Bit 7:6=01: Accept setting of WORD7[3:0]
Bit 9:8=01: Accept setting of WORD7[6:4]
Bit 11:10=01: Accept setting of WORD7[7]
Bit 13:12=01: Accept setting of WORD7[8]
Bit 15:14=01: Accept setting of WORD11
8-9
2 byte vendor ID (Default: 0A46h)
10-11 2 byte product ID (Default: 9620h)
12-13 reserved
14-15 Bit0: WOL active low when set (default: active high)
Bit1: WOL is pulse mode (default: level mode)
Bit2: magic wakeup event enabled when set. (default: no)
Bit3: link_change wakeup event enabled when set (default: no)
Bit4: magic wakeup event enabled if USB in suspend state (default: yes)
Bit5: link_change wakeup event enabled if USB in suspend state (default: yes)
Bit6: sample frame wakeup event enabled if USB in suspend state (default: yes)
Bit7: reserved
Bit8: internal PHY is enabled after power-on (default: no)
Bit13:9: reserved
Bit14: 1:AUTO-MDIX ON, 0:AUTO-MDIX OFF
Bit15: reserved
16
Vendor describe string from EEPROM start address
17
Vendor describe string length (Note: maximum value is 61)
18
Product describe string from EEPROM start address
19
Product describe string length (Note: maximum value is 61)
20
Product describe string from EEPROM start address
21
Product describe string length (Note: maximum value is 61)
22-23 Bit7: 0: USB maximum power. Unit is 2ma.
Bit15:8: USB class code
29
DM9620
USB2.0 to Fast Ethernet Controller
6. MII Register Description
ADD Name
15
00H CONTR Reset
OL
0
01H STATUS T4
Cap.
0
02H PHYID1
0
03H PHYID2
1
14
Loop
back
0
TX FDX
Cap.
1
0
0
13
12
11
Speed Auto-N Power
select
Enable Down
1
1
0
TX HDX 10 FDX 10 HDX
Cap.
Cap.
Cap.
1
1
1
0
0
0
1
1
1
04H Auto-Neg. Next
Advertise Page
05H Link Part. LP
Ability
Next
Page
06H Auto-Neg.
Expansio
n
10H Specifie BP
4B5B
d
Config.
11H Specifie 100
FDX
d
Conf/Stat
12H
10T
Rsvd
Conf/Stat
FLP Rcv
Ack
LP
Ack
Remote
Fault
LP
RF
Reserved
Reserved
10
Isolate
0
0
0
FC
Adv
LP
FC
9
8
Restart
Full
Auto-N Duplex
0
1
Reserved
7
Coll.
Test
0
6
5
Pream. Auto-N
Supr.
Compl.
0000
1
0
0
1
1
0
0
Model No.
01011
T4
TX FDX TX HDX 10 FDX 10 HDX
Adv
Adv
Adv
Adv
Adv
LP
LP
LP
LP
LP
T4
TX FDX TX HDX 10 FDX 10 HDX
Reserved
BP
SCR
BP
BP_ADP Reserve
ALIGN
OK
dr
100
HDX
10
FDX
LP
Enable
HBE
Enable
13H PWDOR
TX
JAB
Enable
Remote
Fault
0
0
3
Reserved
2
Next Pg
Able
Reserve Reserve Force Reserve Reserve RPDCTR Reset
d
d
100LNK
d
d
-EN
St. Mch
Pream.
Supr.
Reserved
PHY ADDR [4:0]
PDchip
Extd
Cap.
1
1
New Pg LP AutoN
Rcv
Cap.
Sleep
mode
Reserved
Auto-N. Monitor Bit [3:0]
Reserved
PD10DR PD100l
V
0
Link Partner Protocol Selector Field
LP Next
Pg Able
Reserve
d
1
000_0000
Auto-N
Link
Jabber
Cap.
Status
Detect
1
0
0
0
0
0
Version No.
0000
Advertised Protocol Selector Field
Pardet
Fault
10 HDX Reserve Reverse Reverse
d
d
d
SQUE
Enable
4
PDcrm
Polarity
Reverse
PDaeq
PDdrv
PDecli
PDeclo
PD10
14H Specified TSTSE1 TSTSE FORCE_ FORCE_ PREA TX10M NWAY_ Reserved MDIX_C AutoNeg Mdix_fix Mdix_do MonSel1 MonSel0 Reserve PD_valu
config
2
TXSD
FEF
NTL
_dlpbk
Value
wn
d
e
MBLE _PWR PWR
X
1BH DSP_CT
RL
1DH PSCR
DSP Control
Reversed
PREA AMPLIT TX_PW
MBLEX UDE
R
Reversed
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
<Access Type>:
RO = Read only
RW = Read/Write
Where:
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
(PIN#) Value latched in from pin # at reset
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
30
DM9620
USB2.0 to Fast Ethernet Controller
6.1 Basic Mode Control Register (BMCR) – 00H
Bit
Bit Name
Default
Description
Reset:
1=Software reset
0=Normal operation
15
Reset
0, RW/SC
This bit sets the status and controls the PHY registers to their
default states. This bit, which is self-clearing, will keep returning a
value of one until the reset process is completed
Loopback:
Loop-back control register
1 = Loop-back enabled
14
Loopback
0, RW
0 = Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 1300ms "dead
time" before any valid data appear at the MII receive outputs
Speed select:
1 = 100Mbps
0 = 10Mbps
13
Speed selection
1, RW
Link speed may be selected either by this bit or by auto-negotiation.
When auto-negotiation is enabled and bit 12 is set, this bit will return
auto-negotiation selected media type.
Auto-negotiation enable:
Auto-negotiatio
12
1, RW
1 = Auto-negotiation is enabled, bit 8 and 13 will be in
n enable
auto-negotiation status
Power Down:
While in the power-down state, the PHY should respond to
management transactions. During the transition to power-down
11
Power down
0, RW
state and while in the power-down state, the PHY should not
generate spurious signals on the MII.
1=Power down
0=Normal operation
Isolate:
1 = Isolates the PHY from the MII with the exception of the serial
management. (When this bit is asserted, the PHY does not respond
to the TXD[0:3], TX_EN, and TX_ER inputs, and it shall present a
10
Isolate
0,RW
high impedance on its TX_CLK, RX_CLK, RX_DV, RX_ER, RX[0:3],
COL and CRS outputs. When PHY is isolated from the MII it shall
respond to the management transactions)
0 = Normal operation
Restart auto-negotiation:
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this register
cleared), this bit has no function and it should be cleared. This bit is
Restart
9
0,RW/SC self-clearing and it will keep returning a value of 1 until
auto-negotiation
auto-negotiation is initiated by the PHY. The operation of the
auto-negotiation process will not be affected by the management
entity that clears this bit
0 = Normal operation
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
31
DM9620
USB2.0 to Fast Ethernet Controller
8
Duplex mode
1,RW
7
Collision test
0,RW
6-0
RESERVED
0,RO
Duplex mode:
1 = Full duplex operation. Duplex selection is allowed when
Auto-negotiation is disabled (bit 12 of this register is cleared). With
auto-negotiation enabled, this bit reflects the duplex capability
selected by auto-negotiation
0 = Normal operation
Collision test:
1 = Collision test enabled. When set, this bit will cause the COL
signal to be asserted in response to the assertion of TX_EN
0 = Normal operation
Reserved:
Write as 0, ignore on read
6.2 Basic Mode Status Register (BMSR) – 01H
Bit
Bit Name
Default
Description
100BASE-T4 capable:
15
100BASE-T4
0,RO/P
1 = Able to perform in 100BASE-T4 mode
0 = Not able to perform in 100BASE-T4 mode
100BASE-TX full duplex capable:
100BASE-TX
14
1,RO/P
1 = Able to perform 100BASE-TX in full duplex mode
full duplex
0 = Not able to perform 100BASE-TX in full duplex mode
100BASE-TX half duplex capable:
100BASE-TX
13
1,RO/P
1 = Able to perform 100BASE-TX in half duplex mode
half duplex
0 = Not able to perform 100BASE-TX in half duplex mode
10BASE-T full duplex capable:
10BASE-T
12
1,RO/P
1 = Able to perform 10BASE-T in full duplex mode
full duplex
0 = Not able to perform 10BASE-TX in full duplex mode
10BASE-T half duplex capable:
10BASE-T
11
1,RO/P
1 = Able to perform 10BASE-T in half duplex mode
half duplex
0 = Not able to perform 10BASE-T in half duplex mode
Reserved:
10-7
RESERVED
0,RO
Write as 0, ignore on read
MII frame preamble suppression:
MF preamble
1 = PHY will accept management frames with preamble suppressed
6
0,RO
suppression
0 = PHY will not accept management frames with preamble
suppressed
Auto-negotiatio
Auto-negotiation complete:
0,RO
5
n
1 = Auto-negotiation process completed
Complete
0 = Auto-negotiation process not completed
Remote fault:
1 = Remote fault condition detected (cleared on read or by a chip
reset). Fault criteria and detection method is PHY implementation
4
Remote fault
0,RO/LH
specific. This bit will set after the RF bit in the ANLPAR (bit 13,
register address 05) is set
0 = No remote fault condition detected
Auto-negotiatio
Auto configuration ability:
3
1,RO/P
n
1 = Able to perform auto-negotiation
ability
0 = Not able to perform auto-negotiation
Link status:
2
Link status
0,RO/LL
1 = Valid link is established (for either 10Mbps or 100Mbps
operation)
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
32
DM9620
USB2.0 to Fast Ethernet Controller
1
0
Jabber detect
Extended
capability
0,RO/LH
1,RO/P
0 = Link is not established
The link status bit is implemented with a latching function, so that
the occurrence of a link failure condition causes the link status bit to
be cleared and remain cleared until it is read via the management
interface
Jabber detect:
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a PHY reset. This bit works only in
10Mbps mode
Extended capability:
1 = Extended register capable
0 = Basic register capable only
6.3 PHY ID Identifier Register #1 (PHYID1) – 02H
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9620. The Identifier consists
of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model
revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
Bit Name
Default
15.0
OUI_MSB
<0181h>
Description
OUI most significant bits:
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of
this register respectively. The most significant two bits of the OUI
are ignored (the IEEE standard refers to these as bit 1 and 2)
6.4 PHY Identifier Register #2 (PHYID2) – 03H
Bit
Bit Name
Default
Description
OUI least significant bits:
<101110>,
15-10
OUI_LSB
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
RO/P
register respectively
Vendor model number:
<001011>, Six bits of vendor model number mapped to bit 9 to 4 (most
9-4
VNDR_MDL
RO/P
significant bit to bit 9)
Model revision number:
<0000>,
3-0
MDL_REV
Four bits of vendor model revision number mapped to bit 3 to 0
RO/P
(most significant bit to bit 3)
6.5 Auto-negotiation Advertisement Register(ANAR) – 04H
This register contains the advertised abilities of this DM9620 device as they will be transmitted to its link partner
during Auto-negotiation.
Bit
Bit Name
Default
15
NP
0,RO/P
14
ACK
0,RO
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Description
Next page indication:
0 = No next page available
1 = Next page available
The PHY has no next page, so this bit is permanently set to 0
Acknowledge:
1 = Link partner ability data reception acknowledged
33
DM9620
USB2.0 to Fast Ethernet Controller
13
RF
12-11
RESERVED
10
FCS
9
T4
8
TX_FDX
7
TX_HDX
6
10_FDX
5
10_HDX
4-0
Selector
0 = Not acknowledged
The PHY's auto-negotiation state machine will automatically
control this bit in the outgoing FLP bursts and set it at the
appropriate time during the auto-negotiation process. Software
should not attempt to write to this bit.
Remote fault:
0, RW
1 = Local device senses a fault condition
0 = No fault detected
Reserved:
X, RW
Write as 0, ignore on read
Flow control support:
0, RW
1 = Controller chip supports flow control ability
0 = Controller chip doesn’t support flow control ability
100BASE-T4 support:
1 = 100BASE-T4 is supported by the local device
0, RO/P
0 = 100BASE-T4 is not supported
The PHY does not support 100BASE-T4 so this bit is permanently
set to 0
100BASE-TX full duplex support:
1, RW
1 = 100BASE-TX full duplex is supported by the local device
0 = 100BASE-TX full duplex is not supported
100BASE-TX support:
1, RW
1 = 100BASE-TX is supported by the local device
0 = 100BASE-TX is not supported
10BASE-T full duplex support:
1, RW
1 = 10BASE-T full duplex is supported by the local device
0 = 10BASE-T full duplex is not supported
10BASE-T support:
1, RW
1 = 10BASE-T is supported by the local device
0 = 10BASE-T is not supported
Protocol selection bits:
These bits contain the binary encoded protocol selector supported
<00001>, RW by this node.
<00001> indicates that this device supports IEEE 802.3
CSMA/CD.
6.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05H
This register contains the advertised abilities of the link partner when received during Auto-negotiation.
Bit
Bit Name
Default
15
NP
0, RO
14
ACK
0, RO
13
RF
0, RO
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Description
Next page indication:
0 = Link partner, no next page available
1 = Link partner, next page available
Acknowledge:
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The PHY's auto-negotiation state machine will automatically
control this bit from the incoming FLP bursts. Software should not
attempt to write to this bit.
Remote Fault:
1 = Remote fault indicated by link partner
0 = No remote fault indicated by link partner
34
DM9620
USB2.0 to Fast Ethernet Controller
12-11
RESERVED
10
FCS
9
T4
8
TX_FDX
7
TX_HDX
6
10_FDX
5
10_HDX
4-0
Selector
Reserved:
Write as 0, ignore on read
Flow control support:
1 = Controller chip supports flow control ability by link partner
0, RW
0 = Controller chip doesn’t support flow control ability by link
partner
100BASE-T4 support:
0, RO
1 = 100BASE-T4 is supported by the link partner
0 = 100BASE-T4 is not supported by the link partner
100BASE-TX full duplex support:
0, RO
1 = 100BASE-TX full duplex is supported by the link partner
0 = 100BASE-TX full duplex is not supported by the link partner
100BASE-TX support:
0, RO
1 = 100BASE-TX half duplex is supported by the link partner
0 = 100BASE-TX half duplex is not supported by the link partner
10BASE-T full duplex support:
0, RO
1 = 10BASE-T full duplex is supported by the link partner
0 = 10BASE-T full duplex is not supported by the link partner
10BASE-T support:
0, RO
1 = 10BASE-T half duplex is supported by the link partner
0 = 10BASE-T half duplex is not supported by the link partner
Protocol selection bits:
<00000>, RO
Link partner’s binary encoded protocol selector
X, RO
6.7 Auto-negotiation Expansion Register (ANER)- 06H
Bit
Bit Name
Default
Description
Reserved:
15-5
RESERVED
X, RO
Write as 0, ignore on read
Local device parallel detection fault:
4
PDF
0, RO/LH
PDF = 1 : A fault detected via parallel detection function.
PDF = 0 : No fault detected via parallel detection function
Link partner next page able:
3
LP_NP_ABLE
0, RO
LP_NP_ABLE = 1 : Link partner, next page available
LP_NP_ABLE = 0 : Link partner, no next page
Local device next page able:
2
NP_ABLE
0,RO/P
NP_ABLE = 1 : next page available
NP_ABLE = 0 : no next page
New page received:
1
PAGE_RX
0, RO/LH
A new link code word page received. This bit will be automatically
cleared when the register (register 6) is read by management.
Link partner auto-negotiation able:
0
LP_AN_ABLE
0, RO
A “1” in this bit indicates that the link partner supports
Auto-negotiation.
6.8 DAVICOM Specified Configuration Register (DSCR) – 10H
Bit
Bit Name
Default
Description
Bypass 4B5B encoding and 5B4B decoding :
15
BP_4B5B
0, RW
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5B and 5B4B operation
14
BP_SCR
0, RW
Bypass scrambler/descrambler function :
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
35
DM9620
USB2.0 to Fast Ethernet Controller
13
BP_ALIGN
0, RW
12
BP_ADPOK
0, RW
11
RESERVED
0, RO
10
TX
1, RW
9
RESERVED
0, RO
8
RESERVED
0, RO
7
F_LINK_100
0, RW
6
RESERVED
0, RO
5
RESERVED
0, RO
4
RPDCTR-EN
1, RW
3
SMRST
0, RW
2
MFPSC
1, RW
1
SLEEP
0, RW
0
Reserved
0, RW
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
Bypass symbol alignment function:
1 = Receive functions (descrambler, symbol alignment and
symbol decoding functions) bypassed. Transmit functions
( symbol encoder and scrambler) bypassed
0 = Normal operation
BYPASS ADPOK :
Force signal detector (SD) active. This register is for debug only,
not release to customer.
1=Force SD is OK,
0=Normal operation
Reserved:
Write as 0, ignore on read.
100BASE-TX or FX mode control:
1 = 100BASE-TX operation
0 = 100BASE-FX operation
Reserved
Reserved:
Write as 0, ignore on read.
Force good link in 100Mbps:
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes.
Reserved:
Write as 0, ignore on read.
Reserved:
Write as 0, ignore on read.
Reduced power down control enable:
This bit is used to enable automatic reduced power down.
0 : Disable automatic reduced power down.
1 : Enable automatic reduced power down.
Reset state machine:
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed.
MF preamble suppression control:
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep mode:
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
Reserved
Force to 0 in application.
36
DM9620
USB2.0 to Fast Ethernet Controller
6.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H
Bit
Bit Name
Default
Description
100M full duplex operation mode:
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M full duplex
15
100FDX
1, RO
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in
the auto-negotiation mode.
100M half duplex operation mode:
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M half duplex
14
100HDX
1, RO
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in
the auto-negotiation mode.
10M full duplex operation mode:
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 10M Full Duplex
13
10FDX
1, RO
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in
the auto-negotiation mode.
10M half duplex operation mode:
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 10M half duplex
12
10HDX
1, RO
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in
the auto-negotiation mode.
Reserved:
11-9
RESERVED
0, RO
Write as 0, ignore on read
PHY address Bit 4:0:
(PHYADR), The first PHY address bit transmitted or received is the MSB of the
8-4
PHYADR[4:0]
RW
address (bit 4). A station management entity connected to multiple
PHY entities must know the appropriate address of each PHY.
Auto-negotiation monitor bits:
3-0
ANMB[3:0]
0, RO
These bits are for debug only. The auto-negotiation status will be
written to these bits.
B3 b2 b1 b0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal_link_ready
Parallel detects signal_link_ready fail
Auto-negotiation completed successfully
37
DM9620
USB2.0 to Fast Ethernet Controller
6.10 10BASE-T Configuration/Status (10BTCSR) – 12H
Bit
Bit Name
Default
Description
Reserved:
15
RESERVED
0, RO
Write as 0, ignore on read
Link pulse enable:
1 = Transmission of link pulses enabled
14
LP_EN
1, RW
0 = Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation.
Heartbeat enable:
1 = Heartbeat function enabled
0 = Heartbeat function disabled
13
HBE
1,RW
When the PHY is configured for full duplex operation, this bit will
be ignored (the collision/heartbeat function is invalid in full duplex
mode).
Squelch enable :
12
SQUELCH
1, RW
1 = normal squelch
0 = low squelch
Jabber Enable:
Enables or disables the Jabber function when the PHY is in
11
JABEN
1, RW
10BASE-T full duplex or 10BASE-T transceiver loopback mode
1 = Jabber function enabled
0 = Jabber function disabled
Reserved:
10-1
RESERVED
0, RO
Write as 0, ignore on read
Polarity reversed:
When this bit is set to 1, it indicates that the 10Mbps cable polarity
0
POLR
0, RO
is reversed. This bit is set and cleared by 10BASE-T module
automatically.
6.11 Power down Control Register (PWDOR) – 13H
Bit
Bit Name
Default
15
Reserved
0, RO
-9
Description
Reserved
Read as 0, ignore on write
8
PD10DRV
0, RW
Vendor power down control test
7
PD100DL
0, RW
Vendor power down control test
6
PDchip
0, RW
Vendor power down control test
5
PDcom
0, RW
Vendor power down control test
4
PDaeq
0, RW
Vendor power down control test
3
PDdrv
0, RW
Vendor power down control test
2
PDedi
0, RW
Vendor power down control test
1
PDedo
0, RW
Vendor power down control test
0
PD10
0, RW
Vendor power down control test
* When selected, the power down value is control by Register 20.0
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6.12 (Specified config) Register – 14H
Bit
Bit Name
Default
Description
15
TSTSE1
0,RW
Vendor test select control
14
TSTSE2
0,RW
Vendor test select control
13
FORCE_TXSD
0,RW
Force Signal Detect
1: force SD signal OK in 100M
0: normal SD signal.
12
FORCE_FEF
0,RW
11
PREAMBLEX
1,RW
10
TX10M_PWR
1,RW
9
NWAY_PWR
0,RW
8
Reserved
0, RW
7
MDIX_CNTL
Vendor test select control
Preamble Saving Control
0: when bit 10 is set, the 10BASE-T transmit preamble count is
reduced. When bit 11 of register 1DH is set, 12-bit preamble is
reduced; otherwise 22-bit preamble is reduced.
1: transmit preamble bit count is normal in 10BASE-T mode
10BASE-T mode Transmit Power Saving Control
1: enable transmit power saving in 10BASE-T mode
0: disable transmit power saving in 10BASE-T mode
Auto-negotiation Power Saving Control
1: disable power saving during auto-negotiation period
0: enable power saving during auto-negotiation period
Reserved
MDI/MDIX,RO The polarity of MDI/MDIX value
1: MDIX mode
0: MDI mode
6
AutoNeg_lpbk
0,RW
Auto-negotiation Loop-back
1: test internal digital auto-negotiation Loop-back
0: normal.
5
Mdix_fix Value
0, RW
MDIX_CNTL force value:
When Mdix_down = 1, MDIX_CNTL value depend on the register
value.
4
Mdix_down
0,RW
HP Auto-MDIX Down
Manual force MDI/MDIX.
1: Disable HP Auto-MDIX , MDIX_CNTL value depend on Bit5
0: Enable HP Auto-MDIX
3
MonSel1
0,RW
Vendor monitor select
2
MonSel0
0,RW
Vendor monitor select
1
Reserved
0,RW
Reserved
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Force to 0, in application.
0
PD_value
0,RW
Power down control value
Decision the value of each field Register 19.
1: power down
0: normal
6.13 DSP Control (DSP_CTRL) – 1BH
Bit
Bit Name
Default
15~0
DSP_CTRL
0, RW
Description
DSP CONTROL
For internal testing only
6.14 Power Saving Control Register (PSCR) – 1DH
Bit
15-12
11
Bit Name
RESERVED
PREAMBLEX
Default
0,RO
0,RW
10
AMPLITUDE
0,RW
9
TX_PWR
0.RW
8-0
RESERVED
0,RO
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Version: DM9620 -15-DS-P02
February 20, 2012
Description
RESERVED
Preamble Saving Control
when both bit 10and 11 of register 14H are set, the 10BASE-T
transmit preamble count is reduced.
1: 12-bit preamble is reduced.
0: 22-bit preamble is reduced.
Transmit Amplitude Control Disabled
1: when cable is unconnected with link partner, the TX amplitude is
reduced for power saving.
0: disable Transmit amplitude reduce function
Transmit Power Saving Control Disabled
1: when cable is unconnected with link partner, the driving current
of transmit is reduced for power saving.
0: disable transmit driving power saving function
RESERVED
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7. Functional description
7.1 USB Functional description
7.1.1 USB Standard Command
1. Supported Standard Command
Setup Stage
BmReqType
BRequest
00000000B
00000001B
CLEAR_FEATURE
00000010B
10000000B
GET_CONFIGURATION
10000000B
GET_DESCRIPTOR
10000001B
GET_INTERFACE
wValue
Feature
Selector
Zero
Descriptor
type/index
Zero
10000000B
wIndex
wLength
Data
Zero
None
Zero
One
Configuration value
Zero/LID
Length
Descriptor
Interface
One
Alternate Interface
Two
Status
Zero
Zero
None
Zero
Zero
None
Zero/LID
Length
Descriptor
Zero
None
Interface
Zero
None
Endpoint
Two
Frame Number
Zero
Interface
Endpoint
Zero
GET_STATUS
10000001B
Zero
10000010B
Interface
Endpoint
00000000B
SET_ADDRESS
00000000B
SET_CONFIGURATION
00000000B
SET_DESCRIPTOR
00000000B
00000001B
Data Stage
SET_FEATURE
00000010B
00000001B
SET_INTERFACE
10000010B
SYNCH_FRAME
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Device address
Configuration
value
Descriptor
type/index
Feature
Selector
Alternate
setting
Zero
Zero
Interface
Endpoint
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2. Not Supported Standard Commands
• Clear_Feature (Interface)
• Set_Feature (Interface)
• Set_Descriptor ( )
• Sync_Frame ( )
7.1.2 Vendor commands
There are two types of vendor’s command. We can access internal register maximum 64 bytes, and can
access internal memory.
7.1.2.1 Register Type
READ_REGISTER( )
Setup Stage
BmReqType
bReq
WValue
Byte 0
Byte 1
Byte 2
C0H
00H
00H
WIndex
Byte
Byte 4
3
wLength
Byte 5
Byte 6
00H
BC[7:0]
RegOffset[7:
00H
0]
Byte
7
00H
WRITE_REGISTER( )
Setup Stage
BmReqType
bReq
WValue
wIndex
wLength
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
40H
01H
00H
00H
RegOffset[7:0]
00H
BC[7:0]
00H
WRITE1_REGISTER( )
Setup Stage
BmReqType
bReq
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
40H
03H
Data[7:0]
00H
RegOffset[7:0]
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Wvalue
wIndex
wLength
Byte 5 Byte 6
00H
Byte 7
0000H
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7.1.2.2 Memory Type
Theses kind of commands are valid when the bit “MEM_MODE “ is set, otherwise device will respond with
request error when receiving these commands.
READ_MEMORY( )
Setup Stage
BmReqType
Breq
Wvalue
Windex
wLength
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
C0H
02H
00H
00H
MemOff[7:0]
MemOff[15:8]
BC[7:0]
00H
WRITE_MEMORY( )
Setup Stage
BmReqType BReq
WValue
Windex
wLength
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
40H
05H
00H
00H
MemOff[7:0]
MemOff[15:8]
BC[7:0]
00H
WRITE1_MEMORY( )
Setup Stage
BmReqType Breq
WValue
Windex
wLength
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
40H
07H
Data[7:0]
00H
MemOff[7:0]
MemOff[15:8]
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Byte 6
Byte 7
0000H
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7.1.3 Interface 0 Configuration
Definition: len-byte is 64-byte in full speed mode and 256-byte in high speed mode.
1. Endpoint 1
Type: Bulk In
Packet Padload: len-byte
When host accessing EP1.
If IN-FIFO is full, device will send len-byte data.
If IN-FIFO isn’t full and Ethernet packet isn’t end, device will send a NAK.
If IN-FIFO isn’t full and Ethernet packet is end, device will send the surplus data in IN-FIFO.
Data Format
For 3-byte header mode
Fist byte
: Ethernet Receive Packet Status, the bit format is same as register 6 (RSR)
Second byte : Ethernet Receive Packet byte count low
Third byte
: Ethernet Receive Packet byte count high
The others
: Ethernet Receive Packet Data
For 4-byte header mode (if pin TXD0 is pull-high)
Fist byte
: Ethernet Receive Packet Checksum Status, the bit format is same as register 6 (RSR)
Second byte : Ethernet Receive Packet Status, the bit[7:2] format is same as register 32 (RCSCSR)
Third byte
: Ethernet Receive Packet byte count low
Fourth byte : Ethernet Receive Packet byte count high
The others
: Ethernet Receive Packet Data
2. Endpoint 2
Type: Bulk Out
Packet Padload: len-byte
When host accessing EP2.
If OUT-FIFO isn’t full, host sends data, device response ACK.
If OUT-FIFO is full, host sends data, device response NAK.
If host sends data less len-byte or zero byte, it means Ethernet packet end.
Data Format
First byte
Second byte
The others
: Ethernet Transmit Packet byte count low
: Ethernet Transmit Packet byte count high
: Ethernet Transmit Packet data
3. Endpoint 3
Type: Interrupt In
Packet Load: 8-byte
When host accessing EP3.
If no interrupt condition, device response NAK.
If interrupt condition, device will send content back to host.
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Data Format
Offset
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Name
NSR
TSR1
TSR2
RSR
ROCR
RXC
TXC
GPR
Description
Network status register
Reserved
Reserved
RX status register
Received overflow counter register
Received packet counter
Transmit packet counter
Reserved
7.1.4 Descriptor Values
All descriptors are stored in it’s default values..
Device Descriptor/18-Byte
Offset
Field
Size
Value
Description
0
bLength
1
12H
Size of descriptor in bytes
1
bDescriptorType
1
01H
DEVICE Descriptor Type
2
bcdUSB
2
4
bDeviceClass
1
0200H USB BCD version
00H
Class code, assign by USB
Zero: No device level class
01H~FEH : Valid device class
FFH : Vender-specific
5
bDeviceSubClass
1
00H
SubClass code, assign by USB
6
bDeviceProtocol
1
00H
Protocol code, assign by USB
7
bMaxPacketSize0
1
08H
Maximum PL for EP0(8,16,32,64)
8
idVender
2
0A46H Vendor ID(0A46) (fm EEP)
10
idProduce
2
9620H Product ID (fm EEP)
12
bcdDevice
2
0101H Device release number
14
iManufacturer
1
01H
Index of string descriptor for manufacturer
15
iProduct
1
02H
Index of string descriptor for product
16
iSerialNumber
1
03H
Index of string descriptors for serial number
17
bNumConfigurations
1
01H
Number of configurations
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Configuration0 Descriptor/9-Byte
Offset
Field
Size
Value
Description
0
bLength
1
09H
Size of descriptors
1
bDescriptorType
1
02H
CONFIGURATION Descriptor Type
2
wTotalLength
2
4
bNumInterfaces
1
01H
Number of interfaces
5
bConfigurationValue
1
01H
Value of this configuration
6
iConfiguration
1
00H
Index of string descriptor for configuration
7
bmAttributes
1
0027H Total descriptor length
A(8)0H Configuration characteristics
D7:Reserved (set to 1)
D6: Self-powered
D5: Remote WakeUp
0: if REG00H bit 6 is “0”
1: if REG00H bit 6 is “1”
D4: Reserved ( reset to 0)
8
MaxPower
1
3CH
Maximum power, 2mA units (fm EEP)
Interface0 Descriptor/9-Byte
Offset
Field
Size
Value
Description
0
bLength
1
09H
Size of this descriptor
1
bDescriptorType
1
04H
INTERFACE Descriptor Typr
2
bInterfaceNumber
1
00H
Number of interface
3
bAlternateSetting
1
00H
Value used to select alternate setting
4
bNumEndpoints
1
03H
Number of ednpoints
5
bInterfaceClass
1
00H
Class code
6
bInterfaceSubClass
1
00H
SunClass code
7
bInterfaceProtocol
1
00H
Protocol code
8
iInterface
1
00H
Index of string for this interface
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Endpoint1 Descriptor/6-Byte
Offset
Field
Size
Value
Description
0
bLength
1
07H
Size of this descriptor
1
bDescriptorType
1
05H
ENDPOINT Descriptor Type
2
bEndpointAddress
1
81H
Address of the endpoint
Bit3~0: The endpoint number
Bit 6~4: Reserved(0)
Bit7 : Direction(Control EP exclude)
0 = OUT endpoint
1 = IN endpoint
3
bmAttributes
1
02H
EP's attributes
Bit1~0: Transfer Type
00 = Control
01 = Isochronous
10 = Bulk
11 = Interrupt
4
wMaxPacketSize
2
0040H
6
bInterval
1
00H
Maximum packet size of this EP
(0200H for high speed)
Interval for polling (periodical pipe) (fm EEP)
Interrupt Tpye = 1 ~ 255 (ms)
Isochronoous Type = 1 (ms)
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USB2.0 to Fast Ethernet Controller
Endpoint 2 Descriptor/6-Byte
Offset
Field
Size
Value
Description
0
bLength
1
07H
Size of this descriptor
1
bDescriptorType
1
05H
ENDPOINT Descriptor Type
2
bEndpointAddress
1
02H
Address of the endpoint
Bit3~0: The endpoint number
Bit 6~4: Reserved(0)
Bit7 : Direction(Control EP exclude)
0 = OUT endpoint
1 = IN endpoint
3
bmAttributes
1
02H
EP's attributes
Bit1~0: Transfer Type
00 = Control
01 = Isochronous
10 = Bulk
11 = Interrupt
4
wMaxPacketSize
2
0040H
6
bInterval
1
00H
Maximum packet size of this EP
(0200H for high speed)
Interval for polling (periodical pipe) (fm EEP)
Interrupt Tpye = 1 ~ 255 (ms)
Isochronoous Type = 1 (ms)
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Endpoint3 Descriptor/6-Byte
Offset
Field
Size
Value
Description
0
bLength
1
07H
Size of this descriptor
1
bDescriptorType
1
05H
ENDPOINT Descriptor Typr
2
bEndpointAddress
1
83H
Address of the endpoint
Bit3~0: The endpoint number
Bit 6~4: Reserved(0)
Bit7 : Direction(Control EP exclude)
0 = OUT endpoint
1 = IN endpoint
3
bmAttributes
1
03H
EP's attributes
Bit1~0: Transfer Type
00 = Control
01 = Isochronous
10 = Bulk
11 = Interrupt
4
wMaxPacketSize
2
6
bInterval
1
0008H Maximum packet size of this EP
01H
Interval for polling (periodical pipe)
Interrupt Tpye = 1 ~ 255 (ms)
Isochronoous Type = 1 (ms)
String0 Descriptor/Code array
Offset
Field
Size
Value
Description
0
bLength
1
04H
Size of this descriptor
1
bDescriptorType
1
03H
STRING Descriptor Type
2
wLANGID[1]
2
0409H
Preliminary
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February 20, 2012
LANGID code(Eng.)
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7.1.5 Descriptors of string/1/2/3 are loaded from EEPROM
String1 Descriptor/UNICODE String
Offset
0
Field
bLength
Size
Value
1
Description
Descriptor length
In the EEPROM, data is loaded from the low
byte address position indexed by the word
address position at low byte: 8.
1
bDescriptorType
1
03H
STRING Descriptor Type
In the EEPROM, data is loaded from the high
byte address position indexed by the word
address position at low byte: 8
2
bString
n
Manufacture data
Data is loaded from the next word address
position indexed by the word address position
at low byte: 8
String2 Descriptor/UNICODE String
Offset
0
Field
bLength
Size
Value
1
Description
Descriptor length
In the EEPROM, data is loaded from the low
byte address position indexed by the word
address position at low byte: 9.
1
bDescriptorType
1
03H
STRING Descriptor Type
In the EEPROM, data is loaded from the high
byte address position indexed by the word
address position at low byte: 9
2
bString
n
Product
Data is loaded from the next word address
position indexed by the word address position
at low byte: 9
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USB2.0 to Fast Ethernet Controller
String3 Descriptor/UNICODE String
Offset
Field
Size
Value
Description
Descriptor length
0
bLength
In the EEPROM, data is loaded from the low
1
byte address position indexed by the word
address position at low byte: 10.
STRING Descriptor Type
1
bDescriptorType
1
03H
In the EEPROM, data is loaded from the high
byte address position indexed by the word
address position at low byte: 10.
Serial Number
2
bString
Data is loaded from the next word address
n
position indexed by the word address position
at low byte: 10.
Descriptors of string/1/2/3 if no EEPROM exist.
String1 Descriptor/UNICODE String
Offset
Field
Size
Value
Description
0
bLength
1
04H
Descriptor length
1
bDescriptorType
1
03H
STRING Descriptor Type
2
bString
2
String2 Descriptor/UNICODE String
Offset
Field
0020H Manufacture
Size
Value
Description
0
bLength
1
10H
Descriptor length
1
bDescriptorType
1
03H
STRING Descriptor Type
2
bString
14
55 00 53 00 42 00 20 00 45 00 74 00 68 00
U
S
B
E
t
h
String3 Descriptor/UNICODE String
Offset
Field
Size
Value
Description
0
bLength
1
04H
Descriptor length
1
bDescriptorType
1
03H
STRING Descriptor Type
2
bString
2
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0031H Serial Number
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7.2 Ethernet Functional Description
7.2.1 Serial Management Interface
DM9620
MDC
MDIO
MDC
MDIO
PHY
External PHY can be accessed via the MDC, MDIO
Management Interface - Read Frame Structure
MDC
MDIO Read
32 "1"s
Idle
0
Preamble
1
SFD
1
0
A4
Op Code
A3
A0
R4
PHY Address
R3
R0
Register Address
0
Z
D15
//
D14
Turn Around
//
D1
D0
Data
Read
Write
Idle
Management Interface - Write Frame Structure
MDC
MDIO Write
32 "1"s
Idle
Preamble
0
1
SFD
0
1
Op Code
A4
A3
A0
PHY Address
R4
R3
R0
Register Address
Write
1
0
D15
Turn Around
D14
Data
D1
D0
Idle
7.2.2 100Base-TX Operation
The block diagram in figure 3 provides an overview of
the functional blocks contained in the transmit
section.
The transmitter section contains the following
functional blocks:
- 4B5B Encoder
- Scrambler
- Parallel to Serial Converter
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- NRZ to NRZI Converter
- NRZI to MLT-3
- MLT-3 Driver
7.2.3 4B5B Encoder
The 4B5B encoder converts 4-bit (4B) nibble data
generated by the MAC Reconciliation Layer into a
5-bit (5B) code group for transmission, reference
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Table 1. This conversion is required for control and
packet data to be combined in code groups. The
4B5B encoder substitutes the first 8 bits of the MAC
preamble with a J/K code-group pair (11000 10001)
upon transmit. The 4B5B encoder continues to
replace subsequent 4B preamble and data nibbles
with corresponding 5B code-groups. At the end of the
transmit packet, upon the deassertion of the Transmit
Enable signal from the MAC Reconciliation layer, the
4B5B encoder injects the T/R code-group pair (01101
00111) indicating end of frame. After the T/R
code-group pair, the 4B5B encoder continuously
injects IDLEs into the transmit data stream until
Transmit Enable is asserted and the next transmit
packet is detected.
The DM9620 includes a Bypass 4B5B conversion
option within the 100Base-TX Transmitter for support
of applications like 100 Mbps repeaters which do not
require 4B5B conversion.
7.2.4 Scrambler
The scrambler is required to control the radiated
emissions (EMI) by spreading the transmit energy
across the frequency spectrum at the media
connector and on the twisted pair cable in
100Base-TX operation.
By scrambling the data, the total energy presented to
the cable is randomly distributed over a wide
frequency range. Without the scrambler, energy
levels on the cable could peak beyond FCC
limitations at frequencies related to repeated 5B
sequences like continuous transmission of IDLE
symbols. The scrambler output is combined with the
NRZ 5B data from the code-group encoder via an
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
XOR logic function. The result is a scrambled data
stream with sufficient randomization to decrease
radiated emissions at critical frequencies.
7.2.5 Parallel to Serial Converter
The Parallel to Serial Converter receives parallel 5B
scrambled data from the scrambler and serializes it
(converts it from a parallel to a serial data stream).
The serialized data stream is then presented to the
NRZ to NRZI Encoder block
7.2.6 NRZ to NRZI Encoder
After the transmit data stream has been scrambled
and serialized, the data must be NRZI encoded for
compatibility with the TP-PMD standard for
100Base-TX transmission over Category-5
unshielded twisted pair cable.
7.2.7 MLT-3 Converter
The MLT-3 conversion is accomplished by converting
the data stream output from the NRZI encoder into
two binary data streams with alternately phased logic
one events.
7.2.8 MLT-3 Driver
The two binary data streams created at the MLT-3
converter are fed to the twisted pair output driver
which converts these streams to current sources and
alternately drives either side of the transmit
transformer primary winding resulting in a minimal
current MLT-3 signal. Refer to figure 4 for the block
diagram of the MLT-3 converter.
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7.2.9 4B5B Code Group
Symbol
Meaning
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
4B code
3210
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I
J
K
T
R
H
Idle
SFD (1)
SFD (2)
ESD (1)
ESD (2)
Error
undefined
0101
0101
undefined
undefined
undefined
11111
11000
10001
01101
00111
00100
V
V
V
V
V
V
V
V
V
V
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
undefined
undefined
undefined
undefined
Undefined
undefined
undefined
undefined
undefined
undefined
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
Table 1
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
54
DM9620
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7.2.10 100Base-TX Receiver
The 100Base-TX receiver contains several function
blocks that convert the scrambled 125Mb/s serial
data to synchronous 4-bit nibble data that is then
provided to the MII.
The receive section contains the following functional
blocks:
- Signal Detect
- Digital Adaptive Equalization
- MLT-3 to Binary Decoder
- Clock Recovery Module
- NRZI to NRZ Decoder
- Serial to Parallel
- Descrambler
- Code Group Alignment
- 4B5B Decoder
conditioning of the received signal independent of the
cable length.
7.2.13 MLT-3 to NRZI Decoder
The DM9620 decodes the MLT-3 information from
the Digital Adaptive Equalizer into NRZI data. The
relationship between NRZI and MLT-3 data is shown
in figure 4.
7.2.14 Clock Recovery Module
The Clock Recovery Module accepts NRZI data from
the MLT-3 to NRZI decoder. The Clock Recovery
Module locks onto the data stream and extracts the
125Mhz reference clock. The extracted and
synchronized clock and data are presented to the
NRZI to NRZ Decoder.
7.2.11 Signal Detect
The signal detect function meets the specifications
mandated by the ANSI XT12 TP-PMD 100Base-TX
Standards for both voltage thresholds and timing
parameters.
7.2.12 Adaptive Equalization
When transmitting data at high speeds over copper
twisted pair cable, attenuation based on frequency
becomes a concern. In high speed twisted pair
signaling, the frequency content of the transmitted
signal can vary greatly during normal operation based
on the randomness of the scrambled data stream.
This variation in signal attenuation caused by
frequency variations must be compensated for to
ensure the integrity of the received data. In order to
ensure quality transmission when employing MLT-3
encoding, the compensation must be able to adapt to
various cable lengths and cable types depending on
the installed environment. The selection of long cable
lengths for a given implementation, requires
significant compensation which will be over-kill in a
situation that includes shorter, less attenuating cable
lengths. Conversely, the selection of short or
intermediate cable lengths requiring less
compensation will cause serious under-compensation
for longer length cables. Therefore, the compensation
or equalization must be adaptive to ensure proper
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
7.2.15 NRZI to NRZ
The transmit data stream is required to be NRZI
encoded in for compatibility with the TP-PMD
standard for 100Base-TX transmission over
Category-5 unshielded twisted pair cable. This
conversion process must be reversed on the receive
end. The NRZI to NRZ decoder, receives the NRZI
data stream from the Clock Recovery Module and
converts it to a NRZ data stream to be presented to
the Serial to Parallel conversion block.
7.2.16 Serial to Parallel
The Serial to Parallel Converter receives a serial data
stream from the NRZI to NRZ converter, and converts
the data stream to parallel data to be presented to the
descrambler.
7.2.17 Descrambler
Because of the scrambling process required to
control the radiated emissions of transmit data
streams, the receiver must descramble the receive
data streams. The descrambler receives scrambled
parallel data streams from the Serial to Parallel
converter, descrambles the data streams, and
presents the data streams to the Code Group
alignment block.
55
DM9620
USB2.0 to Fast Ethernet Controller
7.2.18 Code Group Alignment
The Code Group Alignment block receives un-aligned
5B data from the descrambler and converts it into 5B
code group data. Code Group Alignment occurs after
the J/K is detected, and subsequent data is aligned
on a fixed boundary.
7.2.22 Carrier Sense
7.2.19 4B5B Decoder
The 4B5B Decoder functions as a look-up table that
translates incoming 5B code groups into 4B (Nibble)
data. When receiving a frame, the first 2 5-bit code
groups received are the start-of-frame delimiter (J/K
symbols). The J/K symbol pair is stripped and two
nibbles of preamble pattern are substituted. The last
two code groups are the end-of-frame delimiter (T/R
symbols).
The T/R symbol pair is also stripped from the nibble
presented to the Reconciliation layer.
7.2.23 Auto-Negotiation
The objective of Auto-negotiation is to provide a
means to exchange information between segment
linked devices and to automatically configure both
devices to take maximum advantage of their abilities.
It is important to note that Auto-negotiation does not
test the link segment characteristics. The
Auto-Negotiation function provides a means for a
device to advertise supported modes of operation to
a remote link partner, acknowledge the receipt and
understanding of common modes of operation, and to
reject un-shared modes of operation. This allows
devices on both ends of a segment to establish a link
at the best common mode of operation. If more than
one common mode exists between the two devices, a
mechanism is provided to allow the devices to
resolve to a single mode of operation using a
predetermined priority resolution function.
7.2.20 10Base-T Operation
The 10Base-T transceiver is IEEE 802.3u compliant.
When the DM9620 is operating in 10Base-T mode,
the coding scheme is Manchester. Data processed
for transmit is presented to the MII interface in nibble
format, converted to a serial bit stream, then
Manchester encoded. When receiving, the
Manchester encoded bit stream is decoded and
converted into nibble format for presentation to the
MII interface.
7.2.21 Collision Detection
For half-duplex operation, a collision is detected
when the transmit and receive channels are active
simultaneously. When a collision has been detected,
it will be reported by the COL signal on the MII
interface. Collision detection is disabled in Full
Duplex operation.
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Carrier Sense (CRS) is asserted in half-duplex
operation during transmission or reception of data.
During full-duplex mode, CRS is asserted only during
receive operations.
7.2.24 Auto-Negotiation (continued)
Auto-negotiation also provides a parallel detection
function for devices that do not support the
Auto-negotiation feature. During Parallel detection
there is no exchange of configuration information,
instead, the receive signal is examined. If it is
discovered that the signal matches a technology that
the receiving device supports, a connection will be
automatically established using that technology. This
allows devices that do not support Auto-negotiation
but support a common mode of operation to establish
a link.
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DM9620
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8. DC and AC Electrical Characteristics
8.1 Absolute Maximum Ratings
Symbol
Parameter
DVDD
Supply Voltage
VIN
DC Input Voltage (VIN)
VOUT
DC Output Voltage(VOUT)
Storage Temperature range
TSTG
Ambient
Temperature
TA
Lead Temperature
LT
(LT, soldering, 10 sec.).
*1: Power pin
*2: IO pin
Min.
-0.3
-0.5
-0.3
-65
0
-
Max.
3.6
5.5
3.6
+150
+70
+245
Unit
V
V
V
°C
°C
°C
Conditions
*1
*2
*2
-
8.1.1 Operating Conditions
Symbol
DVDD
Parameter
Supply Voltage
Min.
Typ.
Max.
Unit
3.135
3.300
3.465
V
Conditions
PD
100BASE-TX
---
180
---
mA
3.3V
(Power
10BASE-T TX
---
200
---
mA
3.3V
Dissipation)
10BASE-T idle
---
110
---
mA
3.3V,power
saving
*1
USB suspend mode
---
2.48
---
mA
3.3V
*1: demo board testing result
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
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DM9620
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8.2 DC Electrical Characteristics (VDD = 3.3V)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Inputs
VIL
Input Low Voltage
-
-
0.8
V
VIH
Input High Voltage
2.0
-
-
V
IIL
Input Low Leakage Current
-1
-
-
uA
VIN = 0.0V
IIH
Input High Leakage Current
-
-
1
uA
VIN = 3.3V
VOL
Output Low Voltage
-
-
0.4
V
IOL = 4mA
VOH
Output High Voltage
2.4
-
-
V
IOH = -4mA
-
1.8
-
V
100 Ω Termination
Outputs
Receiver
VICM
RX+/RX- Common Mode Input
Voltage
Across
Transmitter
VTD100
100TX+/- Differential Output
1.9
2.0
2.1
V
Peak to Peak
4.4
5
5.6
V
Peak to Peak
│19│
│20│
│21│
mA
Absolute Value
│44│
│50│
│56│
mA
Absolute Value
Min.
Typ.
Max.
Unit
Voltage
VTD10
10TX+/- Differential Output Voltage
ITD100
100TX+/- Differential Output
Current
ITD10
10TX+/- Differential Output Current
8.3 AC Electrical Characteristics & Timing Waveforms
8.3.1 TP Interface
Symbol
Parameter
tTR/F
100TX+/- Differential Rise/Fall Time
3.0
-
5.0
ns
tTM
100TX+/- Differential Rise/Fall Time
0
-
0.5
ns
0
-
0.5
ns
0
-
1.4
ns
0
-
5
%
Conditions
Mismatch
tTDC
100TX+/- Differential Output Duty Cycle
Distortion
Tt/T
100TX+/- Differential Output Peak-to-Peak
Jitter
XOST
100TX+/- Differential Voltage Overshoot
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
58
DM9620
USB2.0 to Fast Ethernet Controller
8.3.2 Oscillator/Crystal Timing ( 25°C )
Symbol
Parameter
TCKC
TPWH
TPWL
OSC Clock Cycle
OSC Pulse Width High
OSC Pulse Width Low
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Min.
39.9988
-
Typ
.
40
20
20
Max.
Unit
Conditions
40.0012
-
ns
ns
ns
30ppm
59
DM9620
USB2.0 to Fast Ethernet Controller
9. AC Timing waveform:
9.1 Power On Reset Timing
T1
Power on
T2
PWRST#
T3
T6
Strap pins
T4
EECS
T5
Symbol
T1
T2
T3
T4
T5
T6
Parameter
Power on reset time
PWRST# Low Period
Strap pin setup time with PWRST#
Strap pin hold time with PWRST#
PWRST# high to EECS high
PWRST# high to EECS burst end
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Min.
15
5
40
40
-
Typ.
1
--
Max.
1.85
Unit
ms
ms
ns
ns
us
ms
Conditions
-
60
DM9620
USB2.0 to Fast Ethernet Controller
9.2 EEPROM timing
T1
EECS
T2
EECK
T4
EEDIO
T5
T3
Symbol
T1
T2
T3
T4
T5
Parameter
EECS Hold Time
EECK cycle time
EEDIO Hold Time in output state
EEDIO Setup Time in input state
EEDIO Hold Time in input state
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Min.
8
1
Typ.
4.2
5.12
4.2
Max.
Unit
us
us
us
ns
ns
61
DM9620
USB2.0 to Fast Ethernet Controller
9.3 MII Management Timing
T1
MDC
MDIO (from DM9620)
T2
T3
MDIO (to DM9620)
T4
Symbol
T1
T2
T3
T4
Parameter
MDC Frequency
MDIO by DM9620 Delay Time
MDIO by External MII Setup Time
MDIO by External MII Hold Time
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Min.
368
1
Typ.
1.04
600
Max.
Unit
MHz
ns
ns
ns
62
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USB2.0 to Fast Ethernet Controller
9.4 MII TX timing
TXC
TXE
T1
TXD_3~0
Symbol
Parameter
T1
TXE,TXD_3~0 Delay Time
Min.
Typ.
5
Max.
Unit
ns
Max.
Unit
ns
ns
9.5 MII RX timing
RXC
RXER,RXDV
T1
T2
RXD_3~0
Symbol
Parameter
T1
RXDV,RXER, RXD_3~0 Setup Time
T2
RXDV, RXER, RXD_3~0 Hold Time
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Min.
2
2
Typ.
63
DM9620
USB2.0 to Fast Ethernet Controller
9.6 RMII TX timing
CLK50M
TXE
T1
TXD_1~0
Symbol
Parameter
T1
TXE,TXD_1~0 Delay Time
Min.
Typ.
7
Max.
Unit
ns
Max.
Unit
ns
ns
9.7 RMII RX timing
CLK50M
RXDV
T1
T2
RXD_1~0
Symbol
Parameter
T1
RXDV,RXD_1~0 Setup Time
T2
RXDV,RXD_1~0 Hold Time
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Min.
3
2
Typ.
64
DM9620
USB2.0 to Fast Ethernet Controller
9.8 RevMII TX timing
TXC
TXE
T1
TXD_3~0
Symbol
Parameter
T1
TXE,TXD_3~0 Delay Time
Min.
3
Typ.
8
Max.
13
Unit
ns
Max.
Unit
ns
ns
9.9 RevMII RX timing
RXC
RXDV
T1
T2
RXD_3~0
Symbol
Parameter
T1
RXDV, RXD_3~0 Setup Time
T2
RXDV, RXD_3~0 Hold Time
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Min.
2
2
Typ.
65
DM9620
USB2.0 to Fast Ethernet Controller
10 Magnetic and Crystal Selection Guide
10.1 Magnetic Selection Guide
Refer to Table 1 for transformer requirements.
Transformers, meeting these requirements, are
available from a variety of magnetic manufacturers.
Designers should test and qualify all magnetic before
using them in an application. The transformers listed
in Table 1 are electrical equivalents, but may not be
pin-to-pin equivalents. Designers should test and
qualify all magnetic specifications before using them
in an application. RoHS regulations, please contact
with your magnetic vendor, this table only for you
reference
Manufacturer
Part Number
DELTA
LFE8505-DC , LFE8563-DC, LFE8583-DC
MAGCOM
HS9016, HS9024
Halo
TG110-S050N2, TG110-LC50N2
Bel Fuse
S558-5999-W2
Table
10.2 Crystal Selection Guide
A crystal can be used to generate the 25MHz /
12MHz (Option) reference clock instead of an
oscillator. The crystal must be a fundamental type,
and series-resonant. Connects to pins X1 and X2,
and shunts each crystal lead to ground with a 15pf
capacitor (see figure 10-1).
PARAMETER
SPEC
Type
Fundamental, series-resonant
Frequency
25.000 MHz +/- 30ppm
Equivalent Series Resistance
25 ohms max
Load Capacitance
22 pF typ.
Case Capacitance
7 pF max.
Power Dissipation
1mW max.
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
66
DM9620
USB2.0 to Fast Ethernet Controller
X1
X2
60
61
25MHz
15pf
GND
15pf
G ND
Figure 10-1
Crystal Circuit Diagram
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
67
DM9620
USB2.0 to Fast Ethernet Controller
11. Application circuit
DM9620 Reverse MII Block Diagram
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
68
DM9620
USB2.0 to Fast Ethernet Controller
DM9620 Reduce MII Block Diagram
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
69
DM9620
USB2.0 to Fast Ethernet Controller
12. Package Information
64 Pins LQFP Package Outline Information:
Symbol
A
A1
A2
b
b1
c
c1
D
D1
E
E1
e
L
L1
R1
R2
S
θ
θ1
θ2
θ3
Min
0.05
1.35
0.17
0.17
0.09
0.09
0.45
0.08
0.08
0.20
0o
0o
Dimension in mm
Nom
1.40
0.22
0.20
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.50 BSC
0.60
1.00 REF
3.5o
12o TYP
o
12 TYP
Max
1.60
0.15
1.45
0.27
0.23
0.20
0.16
0.75
0.20
7o
-
Dimension in inch
Min
Nom
Max
0.063
0.002
0.006
0.053
0.055
0.057
0.007
0.009
0.011
0.007
0.008
0.009
0.004
0.008
0.004
0.006
0.472 BSC
0.394 BSC
0.472 BSC
0.394 BSC
0.020 BSC
0.018
0.024
0.030
0.039 REF
0.003
0.003
0.008
0.008
0o
3.5o
7o
o
0
12o TYP
o
12 TYP
1. Dimension D1 and E1 do not include resin fin.
2. All dimensions are base on metric system.
3. General appearance spec should base on its final visual inspection spec.
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
70
DM9620
USB2.0 to Fast Ethernet Controller
13. Ordering Information
Part Number
Pin Count
DM9620EP
64
application circuits illustrated in this document are for
reference purposes only.
Package
LQFP
(Pb-Free)
Disclaimer
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
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warranty and patent indemnification provisions
stipulated in the terms of sale only. DAVICOM makes
no warranty, express, statutory, implied or by
description regarding the information in this
publication or regarding the information in this
publication or regarding the freedom of the described
chip(s) from patent infringement.
FURTHER,
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MAKES
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WARRANTY
OF
MERCHANTABILITY OR FITNESS FOR ANY
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inconsistent with these unless DAVICOM agrees
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Company Overview
DAVICOM Semiconductor Inc. develops and
manufactures integrated circuits for integration into
data communication products. Our mission is to
design and produce IC products that are the
industry’s best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal,
we have built an organization that is able to develop
chipsets in response to the evolving technology
requirements of our customers while still delivering
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Products
We offer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards. Our currently
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WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near
the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and function.
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
71