Seme LAB DMD5010-A Rohs compliant metal gate rf silicon fet Datasheet

TetraFET
DMD5010
DMD5010-A
ROHS COMPLIANT METAL GATE RF SILICON FET
MECHANICAL DATA
B
C
(2 pls)
2
G
(typ)
3
1
H
P
(2 pls) A
D
5
4
E
(4 pls)
GOLD METALLISED
MULTI-PURPOSE SILICON
DMOS RF FET
125W – 50V – 400MHz
PUSH–PULL
F
I
FEATURES
N
M
O
J
K
• SIMPLE BIAS CIRCUITS
D1
PIN 1
PIN 3
PIN 5
SOURCE (COMMON)
DRAIN 2
GATE 1
DIM
A
B
C
D
E
F
G
H
I
J
K
M
N
O
P
Millimetres
15.24
10.80
45°
9.78
8.38
27.94
1.52R
10.16
21.84
0.10
1.96
1.02
4.45
34.04
1.63R
• SUITABLE FOR BROAD BAND APPLICATIONS
PIN 2
PIN 4
DRAIN 1
GATE 2
• ULTRA-LOW THERMAL RESISTANCE
• BeO FREE
Tol.
0.50
0.13
5°
0.13
0.13
0.13
0.13
0.15
0.23
0.02
0.13
0.13
0.38
0.13
0.13
Inches
0.600
0.425
45°
0.385
0.330
1.100
0.060R
0.400
0.860
0.004
0.077
0.040
0.175
1.340
0.064R
Tol.
0.020
0.005
5°
0.005
0.005
0.005
0.005
0.006
0.009
0.001
0.005
0.005
0.015
0.005
0.005
• LOW Crss
• HIGH GAIN – 13 dB MINIMUM
APPLICATIONS
• VHF/UHF COMMUNICATIONS
from 1 MHz to 500 MHz
ABSOLUTE MAXIMUM RATINGS (Tcase = 25°C unless otherwise stated)
PD
BVDSS
BVGSS
ID(sat)
Tstg
Tj
Power Dissipation
Drain – Source Breakdown Voltage *
Gate – Source Breakdown Voltage*
Drain Current*
Storage Temperature
Maximum Operating Junction Temperature
648W (389W -A Version)
125V
±20V
12A
–65 to 150°C
200°C
* Per Side
Semelab Plc reserves the right to change test conditions, parameter limits and package dimensions without notice. Information furnished by Semelab is believed
to be both accurate and reliable at the time of going to press. However Semelab assumes no responsibility for any errors or omissions discovered in its use.
Semelab encourages customers to verify that datasheets are current before placing orders.
Semelab plc.
Telephone +44(0)1455 556565. Fax +44(0)1455 552612.
Website: http://www.semelab.co.uk
E-mail: [email protected]
Document Number 7347
Issue 1
DMD5010
DMD5010-A
ELECTRICAL CHARACTERISTICS (Tcase = 25°C unless otherwise stated)
Parameter
Test Conditions
Min.
Typ.
Max. Unit
PER SIDE
BVDSS
IDSS
Drain–Source Breakdown
Voltage
Zero Gate Voltage
Drain Current
ID = 100mA
VDS = 50V
VGS = 0
4
mA
1
μA
7
V
IGSS
Gate Leakage Current
VGS = 20V
VDS = 0
VGS(th)
Gate Threshold Voltage*
ID = 10mA
VDS = VGS
gfs
Forward Transconductance*
VDS = 10V
ID = 2A
ID = 10mA
VDS = VGS
VGS(th)match
Gate Threshold Voltage
Matching Between Sides
V
VGS = 0
125
1
mhos
3.2
0.1
V
TOTAL DEVICE
GPS
Common Source Power Gain
PO = 125W
η
Drain Efficiency
VDS = 50V
VSWR
Load Mismatch Tolerance
f = 400MHz
Ciss
Input Capacitance
VDS = 50V
VGS = –5V f = 1MHz
240
pF
Coss
Output Capacitance
VDS = 50V
VGS = 0
f = 1MHz
100
pF
Crss
Reverse Transfer Capacitance VDS = 50V
VGS = 0
f = 1MHz
6
pF
IDQ = 1.4A
13
dB
60
%
20:1
—
PER SIDE
* Pulse Test:
Pulse Duration = 300 μs , Duty Cycle ≤ 2%
THERMAL DATA
RTHj–case
Thermal Resistance Junction – Case
Max. 0.27°C / W
0.45 °C / W -A Version
Semelab Plc reserves the right to change test conditions, parameter limits and package dimensions without notice. Information furnished by Semelab is believed
to be both accurate and reliable at the time of going to press. However Semelab assumes no responsibility for any errors or omissions discovered in its use.
Semelab encourages customers to verify that datasheets are current before placing orders.
Semelab plc.
Telephone +44(0)1455 556565. Fax +44(0)1455 552612.
Website: http://www.semelab.co.uk
E-mail: [email protected]
Document Number 7347
Issue 1
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