Dallas DS1706P 3.3 and 5.0 volt micromonitor Datasheet

DSDS1705/DS1706
DS1705/DS1706
3.3 and 5.0 Volt MicroMonitor
FEATURES
PIN ASSIGNMENT
• Halts and restarts an out–of–control microprocessor
• Holds
microprocessor in check during power tran-
sients
• Automatically
restarts microprocessor after power
PBRST
1
8
WDS
VCC
2
7
RST
GND
3
6
ST
IN
4
5
NMI
failure
8–PIN DIP
(300 MIL)
• Monitors pushbutton for external override
• Accurate 5%, 10% or 20% resets for 3.3 systems and
5% or 10% resets for 5.0 volt systems
• Eliminates the need for discrete components
WDS
PBRST
1
8
VCC
2
7
RST (*RST)
GND
3
6
ST
IN
4
5
NMI
• 3.3 volt 20% tolerance for use with 3.0 volt systems
8–PIN SOIC
(150 MIL)
• Pin compatible with the MAXIM MAX705/MAX706 in
PBRST
VCC
GND
IN
8–pin DIP and 8–pin SOIC
• 8–pin DIP, 8–pin SOIC and 8–pin µ–SOP packages
1
2
3
4
8
7
6
5
WDS
RST (*RST)
ST
NMI
8–PIN µ–SOP
(118 MIL)
• Industrial temperature range –40°C to +85°C
See Mech. Drawings
Section
DS1705 and DS1706_/R/S/T (*DS1706L and DS1706P)
PIN DESCRIPTION
PBRST
VCC
GND
IN
NMI
ST
RST
*RST
WDS
–
–
–
–
–
–
–
–
Pushbutton Reset Input
Power Supply
Ground
Input
Non–maskable Interrupt
Strobe Input
Active Low Reset Output
Active High Reset Output
(DS1706P and DS1706L only)
– Watchdog Status Output
DESCRIPTION
The DS1705/DS1706 3.3 or 5.0 Volt MicroMonitor monitors three vital conditions for a microprocessor: power
supply, software execution, and external override. A
precision temperature compensated reference and
comparator circuit monitors the status of VCC at the
device and at an upstream point for maximum protection. When the sense input detects an out–of–tolerance
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
condition a non–maskable interrupt is generated. As
the voltage at the device degrades an internal power fail
signal is generated which forces the reset to an active
state. When VCC returns to an in–tolerance condition,
the reset signal is kept in the active state for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
011296 1/10
DS1705/DS1706
The second function the DS1705/DS1706 performs is
pushbutton reset control.
The DS1705/DS1706
debounces the pushbutton input and guarantees an
active reset pulse width of 130 ms minimum.
The third function is a watchdog timer.
The
DS1705/DS1706 has an internal timer that forces the
WDO signal to the active state if the strobe input is not
driven low prior to time–out.
OPERATION
Power Monitor
The DS1705/DS1706 detects out–of–tolerance power
supply conditions and warns a processor–based system of impending power failure. When VCC falls below
the minimum VCC tolerance, a comparator outputs the
RST (or RST) signal. RST (or RST) is an excellent control signal for a microprocessor, as processing is
stopped at the last possible moment of valid VCC. On
power–up, RST (or RST) are kept active for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
DS1705/DS1706 requires that the voltage at the IN pin
be limited to VCC. Therefore, the maximum allowable
voltage at the supply being monitored (VMAX) can also
be derived as shown in Figure 5. A simple approach to
solving the equation is to select a value for R2 high
enough to keep power consumption low, and solve for
R1. The flexibility of the IN input pin allows for detection
of power loss at the earliest point in a power supply system, maximizing the amount of time for system shut–
down between NMI and RST (or RST).
When the supply being monitored decays to the voltage
sense point, the DS1705/DS1706 pulses the NMI output to the active state for a minimum 200 µs. The NMI
power fail detection circuitry also has built–in hysteresis
of 100 µV. The supply must be below the voltage sense
point for approximately 5 µs before a low NMI will be
generated. In this way, power supply noise is removed
from the monitoring function, preventing false interrupts. During a power–up, any detected IN pin levels
below VTP by the comparator are disabled from generating an interrupt until VCC rises to VCCTP. As a result,
any potential NMI pulse will not be initiated until VCC
reaches VCCTP.
Pushbutton Reset
The DS1705/DS1706 provides an input pin for direct
connection to a push–button reset (see Figure 2). The
pushbutton reset input requires an active low signal.
Internally, this input is debounced and timed such that a
RST (or RST) signal of at least 130 ms minimum will be
generated. The 130 ms delay commences as the pushbutton reset input is released from the low level. The
push–button can be initiated by connecting the WDS or
NMI outputs to the PBRST input as shown in Figure 3.
Non–Maskable Interrupt
The DS1705/DS1706 generates a non–maskable interrupt (NMI) for early warning of a power failure. A precision comparator monitors the voltage level at the IN pin
relative to an on–chip reference generated by an internal band gap. The IN pin is a high impedance input
allowing for a user–defined sense point. An external
resistor voltage divider network (Figure 5) is used to
interface with high voltage signals. This sense point
may be derived from a regulated supply or from a higher
DC voltage level closer to the main system power input.
Since the IN trip point VTP is 1.25 volts, the proper values for R1 and R2 can be determined by the equation as
shown in Figure 5.
Proper operation of the
011296 2/10
Connecting NMI to PBRST would allow non–maskable
interrupt to generate an automatic reset when an out–
of–tolerance condition occurred in a monitored supply.
An example is shown in Figure 3.
Watchdog Timer
The watchdog timer function forces WDS signals active
when the ST input is not clocked within the 1 second
time out period. Timeout of the watchdog starts when
RST (or RST) becomes inactive. If a high–to–low transition occurs on the ST input pin prior to time–out, the
watchdog timer is reset and begins to time–out again. If
the watchdog timer is allowed to time out, the WDS signal is driven active (low) for a minimum of 130 ms. The
ST input can be derived from many microprocessor outputs. The typical signals used are the microprocessors
address signals, data signals, or control signals. When
the microprocessor functions normally, these signals
would, as a matter of routine, cause the watchdog to be
reset prior to time–out. To guarantee that the watchdog
timer does not time–out, a high–to–low transition must
occur at or less than the minimum watchdog time–out of
1 second. A typical circuit example is shown in Figure 6.
DS1705/DS1706
MICROMONITOR BLOCK DIAGRAM Figure 1
IN
–
DIGITAL
SAMPLER
+
T.C.
REFERENCE
VCC
PBRST
NMI
–
DIGITAL
SAMPLER
+
DIGITAL
DELAY
RST
DS1706_/A/R/S/T
RST
DS1706L/DS1706P
LEVEL SENSE
AND
DEBOUNCE
WATCHDOG
STATUS
LATCH
ST
WDS
PUSH–BUTTON RESET Figure 2
PBRST
8051
µP
WDS
VCC
RST
RST
DS1706P
ST
GND
ALE
NMI
IN
PUSH–BUTTON RESET CONTROLLED BY NMI AND WDS Figure 3
UPSTREAM
SUPPLY
VOLTAGE
VCC
RST
DS1706
GND
IN
µP
WDS
PBRST
RST
ST
ALE
NMI
011296 3/10
DS1705/DS1706
TIMING DIAGRAM: PUSHBUTTON RESET Figure 4
tPDLY
PBRST
tPB
VIH
VIL
tRST
RST
VOH
VOL
RST
NON–MASKABLE INTERRUPT CIRCUIT EXAMPLE Figure 5
PBRST
WDS
VCC
VSENSE
RST
DS1706
ST
GND
R1
TO µP
NMI
IN
R2
V SENSE R1 R2 x 1.25
R2
Example:
Therefore:
VSENSE = 4.50 volts at the trip point
VCC = 3.3 volts
10KΩ = R2
4.50 x 3.3 12.4 volts maximum
1.25
4.5 R1 10K x 1.25
10K
011296 4/10
V MAX R1 26K
V SENSE
x V CC
V TP
DS1705/DS1706
WATCHDOG TIMER Figure 6
Z80
µP
WDS
PBRST
VCC
RST
RST
DS1706
MREQ
ST
GND
DECODER
NMI
IN
ADDRESS
BUS
TIMING DIAGRAM: STROBE INPUT Figure 7
INVALID
STROBE
INDETERMINATE
STROBE
VALID
STROBE
ST
MIN.
MAX.
tTD
WDS
RST
RESET INITIATED
BY PUSHBUTTON
TIMING DIAGRAM: NON–MASKABLE INTERRUPT Figure 8
VIN > 1.25V
VTP(MAX)
VTP
VTP(MAX)
VTP
VTP(MIN)
tIPD
VTP(MIN)
tIPD
NMI
VOH
VOL
011296 5/10
DS1705/DS1706
TIMING DIAGRAM: POWER DOWN Figure 9
tF
VCC
VCCTP(MAX)
VCCTP
VCCTP(MIN)
tRPD
RST
(DS1705 AND DS1706_/R/S/T)
VOH
VOL
RST
(DS1706L AND DS1706P ONLY)
WDS
WDS SLEWS WITH VCC
011296 6/10
RST SLEWS WITH VCC
DS1705/DS1706
TIMING DIAGRAM: POWER UP Figure 10
VCCTP(MAX)
VCCTP
VCCTP(MIN)
VCC
tRPU
RST
RST
RST
VOH
(DS1705 AND DS1706_/R/S/T)
VOL
RST
(DS1706L AND DS1706P ONLY)
WDS
011296 7/10
DS1705/DS1706
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to Ground
Voltage on I/O Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
–0.5V to +7.0V
–0.5V to VCC + 0.5V
–40°C to +85°C
–55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(–40°C to +85°C)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Supply Voltage
VCC
1.0
TYP
5.5
V
1
ST and PBRST Input High Level
VIH
2.0
VCC–0.5
VCC+0.3
V
1, 3
1, 4
ST and PBRST Input Low Level
VIL
–0.03
+0.5
V
1
DC ELECTRICAL CHARACTERISTICS
PARAMETER
(–40°C to +85°C; VCC=1.2V to 5.5V)
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
VCC Trip Point DS1705/DS1706L
VCCTP
4.50
4.65
4.75
V
1
VCC Trip Point DS1706
VCCTP
4.25
4.40
4.50
V
1
VCC Trip Point DS1706T
VCCTP
3.00
3.08
3.15
V
1
VCC Trip Point DS1706S
VCCTP
2.85
2.93
3.00
V
1
VCC Trip Point DS1706P or R
VCCTP
2.55
2.63
2.70
V
1
Input Leakage
IIL
–1.0
+1.0
µA
2
Output Current @ 2.4 volts
IOH
µA
3
Output Current @ 0.4 volts
IOL
10
mA
3
Output Voltage @ –500 µA
VOH
VCC+–0.3
V
3
Operating Current
@ VCC < 5.5 volts
ICC
60
µA
5
Operating Current
@ VCC < 3.6 volts
ICC
50
µA
5
IN Input Trip Point
VTP
1.30
V
1
350
1.20
VCC–0.1
1.25
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
011296 8/10
(tA=25°C)
SYMBOL
MIN
TYP
MAX
UNITS
CIN
5
pF
COUT
7
pF
NOTES
DS1705/DS1706
AC ELECTRICAL CHARACTERISTICS
(–40°C to +85°C; VCC=1.2V to 5.5V)
PARAMETER
SYMBOL
MIN
PBRST = VIL
tPB
150
Reset Active Time
tRST
130
ST Pulse Width
tST
10
VCC Detect to RST and RST
tRPD
VCC Slew Rate
VCC Detect to RST and RST
20
tRPU
130
tR
0
PBRST Stable Low to RST and
RST
205
tTD
VIN Detect to NMI
tIPD
1.0
UNITS
NOTES
285
8
ms
ns
6
µs
9
µs
205
285
ms
7
ns
tPDLY
Watchdog Timeout
MAX
ns
5
tF
VCC Slew Rate
TYP
250
ns
1.6
2.2
s
8
5
8
µs
9
NOTES:
1. All voltages are referenced to ground.
2. PBRST is internally pulled up to VCC with an internal impedance of 40KΩ typical and the ST input is internally
pulled up to VCC with an internal impedance of 180KΩ typical.
3. VCC 2.4 volts
4. VCC < 2.4 volts
5. Measured with outputs open and all inputs at VCC or ground.
6. Must not exceed tTD minimum.
7. tR = 5 µs
8. Minimum watchdog timeout tested at 2.7 volts for the 3.3 volt devices and 4.5 volts for the 5.0 volt devices.
9. Noise immunity – pulses < 2 µs at VCCTP minimum will not cause a reset.
011296 9/10
DS1705/DS1706
PART MARKING CODES
8 7 6 5
ABCD
WWY
1 2 3 4
8–PIN µ–SOP
(118 MIL)
A, B, C and D represents the device type and tolerance.
ABCD
705_
706_
706L
706P
706R
706S
706T
–
–
–
–
–
–
–
DS1705
DS1706
DS1706L
DS1706P
DS1706R
DS1706S
DS1706T
WWY represents the device manufacturing Work
Week, Year.
011296 10/10
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