Dallas DS1708R 3.3 and 5.0 volt micromonitorã Datasheet

DS1707/DS1708
DS1707/DS1708
3.3 and 5.0 Volt MicroMonitor
FEATURES
• Holds
PIN ASSIGNMENT
microprocessor in check during power tran-
sients
• Automatically
restarts microprocessor after power
failure
PBRST
1
8
RST
VCC
2
7
RST
GND
3
6
NC
IN
4
5
NMI
• Monitors pushbutton for external override
8–PIN DIP
(300 MIL)
• Accurate 5%, 10% or 20% resets for 3.3 systems and
5% or 10% resets for 5.0 volt systems
• Eliminates the need for discrete components
• 20% tolerance compatible with 3.0 volt systems
PBRST
1
8
RST
VCC
2
7
RST
GND
3
6
NC
IN
4
5
NMI
• Pin compatible with the MAXIM MAX707/MAX708 in
8–PIN SOIC
(150 MIL)
8–pin DIP and 8–pin SOIC packages
PBRST
VCC
GND
IN
• 8–pin DIP, 8–pin SOIC and 8–pin µ–SOP packages
available
• Industrial temperature range –40°C to +85°C
1
2
3
4
8
7
6
5
RST
RST
NC
NMI
8–PIN µ–SOP
(118 MIL)
See Mech. Drawings
Section
DS1707 and DS1708_/R/S/T
PIN DESCRIPTION
PBRST
VCC
GND
IN
NMI
NC
RST
RST
–
–
–
–
–
–
–
–
Pushbutton Reset Input
Power Supply
Ground
Input
Non–maskable Interrupt
No Connect
Active Low Reset Output
Active High Reset Output
DESCRIPTION
The DS1707/DS1708 3.3 or 5.0 Volt MicroMonitor monitors three vital conditions for a microprocessor: power
supply, voltage sense, and external override. A precision temperature–compensated reference and
comparator circuit monitors the status of VCC at the
device and at an upstream point for maximum protection. When the sense input detects an out–of–tolerance
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
condition a non–maskable interrupt is generated. As
the voltage at the device degrades an internal power fail
signal is generated which forces the reset to an active
state. When VCC returns to an in–tolerance condition,
the reset signal is kept in the active state for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
010996 1/9
DS1707/DS1708
The third function the DS1707/DS1708 performs is
pushbutton reset control.
The DS1707/DS1708
debounces the pushbutton input and guarantees an
active reset pulse width of 130 ms minimum.
OPERATION
Power Monitor
The DS1707/DS1708 detects out–of–tolerance power
supply conditions and warns a processor–based system of impending power failure. When VCC falls below
the minimum VCC tolerance, a comparator outputs the
RST and RST signals. RST and RST are excellent control signals for a microprocessor, as processing is
stopped at the last possible moment of valid VCC. On
power–up, RST and RST are kept active for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
Pushbutton Reset
The DS1707/DS1708 provides an input pin for direct
connection to a pushbutton reset (see Figure 2). The
pushbutton reset input requires an active low signal.
Internally, this input is debounced and timed such that
RST and RST signals of at least 130 ms minimum will be
generated. The 130 ms delay commences as the pushbutton reset input is released from the low level. The
pushbutton can be initiated by connecting the NMI output to the PBRST input as shown in Figure 3.
Non–Maskable Interrupt
The DS1707/DS1708 generates a non–maskable interrupt (NMI) for early warning of a power failure. A precision comparator monitors the voltage level at the IN pin
relative to an on–chip reference generated by an internal band gap. The IN pin is a high impedance input
allowing for a user–defined sense point. An external
010996 2/9
resistor voltage divider network (Figure 5) is used to
interface with high voltage signals. This sense point
may be derived from a regulated supply or from a higher
DC voltage level closer to the main system power input.
Since the IN trip point VTP is 1.25 volts, the proper values for R1 and R2 can be determined by the equation as
shown in Figure 5.
Proper operation of the
DS1707/DS1708 requires that the voltage at the IN pin
be limited to VCC. Therefore, the maximum allowable
voltage at the supply being monitored (VMAX) can also
be derived as shown in Figure 5. A simple approach to
solving the equation is to select a value for R2 high
enough to keep power consumption low, and solve for
R1. The flexibility of the IN input pin allows for detection
of power loss at the earliest point in a power supply system, maximizing the amount of time for system shut–
down between NMI and RST/RST.
When the supply being monitored decays to the voltage
sense point, the DS1707/DS1708 pulses the NMI output to the active state for a minimum 200 µs. The NMI
power fail detection circuitry also has built–in hysteresis
of 100 µV. The supply must be below the voltage sense
point for approximately 5 µs before a low NMI will be
generated. In this way, power supply noise is removed
from the monitoring function, preventing false interrupts. During a power–up, any detected IN pin levels
below VTP by the comparator are disabled from generating an interrupt until VCC rises to VCCTP. As a result,
any potential NMI pulse will not be initiated until VCC
reaches VCCTP.
Connecting NMI to PBRST would allow the non–maskable interrupt to generate an automatic reset when an
out–of–tolerance condition occurred in a monitored
supply. An example is shown in Figure 3.
DS1707/DS1708
MICROMONITOR BLOCK DIAGRAM Figure 1
IN
–
DIGITAL
SAMPLER
+
T.C.
REFERENCE
–
DIGITAL
SAMPLER
+
VCC
NMI
DIGITAL
DELAY
RST
RST
LEVEL SENSE
AND
DEBOUNCE
PBRST
PUSHBUTTON RESET Figure 2
PBRST
5V
UPSTREAM
SUPPLY
VOLTAGE
RST
VCC
RST
RST
8051
µP
DS1708
GND
NC
IN
NMI
INT0
PUSHBUTTON RESET CONTROLLED BY NMI Figure 3
µP
PBRST
RST
UPSTREAM
SUPPLY
VOLTAGE
5V
VCC
RST
DS1707
GND
IN
RST
NC
NMI
010996 3/9
DS1707/DS1708
TIMING DIAGRAM: PUSHBUTTON RESET Figure 4
tPDLY
PBRST
tPB
VIH
VIL
tRST
RST
VOH
VOL
RST
NON–MASKABLE INTERRUPT CIRCUIT EXAMPLE Figure 5
PBRST
RST
VCC
VSENSE
RST
DS1708
GND
TO µP
NC
R1
NMI
IN
R2
V SENSE R1 R2 x 1.25
R2
Example:
Therefore:
V SENSE
x V CC
V TP
VSENSE = 4.70 volts at the trip point
VCC = 3.3 volts
10KΩ = R2
4.70 x 3.3 12.4 volts maximum
1.25
4.5 R1 10K x 1.25
10K
010996 4/9
V MAX R1 27.6K
DS1707/DS1708
TIMING DIAGRAM: NON–MASKABLE INTERRUPT Figure 6
VIN > 1.25V
VTP(MAX)
VTP
VTP(MAX)
VTP
VTP(MIN)
VTP(MIN)
tIPD
tIPD
NMI
VOH
VOL
TIMING DIAGRAM: POWER DOWN Figure 7
tF
VCC
VCCTP(MAX)
VCCTP
VCCTP(MIN)
tRPD
RST
VOH
RST
RST SLEWS WITH VCC
VOL
010996 5/9
DS1707/DS1708
TIMING DIAGRAM: POWER UP Figure 8
tR
VCCTP(MAX)
VCCTP
VCCTP(MIN)
VCC
tRPU
RST
RST
VOH
RST
010996 6/9
VOL
RST
DS1707/DS1708
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to Ground
Voltage on I/O Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
–0.5V to +7.0V
–0.5V to VCC +0.5V
–40°C to +85°C
–55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(–40°C to +85°C)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Supply Voltage
VCC
1.0
TYP
5.5
V
1
PBRST Input High Level
VIH
2.0
VCC–0.5
VCC+0.3
V
1, 3
1, 4
PBRST Input Low Level
VIL
–0.03
+0.5
V
1
DC ELECTRICAL CHARACTERISTICS
PARAMETER
(–40°C to +85°C; VCC=1.2V to 5.5V)
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
VCC Trip Point DS1707
VCCTP
4.50
4.65
4.75
V
1
VCC Trip Point DS1708
VCCTP
4.25
4.40
4.50
V
1
VCC Trip Point DS1708T
VCCTP
3.00
3.08
3.15
V
1
VCC Trip Point DS1708S
VCCTP
2.85
2.93
3.00
V
1
VCC Trip Point DS1708R
VCCTP
2.55
2.63
2.70
V
1
Input Leakage
IIL
–1.0
+1.0
µA
2
Output Current @ 2.4 volts
IOH
µA
3
Output Current @ 0.4 volts
IOL
mA
3
Output Voltage
VOH
V
3
Operating Current
@ VCC < 5.5 volts
ICC
60
µA
5
Operating Current
@ VCC < 3.6 volts
ICC
50
µA
5
IN Input Trip Point
VTP
1.30
V
1
350
10
VCC–0.1
1.20
1.25
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
(tA=25°C)
SYMBOL
MIN
TYP
MAX
UNITS
CIN
5
pF
COUT
7
pF
NOTES
010996 7/9
DS1707/DS1708
AC ELECTRICAL CHARACTERISTICS
(–40°C to +85°C; VCC=1.2V to 5.5V)
PARAMETER
SYMBOL
MIN
PBRST = VIL
tPB
150
Reset Active Time
tRST
130
VCC Detect to RST and RST
tRPD
VCC Slew Rate
VCC Detect to RST and RST
tF
20
tRPU
130
tR
0
VCC Slew Rate
PBRST Stable Low to RST and
RST
VIN Detect to NMI
TYP
205
285
ms
5
8
µs
NOTES
7
µs
205
285
ms
6
ns
5
250
ns
8
µs
NOTES:
1. All voltages are referenced to ground.
2. PBRST is internally pulled up to VCC with an internal impedance of 40KΩ typical.
3. VCC 2.4 volts
4. VCC < 2.4 volts
5. Measured with outputs open and all inputs at VCC or ground.
6. tR = 5 µs
7. Noise immunity – pulses < 2 µs at VCCTP minimum will not cause a reset.
010996 8/9
UNITS
ns
tPDLY
tIPD
MAX
7
DS1707/DS1708
PART MARKING CODES
8 7 6 5
ABCD
WWY
1 2 3 4
8–PIN µ–SOP
(118 MIL)
A, B, C and D represents the device type and tolerance.
ABCD
707_
708_
708R
708S
708T
–
–
–
–
–
DS1707
DS1708
DS1708R
DS1708S
DS1708T
WWY represents the device manufacturing Work
Week, and Year.
010996 9/9
Similar pages