Dallas DS2045AB-70 Single-piece 1mb nonvolatile sram Datasheet

Rev 2; 1/05
DS2045Y/AB Single-Piece 1Mb
Nonvolatile SRAM
Features
The DS2045 is a 1Mb reflowable nonvolatile (NV) SRAM,
which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium
(ML) battery. These components are encased in a surface-mount module with a 256-ball BGA footprint.
Whenever VCC is applied to the module, it recharges the
ML battery, powers the SRAM from the external power
source, and allows the contents of the SRAM to be modified. When VCC is powered down or out of tolerance,
the controller write-protects the SRAM’s contents and
powers the SRAM from the battery. Two versions of the
DS2045 are available, which provide either a 5% or 10%
power-monitoring trip point. The DS2045 also contains a
power-supply monitor output, RST, which can be used
as a CPU supervisor for a microprocessor.
♦ Single-Piece, Reflowable,
PBGA Package
Footprint
♦ Internal ML Battery and Charger
♦ Unconditionally Write-Protects SRAM when VCC
is Out-of-Tolerance
♦ Automatically Switches to Battery Supply when
VCC Power Failures Occur
♦ Internal Power-Supply Monitor Detects Power Fail
at 5% or 10% Below Nominal VCC (5V)
♦ Reset Output can be used as a CPU Supervisor
for a Microprocessor
♦ Industrial Temperature Range (-40°C to +85°C)
♦ UL Recognized
27mm2
Applications
RAID Systems and Servers
POS Terminals
Industrial Controllers
Data-Acquisition Systems
Gaming
Fire Alarms
Router/Switches
PLC
Pin Configuration appears at end of data sheet.
Ordering Information
PART
SPEED (ns)
SUPPLY TOLERANCE (%)
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
256 Ball 27mm2 BGA Module
70
5
DS2045AB-100
-40°C to +85°C
256 Ball 27mm2 BGA Module
100
5
DS2045Y-70
-40°C to +85°C
256 Ball 27mm2 BGA Module
70
10
DS2045Y-100
-40°C to +85°C
256 Ball 27mm2 BGA Module
100
10
DS2045AB-70
Typical Operating Circuit
P4.0
P3.6
P3.7
(CE0)
CE
(WR)
WE
(RD)
OE
AD0–AD7
8 BITS
DQ0–7
P1.0–7
8 BITS
A0–7
8051
MICROPROCESSOR
A16
P4.4
8 BITS
P2.0–7
P3.2
DS2045
128k x 8
NV SRAM
(INT0)
A8–15
RST
______________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
DS2045Y/AB
General Description
DS2045Y/AB
DS2045Y/AB Single-Piece 1Mb
Nonvolatile SRAM
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground .................-0.3V to +6.0V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range ...............................-40°C to +85°C
Soldering Temperature...................See IPC/JEDEC J-STD-020C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DS2045AB
4.75
5.25
DS2045Y
4.50
5.50
VIH
2.2
VCC
V
VIL
0
0.8
V
Supply Voltage
VCC
Input Logic 1
Input Logic 0
V
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V ±5% for DS2045AB, VCC = 5V ±10% for DS2045Y, TA = -40°C to +85°C.)
PARAMETER
Input Leakage Current
SYMBOL
CONDITIONS
IIL
MIN
MAX
UNITS
-1.0
TYP
+1.0
µA
+1.0
I/O Leakage Current
IIO
CE = VCC
-1.0
Output-Current High
IOH
At 2.4V
-1.0
mA
Output-Current Low
IOL
At 0.4V
2.0
mA
At 0.4V (Note 1)
10.0
Output-Current Low RST
Standby Current
Operating Current
Write Protection Voltage
IOL RST
mA
ICCS1
CE = 2.2V
0.5
7
ICCS2
CE = VCC - 0.5V
0.2
5
ICCO1
tRC = 200ns, outputs open
VTP
µA
85
DS2045AB
4.50
4.62
4.75
DS2045Y
4.25
4.37
4.50
MIN
TYP
MAX
mA
mA
V
CAPACITANCE
(TA = +25°C)
PARAMETER
Input Capacitance
Input/Output Capacitance
2
SYMBOL
CONDITIONS
UNITS
CIN
Not tested
7
pF
COUT
Not tested
7
pF
_____________________________________________________________________
DS2045Y/AB Single-Piece 1Mb
Nonvolatile SRAM
DS2045Y/AB
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V ±5% for DS2045AB, VCC = 5V ±10% for DS2045Y, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
DS2045AB-70
DS2045Y-70
CONDITIONS
MIN
tRC
Read Cycle Time
DS2045AB-100
DS2045Y-100
MAX
MIN
70
UNITS
MAX
100
ns
tACC
70
100
ns
OE to Output Valid
tOE
35
50
ns
CE to Output Valid
tCO
70
100
ns
OE or CE to Output Active
tCOE
Output High Impedance from
Deselection
tOD
Access Time
(Note 2)
5
(Note 2)
5
ns
25
35
ns
Output Hold from Address Change
tOH
5
5
ns
Write Cycle Time
tWC
70
100
ns
Write Pulse Width
tWP
55
75
ns
Address Setup Time
tAW
0
0
ns
(Note 3)
tWR1
(Note 4)
5
5
tWR2
(Note 5)
15
15
Output High Impedance from WE
tODW
(Note 2)
Output Active from WE
tOEW
(Note 2)
5
5
ns
tDS
(Note 6)
30
40
ns
tDH1
(Note 4)
0
0
tDH2
(Note 5)
10
10
Write Recovery Time
Data Setup Time
Data Hold Time
ns
25
35
ns
ns
POWER-DOWN/POWER-UP TIMING
(TA = -40°C to +85°C)
SYMBOL
PARAMETER
VCC Fail Detect to CE and WE Inactive
tPD
CONDITIONS
MIN
TYP
(Note 7)
MAX
1.5
UNITS
µs
VCC Slew from VTP to 0V
tF
150
µs
VCC Slew from 0V to VTP
tR
150
µs
VCC Valid to CE and WE Inactive
tPU
2
ms
VCC Valid to End of Write Protection
tREC
125
ms
VCC Fail Detect to RST Active
tRPD
(Note 1)
3.0
µs
VCC Valid to RST Inactive
tRPU
(Note 1)
225
350
525
ms
MIN
TYP
MAX
UNITS
2
3
DATA RETENTION
(TA = +25°C)
SYMBOL
PARAMETER
Expected Data-Retention Time (Per Charge)
tDR
CONDITIONS
(Note 8)
years
_____________________________________________________________________
3
DS2045Y/AB Single-Piece 1Mb
Nonvolatile SRAM
DS2045Y/AB
Read Cycle
tRC
ADDRESSES
VIH
VIH
VIH
VIL
VIL
VIL
tOH
tACC
VIH
CE
VIH
tCO
VIL
tOD
VIH
OE
tOE
VIH
VIL
tOD
tCOE
tCOE
DOUT
VOH
VOL
OUTPUT
DATA VALID
(SEE NOTE 9.)
4
_____________________________________________________________________
VOH
VOL
DS2045Y/AB Single-Piece 1Mb
Nonvolatile SRAM
tWC
ADDRESSES
VIH
VIL
VIH
VIL
VIH
VIL
tAW
CE
VIL
VIL
tWP
WE
VIH
VIL
tWR1
VIL
VIH
tOEW
tODW
HIGH
IMPEDANCE
DOUT
tDS
tDH1
VIH
VIH
DIN
DATA IN STABLE
VIL
VIL
(SEE NOTES 2, 3, 4, 6, 10–13.)
Write Cycle 2
tWC
ADDRESSES
VIH
VIL
tAW
CE
VIH
VIH
VIL
VIL
tWR2
tWP
VIH
VIH
VIL
VIL
VIL
VIH
WE
VIL
VIL
tODW
tCOE
DOUT
tDH2
tDS
VIH
VIH
DIN
DATA IN STABLE
VIL
VIL
(SEE NOTES 2, 3, 5, 6, 10–13.)
_____________________________________________________________________
5
DS2045Y/AB
Write Cycle 1
DS2045Y/AB Single-Piece 1Mb
Nonvolatile SRAM
DS2045Y/AB
Power-Down/Power-Up Condition
VCC
VTP
tDR
~2.7V
tF
tR
tREC
tPD
SLEWS WITH
VCC
CE,
WE
tPU
VIH
BACKUP CURRENT
SUPPLIED FROM
LITHIUM BATTERY
tRPD
RST
VOL
tRPU
VOL
(SEE NOTES 1, 7.)
Note 1: RST is an open-drain output and cannot source current. An external pullup resistor should be connected to this pin to realize a logic-high level.
Note 2: These parameters are sampled with a 5pF load and are not 100% tested.
Note 3: tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of
CE or WE going high.
Note 4: tWR1 and tDH1 are measured from WE going high.
Note 5: tWR2 and tDH2 are measured from CE going high.
Note 6: tDS is measured from the earlier of CE or WE going high.
Note 7: In a power-down condition, the voltage on any pin can not exceed the voltage on VCC.
Note 8: The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the
user. Minimum expected data-retention time is based on a maximum of two 230°C convection solder reflow exposures,
followed by a fully charged cell. Full charge occurs with the initial application of VCC for a minimum of 96 hours. This parameter is assured by component selection, process control, and design. It is not measured directly in production testing.
Note 9: WE is high for a read cycle.
Note 10: OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
Note 11: If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a highimpedance state during this period.
Note 12: If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a highimpedance state during this period.
Note 13: If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain
in a high-impedance state during this period.
Note 14: DS2045 BGA modules are recognized by Underwriters Laboratory (UL) under file E99151.
6
_____________________________________________________________________
DS2045Y/AB Single-Piece 1Mb
Nonvolatile SRAM
SUPPLY CURRENT
vs. OPERATING FREQUENCY
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
5
200
190
180
170
160
1MHz 50% DUTY CYCLE
0
150
4.0
4.5
5.0
5.5
6.0
4.0
4.5
5.0
DS2045 toc03
2.0
1.0
VCHRG = 3.03V
0
0.2
0
-0.1
-0.2
4.45
4.40
-0.4
4.30
3.7
-20
0
20
40
60
RST VOLTAGE
vs. VCC DURING POWER-UP
DS2045 toc08
VCC = 4.25V
VOL (V)
-2
RST OUTPUT-VOLTAGE LOW
vs. OUTPUT-CURRENT LOW
0.5
DS2045 toc07
-3
IOH (mA)
0.3
0.2
0.15
-4
TEMPERATURE (°C)
0.4
0.20
-5
80
0.10
0.1
0.05
5.5
RST VOLTAGE W/PULLUP RESISTOR (V)
DQ VOL vs. DQ IOL
0.25
0
4.1
3.5
-40
0.30
-1
4.3
3.9
DS2045Y
4.25
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
1.0
4.5
4.50
4.35
0.8
VCC = 4.5V
4.7
DS2045AB
4.55
-0.3
0.6
DQ VOH vs. DQ IOH
4.65
4.60
0.4
4.9
VOH (V)
0.1
VCC = CE = 5.0V
DELTA BELOW VCHRG (V)
4.70
WRITE PROTECT, VTP (V)
0.2
0.35
3.0
6.0
DS2045 toc05
VCC = 5.0V
VBAT = VCHRG
VCC = 4.5V
4.0
VTP vs. TEMPERATURE
-0.5
VOL (V)
5.5
4.75
DS2045 toc04
VCHRG PERCENT CHANGE FROM +25°C (%)
0.5
0.40
5.0
VCC (V)
VCHRG PERCENT CHANGE
vs. TEMPERATURE
0.3
6.0
0
VCC (V)
0.4
7.0
DS2045 toc06
1MHz 100% DUTY CYCLE
210
8.0
5.0
4.5
DS2045AB
TA = +25°C
DS2045 toc09
10
220
9.0
BATTERY CHARGER CURRENT, ICHRG (mA)
230
SUPPLY CURRENT (µA)
SUPPLY CURRENT (mA)
5MHz 50% DUTY CYCLE
TA = +25°C
240
5MHz 100% DUTY CYCLE
15
DS2045 toc02
TA = +25°C
20
250
DS2045 toc01
25
BATTERY CHARGER CURRENT
vs. BATTERY VOLTAGE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IOL (mA)
0
0
0
5
10
IOL (mA)
15
20
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCC POWER-UP (V)
_____________________________________________________________________
7
DS2045Y/AB
Typical Operating Characteristics
(VCC = +5.0V, TA = +25°C, unless otherwise noted.)
DS2045Y/AB
DS2045Y/AB Single-Piece 1Mb
Nonvolatile SRAM
Pin Description
BALLS
NAME
DESCRIPTION
BALLS
NAME
DESCRIPTION
A1, A2, A3, A4
GND
Ground
N17, N18, N19, N20
A5
Address Input 5
B1, B2, B3, B4
N.C.
No Connection
P17, P18, P19, P20
A4
Address Input 4
C1, C2, C3, C4
A15
Address Input 15
R17, R18, R19, R20
A3
Address Input 3
D1, D2, D3, D4
A16
Address Input 16
T17, T18, T19, T20
A2
Address Input 2
E1, E2, E3, E4
RST
Open-Drain Reset Output
U17, U18, U19, U20
A1
Address Input 1
F1, F2, F3, F4
VCC
Supply Voltage
V17, V18, V19, V20
A0
Address Input 0
G1, G2, G3, G4
WE
Write Enable Input
W17, W18, W19, W20
GND
H1, H2, H3, H4
OE
Output Enable Input
Y17, Y18, Y19, Y20
GND
Ground
J1, J2, J3, J4
CE
Chip Enable Input
A5, B5, C5, D5
N.C.
No Connection
Ground
K1, K2, K3, K4
DQ7
Data Input/Output 7
A6, B6, C6, D6
N.C.
No Connection
L1, L2, L3, L4
DQ6
Data Input/Output 6
A7, B7, C7, D7
N.C.
No Connection
M1, M2, M3, M4
DQ5
Data Input/Output 5
A8, B8, C8, D8
N.C.
No Connection
N1, N2, N3, N4
DQ4
Data Input/Output 4
A9, B9, C9, D9
N.C.
No Connection
P1, P2, P3, P4
DQ3
Data Input/Output 3
A10, B10, C10, D10
N.C.
No Connection
R1, R2, R3, R4
DQ2
Data Input/Output 2
A11, B11, C11, D11
N.C.
No Connection
T1, T2, T3, T4
DQ1
Data Input/Output 1
A12, B12, C12, D12
N.C.
No Connection
U1, U2, U3, U4
DQ0
Data Input/Output 0
A13, B13, C13, D13
N.C.
No Connection
V1, V2, V3, V4
GND
Ground
A14, B14, C14, D14
N.C.
No Connection
W1, W2, W3, W4
GND
Ground
A15, B15, C15, D15
N.C.
No Connection
Y1, Y2, Y3, Y4
GND
Ground
A16, B16, C16, D16
N.C.
No Connection
A17, A18, A19, A20
GND
Ground
U5, V5, W5, Y5
N.C.
No Connection
B17, B18, B19, B20
N.C.
No Connection
U6, V6, W6, Y6
N.C.
No Connection
C17, C18, C19, C20
N.C.
No Connection
U7, V7, W7, Y7
N.C.
No Connection
Address Input 14
U8, V8, W8, Y8
N.C.
No Connection
D17, D18, D19, D20
A14
E17, E18, E19, E20
A13
Address Input 13
U9, V9, W9, Y9
N.C.
No Connection
F17, F18, F19, F20
A12
Address Input 12
U10, V10, W10, Y10
N.C.
No Connection
G17, G18, G19, G20
A11
Address Input 11
U11, V11, W11, Y11
N.C.
No Connection
H17, H18, H19, H20
A10
Address Input 10
U12, V12, W12, Y12
N.C.
No Connection
J17, J18, J19, J20
A9
Address Input 9
U13, V13, W13, Y13
N.C.
No Connection
K17, K18, K19, K20
A8
Address Input 8
U14, V14, W14, Y14
N.C.
No Connection
L17, L18, L19, L20
A7
Address Input 7
U15, V15, W15, Y15
N.C.
No Connection
M17, M18, M19, M20
A6
Address Input 6
U16, V16, W16, Y16
N.C.
No Connection
8
_____________________________________________________________________
DS2045Y/AB Single-Piece 1Mb
Nonvolatile SRAM
CE
RST
DELAY TIMING
CIRCUITRY
VTP REF
CHARGER
UNINTERRUPTED
POWER SUPPLY
FOR THE SRAM
CURRENT-LIMITING
RESISTOR
VCC
VCC
CE
OE
WE
VSW REF
SRAM
DQ0–7
REDUNDANT LOGIC
ML
GND
CURRENT-LIMITING
RESISTOR
REDUNDANT
SERIES FET
BATTERY-CHARGING/SHORTING
PROTECTION CIRCUITRY (UL RECOGNIZED)
OE
DS2045
WE
A0–A16
Detailed Description
The DS2045 is a 1Mb (128k x 8 bits) fully static, NV
memory similar in function and organization to the
DS1245 NV SRAM, but containing a rechargeable ML
battery. The DS2045 NV SRAM constantly monitors VCC
for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically
switched on and write protection is unconditionally
enabled to prevent data corruption. There is no limit to
the number of write cycles that can be executed and no
additional support circuitry is required for microprocessor interfacing. This device can be used in place of
SRAM, EEPROM, or flash components.
The DS2045 assembly consists of a low-power SRAM,
an ML battery, and an NV controller with a battery
charger, integrated on a standard 256-ball, 27mm 2
BGA substrate. Unlike other surface-mount NV memory
modules that require the battery to be removable for
soldering, the internal ML battery can tolerate exposure
to convection reflow soldering temperatures allowing
this single-piece component to be handled with standard BGA assembly techniques.
Two versions of the DS2045 are available that provide
either a 5% (DS2045AB) or 10% (DS2045Y) powermonitoring trip point. The DS2045 also contains a
power-supply monitor output, RST, which can be used
as a CPU supervisor for a microprocessor.
_____________________________________________________________________
9
DS2045Y/AB
Functional Diagram
DS2045Y/AB
DS2045Y/AB Single-Piece 1Mb
Nonvolatile SRAM
Memory Operation Truth Table
WE
CE
OE
MODE
ICC
OUTPUTS
1
0
0
Read
Active
Active
1
0
1
Read
Active
High Impedance
0
0
X
Write
Active
High Impedance
X
1
X
Standby
Standby
High Impedance
X = Don’t care.
Read Mode
The DS2045 executes a read cycle whenever WE (write
enable) is inactive (high) and CE (chip enable) is active
(low). The unique address specified by the 17 address
inputs (A0 to A16) defines which of the 131,072 bytes of
data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (access time) after
the last address input signal is stable, providing that CE
and OE (output enable) access times are also satisfied.
If CE and OE access times are not satisfied, then data
access must be measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for
CE or tOE for OE rather than address access.
Write Mode
The DS2045 executes a write cycle whenever the CE
and WE signals are active (low) after address inputs
are stable. The later-occurring falling edge of CE or WE
will determine the start of the write cycle. The write
cycle is terminated by the earlier rising edge of CE or
WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (tWR) before another cycle can
be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention.
However, if the output drivers have been enabled (CE
and OE active) then WE will disable the outputs in tODW
from its falling edge.
(VSW), the power-switching circuit connects the lithium
energy source to the RAM to retain data. During powerup, when VCC rises above VSW, the power-switching
circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation
can resume after VCC exceeds V TP for a minimum
duration of tREC.
Battery Charging
When VCC is greater than VTP, an internal regulator
charges the battery. The UL-approved charger circuit
includes short-circuit protection and a temperature-stabilized voltage reference for on-demand charging of
the internal battery. Typical data-retention expectations
of 3 years per charge cycle are achievable.
A maximum of 96 hours of charging time is required to
fully charge a depleted battery.
System Power Monitoring
When the external VCC supply falls below the selected
out-of-tolerance trip point, the output RST is forced
active (low). Once active, the RST is held active until
the VCC supply has fallen below that of the internal battery. On power-up, the RST output is held active until
the external supply is greater than the selected trip
point and one reset timeout period (tRPU) has elapsed.
This is sufficiently longer than tREC to ensure that the
SRAM is ready for access by the microprocessor.
Data-Retention Mode
Freshness Seal and Shipping
The DS2045AB provides full functional capability for
VCC greater than 4.75V and write-protects at 4.5V. The
DS2045Y provides full functional capability for V CC
greater than 4.5V and write-protects at 4.25V. Data is
maintained in the absence of VCC without additional
support circuitry. The NV static RAM constantly monitors V CC. Should the supply voltage decay, the NV
SRAM automatically write-protects itself. All inputs
become “don’t care”, and all data outputs become high
impedance. As V CC falls below approximately 2.7V
The DS2045 is shipped from Dallas Semiconductor with
the lithium battery electrically disconnected, guaranteeing that no battery capacity has been consumed during
transit or storage. As shipped, the lithium battery is
~60% charged, and no preassembly charging operations should be attempted.
When VCC is first applied at a level greater than VTP,
the lithium battery is enabled for backup operation. A
96 hour initial battery charge time is recommended for
new system installations.
10
____________________________________________________________________
DS2045Y/AB Single-Piece 1Mb
Nonvolatile SRAM
PROFILE FEATURE
Average ramp-up rate
(TL to TP)
Preheat
- Temperature min (TSmin)
- Temperature max (TSmax)
- Time (min to max) (ts)
Sn-Pb EUTECTIC
ASSEMBLY
3°C/second max
100°C
150°C
60 to 120 seconds
Peak temperature (TP)
183°C
60 to 150 seconds
225 +0/-5°C
Time within 5°C of actual peak
temperature (TP)
10 to 30 seconds
Ramp-down rate
6°C/second max
Time 25°C to peak temperature
Power-Supply Decoupling
To achieve the best results when using the DS2045,
decouple the power supply with a 0.1µF capacitor. Use
a high-quality, ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, while ceramic
capacitors have adequately high frequency response
for decoupling applications.
Using the Open-Drain RST Output
The RST output is open drain, and therefore requires a
pullup resistor to realize a high logic output level. Pullup
resistor values between 1kΩ and 10kΩ are typical.
TSmax to TL
- Ramp-up rate
Time maintained above:
- Temperature (TL)
- Time (tL)
Applications Information
6 minutes max
Note: All temperatures refer to top side of the package, measured on the package body surface.
Battery Charging/Lifetime
The DS2045 charges an ML battery to maximum
capacity in approximately 96 hours of operation when
VCC is greater than VTP. Once the battery is charged,
its lifetime depends primarily on the VCC duty cycle.
The DS2045 can maintain data from a single, initial
charge for up to 3 years. Once recharged, this deepdischarge cycle can be repeated up to 20 times, producing a worst-case service life of 60 years. More
typical duty cycles are of shorter duration, enabling the
DS2045 to be charged hundreds of times, therefore
extending the service life well beyond 60 years.
Recommended Cleaning Procedures
The DS2045 may be cleaned using aqueous-based
cleaning solutions. No special precautions are needed
when cleaning boards containing a DS2045 module.
Removal of the topside label violates the environmental integrity of the package and voids the warranty of
the product.
____________________________________________________________________
11
DS2045Y/AB
Recommended Reflow Temperature Profile
Pin Configuration
TOP VIEW
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
9
1
8
2
0
D
A16
A14
D
E
RST
A13
E
F
VCC
A12
F
G
WE
A11
G
H
OE
A10
H
J
CE
A9
J
K
DQ7
A8
K
L
DQ6
A7
L
M
DQ5
A6
M
N
DQ4
A5
N
P
DQ3
A4
P
R
DQ2
A3
R
T
DQ1
A2
T
U
DQ0
A1
U
V
GND
A0
V
W
GND
GND
W
Y
GND
GND
Y
1
2
N.C.
C
N.C.
N.C.
N.C.
A15
N.C.
C
N.C.
B
N.C.
N.C.
N.C.
N.C.
N.C.
B
N.C.
A
N.C.
GND
N.C.
GND
N.C.
A
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DS2045
N.C.
DS2045Y/AB
DS2045Y/AB Single-Piece 1Mb
Nonvolatile SRAM
1
6
1
7
1
8
1
9
2
0
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Dallas Semiconductor Corporation.
is a registered trademark of Maxim Integrated Products.
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