MAXIM DS2430AP+TR

19-5236; 4/10
S
DS2430A
256-Bit 1-Wire EEPROM
PIN ASSIGNMENT
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ORDERING INFORMATION
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DS2430A+
TO-92 Package
DS2430AP+
6-pin TSOC Package
DS2430A+T&R
TO-92 Package, Tape & Reel
DS2430AP+T&R TSOC Package, Tape & Reel
+Denotes a lead(Pb)-free/RoHS-compliant
package.
Contact factory for availability of the UCSP
version.
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SIDE VIEW
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1 2 3
BOTTOM VIEW
See Mech.
Drawings Section
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TOP VIEW
3.7mm x 4.0mm x 1.5mm
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DALLAS
DS2430A
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TSOC PACKAGE
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TO-92
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256-bit Electrically Erasable Programmable
Read Only Memory (EEPROM) plus 64-bit
one-time programmable application register
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-bit
serial number + 8-bit CRC tester) assures
absolute identity because no two parts are alike
Built-in multidrop controller ensures
compatibility with other MicroLAN products
EEPROM organized as one page of 32 bytes
for random access
Reduces control, address, data, and power to a
single data pin
Directly connects to a single port pin of a
microprocessor and communicates at up to
15.3kbits per second
8-bit family code specifies DS2430A
communication requirements to reader
Presence detector acknowledges when reader
first applies voltage
Low cost TO-92 or 6-pin TSOC and UCSP
surface mount package
Reads and writes over a wide voltage range of
2.8V to 5.25V from -40°C to +85°C
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FEATURES
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www.maxim-ic.com
NOTE: The leads of TO-92 packages on tapeand-reel are formed to approximately 100 mil
(2.54 mm) spacing. For details see Package
Information.
PIN DESCRIPTION
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
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TO-92
Ground
Data
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TSOC
Ground
Data
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DS2430A
DESCRIPTION
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The DS2430A 256-bit 1-Wire EEPROM identifies and stores relevant information about the product to
which it is associated. This lot or product specific information can be accessed with minimal interface, for
example a single port pin of a microcontroller. The DS2430A consists of a factory-lasered registration
number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (14h) plus
256 bits of user-programmable EEPROM and a 64-bit one-time programmable application register. The
power to read and write the DS2430A is derived entirely from the 1-Wire® communication line. Data is
transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return.
The 48-bit serial number that is factory-lasered into each DS2430A provides a guaranteed unique identity
that allows for absolute traceability. The TO-92 and TSOC packages provide a compact enclosure that
allows standard assembly equipment to handle the device easily for attachment to printed circuit boards
or wiring. Typical applications include storage of calibration constants, board identification, and product
revision status.
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OVERVIEW
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The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS2430A. The DS2430A has four main data components: 1) 64-bit lasered ROM, 2) 256-bit
EEPROM data memory with scratchpad, 3) 64-bit one-time programmable application register with
scratchpad and 4) 8-bit status memory. The hierarchical structure of the 1-Wire protocol is shown in
Figure 2. The bus master must first provide one of the four ROM Function Commands: 1) Read ROM, 2)
Match ROM, 3) Search ROM, 4) Skip ROM. The protocol required for these ROM Function Commands
is described in Figure 8. After a ROM Function Command is successfully executed, the memory
functions become accessible and the master can provide any one of the four memory function commands.
The protocol for these memory function commands is described in Figure 6. All data is read and written
least significant bit first.
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64-BIT LASERED ROM
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Each DS2430A contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code
(14h). The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (Figure
3). The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR
gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas
1-Wire Cyclic Redundancy Check is available in Application Note 27. The shift register bits are
initialized to 0. Then starting with the least significant bit of the family code, one bit at a time is shifted
in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th
bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits
of CRC should return the shift register to all 0s.
1-Wire and iButton are registered trademarks of Maxim Integrated Products, Inc.
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DS2430A
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DS2430A BLOCK DIAGRAM Figure 1
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DS2430A
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HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
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64-BIT LASERED ROM Figure 3
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MSB
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8-Bit CRC Code
48-Bit Serial Number
LSB MSB
8-Bit Family Code (14H)
LSB MSB
LSB
Polynomial = X8 + X5 + X4 + 1
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1-WIRE CRC GENERATOR Figure 4
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DS2430A
MEMORY
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The memory of the DS2430A consists of three separate sections, called data memory, application
register, and status register (Figure 5). The data memory and the application register each have its own
intermediate storage area called scratchpad that acts as a buffer when writing to the device. The data
memory can be read and written as often as desired. The application register, however, is one-time
programmable only. Once the application register is programmed, it is automatically write protected. The
status register indicates whether the application register is already locked or whether it is still available
for storing data. As long as the application register is unprogrammed, the status register reads FFh.
Copying data from the register scratchpad to the application register clears the 2 least significant bits of
the status register, yielding an FCh the next time one reads the status register.
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DS2430A MEMORY MAP Figure 5
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MEMORY FUNCTION COMMANDS
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The Memory Function Flow Chart (Figure 6) describes the protocols necessary for accessing the different
memory sections of the DS2430A. An example is shown later in this document.
WRITE SCRATCHPAD [0Fh]
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After issuing the Write Scratchpad command, the master must first provide a 1-byte address, followed by
the data to be written to the scratchpad for the data memory. The DS2430A automatically increments the
address after every byte it receives. After having received a data byte for address 1Fh, the address counter
wraps around to 00h for the next byte and writing continues until the master sends a Reset Pulse.
READ SCRATCHPAD [AAh]
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This command is used to verify data previously written to the scratchpad before it is copied into the final
storage EEPROM memory. After issuing the Read Scratchpad command, the master must provide the 1byte starting address from where data is to be read. The DS2430A automatically increments the address
after every byte read by the master. After the data at address 1Fh has been read, the address counter wraps
around to 00h for the next byte and reading continues until the master sends a Reset Pulse.
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DS2430A
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MEMORY FUNCTION FLOW CHART Figure 6
COPY SCRATCHPAD [55h]
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After the data stored in the scratchpad has been verified the master may send the Copy Scratchpad
command followed by a validation key of A5h to transfer data from the scratchpad to the EEPROM
memory. This command always copies the data of the entire scratchpad. Therefore, if one desires to
change only a few bytes of the EEPROM data, the scratchpad should contain a copy of the latest
EEPROM data before the Write Scratchpad and Copy Scratchpad commands are issued. After this
command and the validation key are issued, the data line must be held above VPUPmin for at least tPROG.
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READ MEMORY [F0h]
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The Read Memory command is used to read a portion or all of the EEPROM data memory and to copy
the entire data memory into the scratchpad to prepare for changing a few bytes. To copy data from the
data memory to the scratchpad and to read it, the master must issue the read memory command followed
by the 1-byte starting address of the data to be read from the scratchpad. The DS2430A automatically
increments the address after every byte read by the master. After the data of address 1Fh has been read,
the address counter wraps around to 00h for the next byte and reading continues until the master sends a
Reset Pulse. If one intends to copy the entire data memory to the scratchpad without reading data, a
starting address is not required; the master may send a Reset Pulse immediately following the command
code.
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DS2430A
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MEMORY FUNCTION FLOW CHART Figure 6 (cont’d)
WRITE APPLICATION REGISTER [99h]
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This command is essentially the same as the Write Scratchpad command, but it addresses the 64-bit
register scratchpad. After issuing the command code, the master must provide a 1-byte address, followed
by the data to be written. The DS2430A automatically increments the address after every byte it receives.
After receiving the data byte for address 07h, the address counter wraps around to 00h for the next byte
and writing continues until the master sends a Reset Pulse. The Write Application Register command can
be used as long as the application register has not yet been locked. If issued for a device with the
application register locked, the data written to the register scratchpad will be lost.
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READ STATUS REGISTER [66h]
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The status register is a means for the master to find out whether the application register has been
programmed and locked. After issuing the read status register command, the master must provide the
validation key 00h before receiving status information. The two least significant bits of the 8-bit status
register are 0 if the application register was programmed and locked; all other bits always read 1. The
master may finish the read status command by sending a Reset Pulse at any time.
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DS2430A
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MEMORY FUNCTION FLOW CHART Figure 6 (cont’d)
READ APPLICATION REGISTER [C3h]
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This command is used to read the application register or the register scratchpad. As long as the
application register is not yet locked, the DS2430A transmits data from the register scratchpad. After the
application register is locked the DS2430A transmits data from the application register, making the
register scratchpad inaccessible for reading. The contents of the status register indicate where the data
received with this command came from. After issuing the Read Application Register command, the
master must provide the 1-byte starting address from where data is to be read. The DS2430A
automatically increments the address after every byte read by the master. After the data at address 07h
has been read, the address counter wraps around to 00h for the next byte and reading continues until the
master sends a Reset Pulse.
COPY & LOCK APPLICATION REGISTER [5Ah]
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After the data stored in the register scratchpad has been verified the master may send the Copy & Lock
Application Register command followed by a validation key of A5h to transfer the contents of the entire
register scratchpad to the application register and to simultaneously write-protect it. The master may
cancel this command by sending a Reset Pulse instead of the validation key. After the validation key is
transmitted, the data line must be held above VPUPmin for at least tPROG. Once tPROG has expired, the
application register will contain the data of the register scratchpad. Further write accesses to the
application register will be denied. The Copy & Lock Application Register command can only be
executed once.
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DS2430A
1-WIRE BUS SYSTEM
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The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances, the
DS2430A is a slave device. The bus master is typically a microcontroller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal type and timing). The 1-Wire protocol defines bus transactions in terms of the bus state
during specified time slots that are initiated on the falling edge of sync pulses from the bus master.
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Hardware Configuration
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HARDWARE CONFIGURATION Figure 7
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The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain connection or three-state outputs. The 1-Wire port of the DS2430A is open drain with an internal
circuit equivalent to that shown in Figure 7. A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS2430A communicates at regular 1-Wire speed, 15.3kbits per second, and requires
a pullup resistor as shown in Figure 7. The idle state for the 1-Wire bus is high. If for any reason a
transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If
this does not occur and the bus is left low for more than 120µs, one or more of the devices on the bus may
be reset.
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RPU
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RPU
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Note: Depending on the 1-Wire communication speed and the bus characteristics, the optimal pullup
resistor value will be in the 0.3k to 2.2k range. To write to a single device, a RPUPmax resistor and
VPUP of at least 4.0V is sufficient. For writing multiple DS2430As simultaneously or operation at low
VPUP, the resistor should be bypassed by a low-impedance pullup to VPUP while the device copies the
scratchpad to EEPROM.
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DS2430A
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ROM FUNCTIONS FLOW CHART Figure 8
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DS2430A
Transaction Sequence
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ROM Function Command
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Memory Function Command
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Transaction/Data
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Initialization
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The sequence for accessing the DS2430A via the 1-Wire port is as follows:
INITIALIZATION
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All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a Reset Pulse transmitted by the bus master followed by a Presence Pulse(s) transmitted by the
slave(s).
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The Presence Pulse lets the bus master know that the DS2430A is on the bus and is ready to operate. For
more details, see the 1-Wire Signaling section.
ROM FUNCTION COMMANDS
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Once the bus master has detected a presence pulse, it can issue one of the four ROM function commands.
All ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in
Figure 8):
Read ROM [33h]
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Match ROM [55h]
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This command allows the bus master to read the DS2430A’s 8-bit family code, 48-bit serial number, and
8-bit CRC. This command can be used only if there is a single DS2430A on the bus. If more than one
slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time
(open drain produces a wired-AND result). The resultant family code and 48-bit serial number usually
result in a mismatch of the CRC.
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The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific DS2430A on a multidrop bus. Only the DS2430A that exactly matches the 64-bit ROM sequence
will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM
sequence will wait for a Reset Pulse. This command can be used with a single or multiple devices on the
bus.
Skip ROM [CCh]
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This command can save time in a single-drop bus system by allowing the bus master to access the
memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus
and a read command is issued following the Skip ROM command, data collision will occur on the bus as
multiple slaves transmit simultaneously (open drain pulldowns produces a wired-AND result).
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Search ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a process
of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The Search ROM process
is the repetition of a simple, three-step routine: read a bit, read the complement of the bit, then write the
desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM.
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DS2430A
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Application Note
187 for a comprehensive discussion of a search ROM, including an actual example.
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1-Wire Signaling
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The DS2430A requires strict protocols to insure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write-0, Write-1 and ReadData. All these signals (except Presence Pulse) are initiated by the bus master.
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To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL.
To get from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The time it takes
for the voltage to make this rise is seen in Figure 9 as , and its duration depends on the pullup resistor
(RPUP) used and the capacitance of the 1-Wire network attached. The voltage VILMAX is relevant for the
DS2430A when determining a logical level, not triggering any events.
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Figure 9 shows the initialization sequence required to begin any communication with the DS2430A. A
Reset Pulse followed by a Presence Pulse indicates the DS2430A is ready to receive data, given the
correct ROM and memory function command. If the bus master uses slew-rate control on the falling
edge, it must pull down the line for tRSTL + tF to compensate for the edge.
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After the bus master has released the line it goes into Receive mode. Now the 1-Wire bus is pulled to
VPUP through the pullup resistor. When the threshold VTH is crossed, the DS2340A waits for tPDH and then
transmits a Presence Pulse by pulling the line low for tPDL. To detect a Presence Pulse, the master must
test the logical state of the 1-Wire line at tMSP. The tRSTH window must be at least the sum of tPDHMAX,
tPDLMAX, and tRECMIN. Immediately after tRSTH is expired, the DS2430A is ready for data communication.
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INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 9
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MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE”
VPUP
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tF
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VTL
VILMAX
0V
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VIHMASTER
VTH
tMSP

tPDH
MASTER
tPDL
tRSTH
tREC
DS2430A
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RESISTOR
tRSTL
Read/Write Time Slots
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Data communication with the DS2430A takes place in time slots, which carry a single bit each. Write
time slots transport data from bus master to slave. Read time slots transfer data from slave to master.
Figure 10 illustrates the definitions of the write and read time slots.
All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line
falls below the threshold VTL, the DS2430A starts its internal timing generator that determines when the
data line is sampled during a write time slot and how long data is valid during a read time slot.
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DS2430A
Master-to-Slave
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For a Write-1 time slot, the voltage on the data line must have crossed the VTH threshold before the
Write-1 low time tW1LMAX is expired. For a Write-0 time slot, the voltage on the data line must stay below
the VTH threshold until the Write-0 low time tW0LMIN is expired. For the most reliable communication, the
voltage on the data line should not exceed VILMAX during the entire tW0L or tW1L window. After the VTH
threshold has been crossed, the DS2430A needs a recovery time tREC before it is ready for the next time
slot.
READ/WRITE TIMING DIAGRAM Figure 10
Write-1 Time Slot
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tW1L
VPUP
MASTER
Write-0 Time Slot
tW0L
VPUP
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tF
tSLOT
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VTL
VILMAX
0V
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VIHMASTER
VTH
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RESISTOR
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tSLOT
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
tF
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VTL
VILMAX
0V
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VIHMASTER
VTH
tREC
MASTER
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RESISTOR

tMSR
tRL
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VPUP
VIHMASTER
VTH
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Read-data Time Slot
Master
Sampling
Window
VTL
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VILMAX
0V
tF

RESISTOR
tSLOT
MASTER
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tREC
DS2430A
DS2430A
Slave-to-Master
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A Read-data time slot begins like a Write-1 time slot. The voltage on the data line must remain below
VTL until the read low time tRL is expired. During the tRL window, when responding with a 0, the
DS2430A starts pulling the data line low; its internal timing generator determines when this pulldown
ends and the voltage starts rising again. When responding with a 1, the DS2430A does not hold the data
line low at all, and the voltage starts rising as soon as tRL is over.
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The sum of tRL +  (rise time) on one side and the internal timing generator of the DS2430A on the other
side define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a read
from the data line. For the most reliable communication, tRL should be as short as permissible, and the
master should read close to but no later than tMSRMAX. After reading from the data line, the master must
wait until tSLOT is expired. This guarantees sufficient recovery time tREC for the DS2430A to get ready for
the next time slot. Note that tREC specified herein applies only to a single DS2430A attached to a 1-Wire
line. For multidevice configurations, tREC must be extended to accommodate the additional 1-Wire device
input capacitance. Alternatively, an interface that performs active pullup during the 1-Wire recovery time
such as the DS2482-x00 or DS2480B 1-Wire line drivers can be used.
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IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS)
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In a 1-Wire environment, line termination is possible only during transients controlled by the bus master
(1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the
physical size and topology of the network, reflections from end points and branch points can add up, or
cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire
communication line. Noise coupled onto the 1-Wire line from external sources can also result in signal
glitching. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization
with the master and, consequently, result in a Search ROM command coming to a dead end or cause a
device-specific function command to abort. For better performance in network applications, the
DS2430A uses a new 1-Wire front end, which makes it less sensitive to noise.
The 1-Wire front end of the DS2430A differs from traditional slave devices in three characteristics.
1) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a
time slot. This reduces the sensitivity to high-frequency noise.
2) There is a hysteresis at the low-to-high switching threshold VTH. If a negative glitch crosses VTH but
does not go below VTH - VHY, it will not be recognized (Figure 11, Case A)..
3) There is a time window specified by the rising edge hold-off time tREH during which glitches are
ignored, even if they extend below VTH - VHY threshold (Figure 11, Case B, tGL < tREH). Deep voltage
droops or glitches that appear late after crossing the VTH threshold and extend beyond the tREH
window cannot be filtered out and are taken as the beginning of a new time slot (Figure 11, Case C,
tGL  tREH).
Devices that have the parameters VHY, and tREH specified in their electrical characteristics use the
improved 1-Wire front end.
NOISE SUPPRESSION SCHEME Figure 11
tREH
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VPUP
tREH
VTH
VHY
0V
Case A
Case B
tGL
Case C
tGL
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DS2430A
MEMORY FUNCTION EXAMPLE
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COMMENTS
Reset pulse (480µs to 960µs)
Presence pulse
Issue “Skip ROM” command
Issue “Write Scratchpad” command
Start address = 06h
Write 2 bytes of data to scratchpad
Reset pulse
Presence pulse
Issue “Skip ROM” command
Issue “Read Scratchpad” command
Start address = 06h
Read scratchpad data and verify
Reset pulse
Presence pulse
Issue “Skip ROM” command
Issue “Copy Scratchpad” command
Validation key
Data line must be above VPUPmin for tPROG.
Reset pulse
Presence pulse
Issue “Skip ROM” command
Issue “Read Memory” command
Start address = 00h
Read EEPROM data page
Reset pulse
Presence pulse
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DATA (LSB FIRST)
Reset
Presence
CCh
0Fh
06h
<2 Data Bytes>
Reset
Presence
CCh
AAh
06h
<2 Data Bytes>
Reset
Presence
CCh
55h
A5h
<Data Line High>
Reset
Presence
CCh
F0h
00h
<32 Bytes>
Reset
Presence
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MASTER MODE
TX
RX
TX
TX
TX
TX
TX
RX
TX
TX
TX
RX
TX
RX
TX
TX
TX
TX
TX
RX
TX
TX
TX
RX
TX
RX
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Example: Write 2 data bytes to data memory locations 0006h and 0007h. Read entire data memory.
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DS2430A
-0.5V to +6.0V
20mA
-40°C to +85°C
+150°C
-55°C to +125°C
+300°C
+260°C (TSOC)
+250°C (TO-92)
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Voltage on DATA to Ground
DATA Sink Current
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Lead Temperature (soldering 10s)
Soldering Temperature (reflow)
S
ABSOLUTE MAXIMUM RATINGS
D
E
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may
affect device reliability.
E
CONDITIONS
(Notes 2)
(Notes 2, 3)
(Notes 4, 5)
DATA pin at VPUP
VTL
(Notes 5, 6, 7)
VIL
(Notes 2, 8)
VTH
(Notes 5, 6, 9)
1.0
VHY
VOL
tREC
(Notes 5, 6, 10)
At 4mA (Note 11)
RPUP = 2.2k (Notes 2,12)
(Notes 5, 13)
0.21
tSLOT
FO
D
E
N
D
tREH
2.8
0.3
R
VPUP
RPUP
CIO
IL
(Notes 2, 14)
0.05
0.46
5.25
2.2
1000
15
VPUP 1.8V
0.5
VPUP 1.1V
1.70
0.4
V
k
pF
µA
5.0
µs
5
0.5
65
M
E
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching
Threshold
Input Low Voltage
Low-to-High Switching
Threshold
Switching Hysteresis
Output Low Voltage
Recovery Time
Rising-Edge Hold-off
Time
Timeslot Duration
(TA = -40°C to +85°C; see Note 1.)
MIN
TYP MAX UNITS
N
PARAMETER
SYMBOL
DATA PIN GENERAL DATA
W
ELECTRICAL CHARACTERISTICS
V
V
V
V
V
µs
µs
DATA PIN, 1-WIRE RESET, PRESENCE DETECT CYCLE
tRSTL
(Note 2)
480
960
µs
tPDH
15
60
µs
tPDL
60
240
µs
60
75
µs
(Notes 2, 16)
(Notes 2, 16)
60
1
120 - 
15 - 
µs
µs
(Notes 2, 17)
(Notes 2, 17)
1
tRL + 
15 - 
15
µs
µs
E
C
O
M
Reset Low Time
Presence Detect High
Time
Presence Detect Low
Time
Presence Detect Sample
Time
tMSP
(Notes 2, 15)
DATA PIN, 1-Wire WRITE
R
Write-0 Low Time
Write-1 Low Time
tW0L
tW1L
T
DATA PIN, 1-Wire READ
N
O
Read Low Time
Read Sample Time
tRL
tMSR
16 of 19
DS2430A
Programming Current
Programming Time
Write/Erase Cycles (Endurance) (Notes 20, 21)
Data Retention (Notes 22,
23, 24)
IPROG
tPROG
NCY
MIN
TYP
MAX UNITS
(Notes 5, 18)
(Note 19)
At 25°C
At 85°C (worst case)
0.5
10
200k
50k

At 85°C (worst case)
40
years
Specifications at TA = -40°C are guaranteed by design only and not production-tested.
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire
recovery times. The specified value here applies to systems with only one device and with the minimum tREC. For
more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may
be required. If longer tREC is used, higher RPUP values may be able to be tolerated.
Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 2.2k resistor is used
to pull up the data line, 2.5µs after VPUP has been applied the parasite capacitance will not affect normal
communications.
Guaranteed by design, characterization and/or simulation only. Not production tested.
VTL, VTH, and VHY are a function of the internal supply voltage which is itself a function of VPUP, RPUP, 1-Wire
timing, and capacitive loading on DATA. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading
all lead to lower values of VTL, VTH, and VHY.
Voltage below which, during a falling edge on DATA, a logic 0 is detected.
The voltage on DATA needs to be less or equal to VIL(MAX) at all times the master is driving DATA to a logic-0
level.
Voltage above which, during a rising edge on DATA, a logic 1 is detected.
After VTH is crossed during a rising edge on DATA, the voltage on DATA has to drop by at least VHY to be
detected as logic '0'.
The I-V characteristic is linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising
edge.
Defines maximum possible bit rate. Equal to 1/(tW0L(min) + tREC(min)).
Interval after tRSTL during which a bus master is guaranteed to sample a logic-0 on DATA if there is a DS2430A
present. Minimum limit is tPDH(max); maximum limit is tPDH(min) + tPDL(min).
 in Figure 10 represents the time required for the pullup circuitry to pull the voltage on DATA up from VIL to
VTH. The actual maximum duration for the master to pull the line low is tW1Lmax + tF and tW0Lmax + tF respectively.
 in Figure 10 represents the time required for the pullup circuitry to pull the voltage on DATA up from VIL to the
input high threshold of the bus master. The actual maximum duration for the master to pull the line low is
tRLmax + tF.
Current drawn from DATA during the EEPROM programming interval. The pullup circuit on DATA during the
programming interval should be such that the voltage drop been VPUP and DATA is less than 0.25V. Current
increases with increased VPUP.
Interval begins tREHmax after the trailing rising edge on DATA for the last timeslot of the validation key for a valid
copy sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the
current drawn by the device has returned from IPROG to IL.
Write-cycle endurance is degraded as TA increases.
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as TA increases.
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production
test to data sheet limit at operating temperature range is established by reliability testing.
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at
elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40
years at +85°C.
D
E
Note 1:
Note 2:
Note 3:
W
Note 4:
N
E
Note 5:
Note 6:
Note 17:
Note 18:
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E
E
C
Note 19:
N
D
Note 16:
M
E
Note 14:
Note 15:
M
Note 11:
Note 12:
Note 13:
O
Note 9:
Note 10:
FO
R
Note 7:
Note 8:
T
R
Note 20:
Note 21:
Note 22:
Note 23:
Note 24:
N
O
mA
ms
S
IG
tDR
CONDITIONS
S
SYMBOL
N
PARAMETER
EEPROM
17 of 19
DS2430A
Package Information
DOCUMENT NO.
3 TO-92 (Bulk)
Q3+1
21-0248
3 TO-92 (T&R)
Q3+4
21-0250
6 TSOC
D6+1
21-0382
E
D
W
E
N
R
FO
D
E
N
D
M
E
M
O
E
C
R
T
N
O
18 of 19
N
PACKAGE CODE
S
IG
PACKAGE TYPE
S
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-“ in the package code
indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of
RoHS status.
DS2430A
REVISION HISTORY
1/20/99
5/20/99
Deleted duplicate tPDL and contradicting tPROG spec from EC table
Template conversion, style changes (capitalization of command names, “Writeone” to “Write-1”, “Write-zero” to “Write-0”)
Part number corrections, style corrections, note below figure 7 revised explaining the appropriate RPUP range, corrections in the Memory Functions Example
(removed Read Memory section at the beginning), changed solder spec from
260°C to JEDEC reference, added notes 11, 12, 13 to EC table, changed
tRSTLmax from 5000µs to 960µs, revised text of EC table note 8.
NRFND watermark added
Lead free part numbers added; added flip chip graphic with bump electrical
assignment, orientation mark and marking; Added flip chip 56-level drawing
number, changed "Chip Scale" name to "Flip Chip"; replaced references to the
Book of iButton Standards with the corresponding application notes.
Note on formed leads for TO-92 TRL and URL to 56-G0006-003 added, ILmin
and ILmax spec values added to EC table. Data retention added to EC table.
Ordering information for standard and flip chip versions deleted, pin assignment
for flip chip version deleted, data rate changed from 16.3kbps to 15.3 kbps.
Style corrections and minor text updates for clarification.
New 1-Wire front end, improved EEPROM and related EC table with notes.
Package information section added
E
1/16/07
D
11/1/05
FO
R
2/2/02
N
D
8/8/07
1
15
All
Various
All
Various
1, 15
1
Various
12-14, 16-17
18
N
O
T
R
E
C
O
M
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E
4/10
19 of 19
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas
Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and
specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim
Products
19 ofIntegrated
19
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc.
S
N
S
IG
Various
N
10/21/99
Various
E
12/8/98
Various
D
3/26/97
Initial release
Changed “C-lead” package to “TSOC” package. Deleted VIHmax specification
value. Note “Under certain low voltage conditions VILMAX may have to be
reduced to as much as 0.5V to always guarantee a presence pulse.” added to
VIL specification, changed VCC to VPUP in Note 6.
Changed “Touch Memory” to “iButton”.
Programming time changed from 100ms to 10ms, change VDD to VPUP, revised
note below Figure 7, programming current changed from 600µA to 500µA, QOP
removed from EC table, deleted from Note 5 “and will remain valid for 14µs
minimum (15µs total from falling edge on 1-wire bus).” Endurance added to EC
table with note “The Copy Scratchpad takes 10 ms maximum, during which the
voltage on the 1-Wire bus must not fall below 2.8V.”
Chip scale package added to ordering information
W
8/26/96
PAGES
CHANGED
—
DESCRIPTION
E
REVISION
DATE
4/3/95