NSC DS25CP102Q Automotive 3.125 gbps 2x2 lvds crosspoint switch with transmit pre-emphasis and receive equalization Datasheet

DS25CP102Q
Automotive 3.125 Gbps 2X2 LVDS Crosspoint Switch with
Transmit Pre-Emphasis and Receive Equalization
General Description
Features
The DS25CP102Q is a 3.125 Gbps 2x2 LVDS crosspoint
switch optimized for high-speed signal routing and switching
over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking
architecture allows connections of any input to any output or
outputs.
The DS25CP102Q features two levels (Off and On) of transmit pre-emphasis (PE) and two levels (Off and On) of receive
equalization (EQ).
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower device insertion and
return losses, reduce component count and further minimize
board space.
■ AECQ-100 Grade 3
■ DC - 3.125 Gbps low jitter, low skew, low power operation
■ Pin configurable, fully differential, non-blocking
architecture
■ Pin selectable transmit pre-emphasis and receive
equalization eliminate data dependant jitter
■ Wide Input Common Mode Voltage Range allows DCcoupled interface to CML and LVPECL drivers
■ On-chip 100Ω input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space
■ 8 kV ESD on LVDS I/O pins protects adjoining
components
■ Small 4 mm x 4 mm LLP-16 space saving package
Applications
■
■
■
■
Automotive display applications
Clock and data buffering and muxing
OC-48 / STM-16
SD/HD/3GHD SDI Routers
Typical Application
30063370
© 2008 National Semiconductor Corporation
300633
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DS25CP102Q Automotive 3.125 Gbps 2X2 LVDS Crosspoint Switch with Signal Conditioning
July 18, 2008
DS25CP102Q
Ordering Code
NSID
Function
DS25CP102QSQ
Crosspoint Switch
Block Diagram
Available Equalization
Levels
Available Pre-Emphasis
Levels
Off / On
Off / On
Connection Diagram
30063301
30063302
Pin Descriptions
Pin Name
Pin Number I/O, Type
Pin Description
IN0+, IN0- ,
IN1+, IN1-
1, 2,
3, 4
I, LVDS
Inverting and non-inverting high speed LVDS input pins.
OUT0+, OUT0-,
OUT1+, OUT1-
12, 11,
10, 9
O, LVDS
Inverting and non-inverting high speed LVDS output pins.
SEL0, SEL1
7, 8
I, LVCMOS
Switch configuration pins. There is a 20k pulldown resistor on this pin.
EN0, EN1
14, 13
I, LVCMOS
Output enable pins. There is a 20k pulldown resistor on this pin.
PE
15
I, LVCMOS
Transmit Pre-Emphasis select pin. There is a 20k pulldown resistor on this pin.
EQ
6
I, LVCMOS
Receive Equalizaton select pin. There is a 20k pulldown resistor on this pin.
VDD
16
Power
Power supply pin.
GND
5, DAP
Power
Ground pin and Device Attach Pad (DAP) ground.
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2
θJA
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+41.8°C/W
θJC
ESD Susceptibility
HBM (Note 1)
Supply Voltage
−0.3V to +4V
LVCMOS Input Voltage
−0.3V to (VCC + 0.3V)
LVDS Input Voltage
−0.3V to +4V
LVDS Differential Input Voltage
0V to 1.0V
LVDS Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage
0V to 1.0V
LVDS Output Short Circuit Current
5 ms
Duration
Junction Temperature
+105°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
SQA Package
1.91W
Derate SQA Package
23.9 mW/°C above +25°C
+6.9°C/W
≥8 kV
≥250V
≥1250V
MM (Note 2)
CDM (Note 3)
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Recommended Operating
Conditions
Supply Voltage (VCC)
Receiver Differential Input
Voltage (VID)
Operating Free Air
Temperature (TA)
Min
3.0
0
Typ
3.3
Max
3.6
1
Units
V
V
−40
+25
+85
°C
DC Electrical Characteristics
(Notes 5, 6, 7)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VCC
V
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
VIN = 3.6V
VCC = 3.6V
175
250
μA
IIL
Low Level Input Current
VIN = GND
VCC = 3.6V
0
±10
μA
VCL
Input Clamp Voltage
ICL = −18 mA, VCC = 0V
−0.9
−1.5
V
1
V
+100
mV
40
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
0
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
VCMR
Common Mode Voltage Range
VID = 100 mV
IIN
Input Current
VIN = +3.6V or 0V
VCC = 3.6V or 0V
CIN
Input Capacitance
Any LVDS Input Pin to GND
1.7
pF
RIN
Input Termination Resistor
Between IN+ and IN-
100
Ω
VCM = +0.05V or VCC-0.05V
0
−100
3
0
0.05
±1
mV
VCC 0.05
V
±10
μA
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DS25CP102Q
Package Thermal Resistance
Absolute Maximum Ratings (Note 4)
DS25CP102Q
Symbol
Parameter
Conditions
Min
Typ
Max
Units
250
350
450
mV
35
mV
1.375
V
35
mV
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
RL = 100Ω
IOS
Output Short Circuit Current (Note 8)
OUT to GND
-35
-55
mA
OUT to VCC
7
55
mA
RL = 100Ω
-35
1.05
1.2
-35
COUT
Output Capacitance
Any LVDS Output Pin to GND
1.2
pF
ROUT
Output Termination Resistor
Between OUT+ and OUT-
100
Ω
SUPPLY CURRENT
ICC
Supply Current
PE = OFF, EQ = OFF
77
90
mA
ICCZ
Supply Current with Outputs Disabled
EN0 = EN1 = 0
23
29
mA
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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4
(Note 11)
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
365
500
ps
345
500
ps
LVDS OUTPUT AC SPECIFICATIONS
tPLHD
Differential Propagation Delay Low to
High
tPHLD
Differential Propagation Delay High to
Low
tSKD1
Pulse Skew |tPLHD − tPHLD| (Note 12)
20
55
ps
tSKD2
Channel to Channel Skew (Note 13)
12
25
ps
tSKD3
Part to Part Skew , (Note 14)
50
150
ps
tLHT
Rise Time
65
120
ps
tHLT
Fall Time
65
120
ps
tON
Output Enable Time
ENn = LH to output active
7
20
μs
tOFF
Output Disable Time
ENn = HL to output inactive
5
12
ns
tSEL
Select Time
SELn LH or HL to output
3.5
12
ns
RL = 100Ω
RL = 100Ω
JITTER PERFORMANCE WITH EQ = Off, PE = Off (Figure 5)
tRJ1
tRJ2
tDJ1
tDJ2
tTJ1
tTJ2
Random Jitter (RMS Value)
No Test Channels
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
Deterministic Jitter (Peak to Peak)
No Test Channels
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
6
22
ps
3.125 Gbps
6
22
ps
Total Jitter (Peak to Peak)
No Test Channels
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.03
0.08
UIP-P
3.125 Gbps
0.05
0.11
UIP-P
JITTER PERFORMANCE WITH EQ = Off, PE = On (Figure 6 Figure 9)
tRJ1B
tRJ2B
tDJ1B
tDJ2B
tTJ1B
tTJ2B
Random Jitter (RMS Value)
Test Channel B
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
Deterministic Jitter (Peak to Peak)
Test Channel B
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
3
12
ps
3.125 Gbps
3
12
ps
Total Jitter (Peak to Peak)
Test Channel B
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.03
0.06
UIP-P
3.125 Gbps
0.04
0.09
UIP-P
JITTER PERFORMANCE WITH EQ = On, PE = Off (Figure 7 Figure 9)
tRJ1D
tRJ2D
tDJ1D
tDJ2D
tTJ1D
tTJ2D
Random Jitter (RMS Value)
Test Channel D
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
Deterministic Jitter (Peak to Peak)
Test Channel D
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
16
24
ps
3.125 Gbps
12
24
ps
Total Jitter (Peak to Peak)
Test Channel D
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.07
0.11
UIP-P
3.125 Gbps
0.07
0.11
UIP-P
5
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DS25CP102Q
AC Electrical Characteristics
DS25CP102Q
Symbol
Parameter
Conditions
Min
Typ
Max
Units
JITTER PERFORMANCE WITH EQ = On, PE = On (Figure 8 Figure 9)
tRJ1BD
tRJ2BD
tDJ1BD
tDJ2BD
tTJ1BD
tTJ2BD
Random Jitter (RMS Value)
Input Test Channel D
Output Test Channel B
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
Deterministic Jitter (Peak to Peak)
Input Test Channel D
Output Test Channel B
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
14
31
ps
3.125 Gbps
6
21
ps
Total Jitter (Peak to Peak)
Input Test Channel D
Output Test Channel B
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.08
0.15
UIP-P
3.125 Gbps
0.10
0.16
UIP-P
Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
Note 13: tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode (any one input to
all outputs).
Note 14: tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to
devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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DS25CP102Q
DC Test Circuits
30063320
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
30063321
FIGURE 2. Differential Driver AC Test Circuit
30063322
FIGURE 3. Propagation Delay Timing Diagram
30063323
FIGURE 4. LVDS Output Transition Times
7
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DS25CP102Q
Pre-Emphasis and Equalization Test Circuits
30063329
FIGURE 5. Jitter Performance Test Circuit
30063327
FIGURE 6. Pre-Emphasis Performance Test Circuit
30063326
FIGURE 7. Equalization Performance Test Circuit
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8
DS25CP102Q
30063330
FIGURE 8. Pre-Emphasis and Equalization Performance Test Circuit
30063328
FIGURE 9. Test Channel Block Diagram
stant of 3.7 and Loss Tangent of 0.02). The edge coupled
differential striplines have the following geometries: Trace
Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils.
Test Channel Loss Characteristics
The test channel was fabricated with Polyclad PCL-FR-370Laminate/PCL-FRP-370 Prepreg materials (Dielectric conTest Channel
Length
(inches)
500 MHz
750 MHz
1000 MHz
Insertion Loss (dB)
1250 MHz
1500 MHz
1560 MHz
A
10
-1.2
-1.7
-2.0
-2.4
-2.7
-2.8
B
20
-2.6
-3.5
-4.1
-4.8
-5.5
-5.6
C
30
-4.3
-5.7
-7.0
-8.2
-9.4
-9.7
D
15
-1.6
-2.2
-2.7
-3.2
-3.7
-3.8
E
30
-3.4
-4.5
-5.6
-6.6
-7.7
-7.9
F
60
-7.8
-10.3
-12.4
-14.5
-16.6
-17.0
9
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DS25CP102Q
Functional Description
The DS25CP102Q is a 3.125 Gbps 2x2 LVDS digital crosspoint switch optimized for high-speed signal routing and
switching over lossy FR-4 printed circuit board backplanes
and balanced cables.
TABLE 1. Switch Configuration Truth Table
SEL1
SEL0
OUT1
OUT0
0
0
IN0
IN0
0
1
IN0
IN1
1
0
IN1
IN0
1
1
IN1
IN1
TABLE 2. Output Enable Truth Table
EN1
EN0
OUT1
OUT0
0
0
Disabled
Disabled
0
1
Disabled
Enabled
1
0
Enabled
Disabled
1
1
Enabled
Enabled
In addition, the DS25CP102Q has a pre-emphasis control pin
for switching the transmit pre-emphasis to ON and OFF setting and an equalization control pin for switching the receive
equalization to ON and OFF setting. The following are the
transmit pre-emphasis and receive equalization truth tables.
Transmit Pre-Emphasis Truth Table
OUTPUTS OUT0 and OUT1
CONTROL Pin (PE) State
Pre-Emphasis Level
0
OFF
1
ON
Transmit Pre-Emphasis Level Selection
Receive Equalization Truth Table
INPUTS IN0 and IN1
CONTROL Pin (EQ) State
Equalization Level
0
OFF
1
ON
Receive Equalization Level Selection
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10
The DS25CP102Q accepts differential signals and allows
simple AC or DC coupling. With a wide common mode range,
the DS25CP102Q can be DC-coupled with all common dif-
30063331
Typical LVDS Driver DC-Coupled Interface to DS25CP102Q Input
30063332
Typical CML Driver DC-Coupled Interface to DS25CP102Q Input
30063333
Typical LVPECL Driver DC-Coupled Interface to DS25CP102Q Input
11
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DS25CP102Q
ferential drivers (i.e. LVPECL, LVDS, CML). The following
three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS25CP102Q inputs
are internally terminated with a 100Ω resistor.
Input Interfacing
DS25CP102Q
and assumes that the receivers have high impedance inputs.
While most differential receivers have a common mode input
range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to
implementing the suggested interface implementation.
Output Interfacing
The DS25CP102Q outputs signals that are compliant to the
LVDS standard. Its outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers
30063334
Typical DS25CP102Q Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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12
DS25CP102Q
Typical Performance
30063350
30063352
Total Jitter as a Function of Data Rate
Residual Jitter as a Function of Data Rate, FR4 Stripline
Length and EQ Level
30063358
Total Jitter as a Function of Input Common Mode Voltage
30063357
Supply Current as a Function of Data Rate and PE Level
30063351
Residual Jitter as a Function of Data Rate, FR4 Stripline
Length and PE Level
13
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DS25CP102Q
30063360
30063362
A 3.125 Gbps NRZ PRBS-7 without PE or EQ
After 2" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
A 3.125 Gbps NRZ PRBS-7 with PE
After 40" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
30063361
A 3.125 Gbps NRZ PRBS-7 without PE or EQ
After 40" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
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14
DS25CP102Q
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS25CP102QSQ
NS Package Number SQA16A
(See AN-1187 for PCB Design and Assembly Recommendations)
15
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DS25CP102Q Automotive 3.125 Gbps 2X2 LVDS Crosspoint Switch with Signal Conditioning
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