Maxim DS3234SN Extremely accurate spi bus rtc with integrated crystal and sram Datasheet

Rev 0; 2/06
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Features
The DS3234 is a low-cost, extremely accurate SPI™ bus
real-time clock (RTC) with an integrated temperaturecompensated crystal oscillator (TCXO) and crystal. The
DS3234 incorporates a precision, temperature-compensated voltage reference and comparator circuit to monitor VCC. When VCC drops below the power-fail voltage
(VPF), the device asserts the RST output and also disables read and write access to the part when VCC drops
below both VPF and VBAT. The RST pin is monitored as
a pushbutton input for generating a reset externally. The
device switches to the backup supply input and maintains accurate timekeeping when main power to the
device is interrupted. The integration of the crystal resonator enhances the long-term accuracy of the device
as well as reduces the piece-part count in a manufacturing line. The DS3234 is available in commercial and
industrial temperature ranges, and is offered in an
industry-standard 300-mil, 20-pin SO package.
♦ Accuracy ±2ppm from 0°C to +40°C
♦ Accuracy ±3.5ppm from -40°C to +85°C
♦ Battery Backup Input for Continuous
Timekeeping
♦ Operating Temperature Ranges
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
♦ Low-Power Consumption
♦ Real-Time Clock Counts Seconds, Minutes,
Hours, Day, Date, Month, and Year with Leap Year
Compensation Valid Up to 2099
♦ Two Time-of-Day Alarms
♦ Programmable Square-Wave Output
♦ 4MHz SPI Bus Supports Modes 1 and 3
♦ Digital Temp Sensor Output: ±3°C Accuracy
♦ Register for Aging Trim
♦ RST Input/Output
♦ 300-Mil, 20-Pin SO Package
♦ Underwriters Laboratory (UL) Recognized
The DS3234 also integrates 256 bytes of battery-backed
SRAM. In the event of main power loss, the contents of
the memory are maintained by the power source connected to the VBAT pin. The RTC maintains seconds,
minutes, hours, day, date, month, and year information.
The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the
24-hour or 12-hour format with AM/PM indicator. Two
programmable time-of-day alarms and a programmable
square-wave output are provided. Address and data are
transferred serially by an SPI bidirectional bus.
Applications
Servers
Telematics
Utility Power Meters
GPS
Ordering Information
PART
DS3234S#
PINPACKAGE
TEMP RANGE
0°C to +70°C
20 SO
TOP
MARK
DS3234S
DS3234SN#
-40°C to +85°C
20 SO
DS3234SN
# Denotes a RoHS-compliant device that may include lead that
is exempt under the RoHS requirements. Lead finish is JESD97
Category e3, and is compatible with both lead-based and
lead-free soldering processes. A "#" anywhere on the top mark
denotes a RoHS-compliant device.
Pin Configuration
Typical Operating Circuit
TOP VIEW
VCC
VPU
VCC
SS
SCLK
MOSI
MISO
RST
CPU
PUSHBUTTON
RESET
VCC
CS
SCLK
DIN
DOUT
RST
N.C.
N.C.
N.C.
N.C.
N.C.
INT/SQW
32kHz
VBAT
DS3234
SPI is a trademark of Motorola, Inc.
GND
N.C.
N.C.
N.C.
N.C.
CS 1
20 SCLK
N.C. 2
19 DOUT
32kHz 3
18 SCLK
VCC 4
INT/SQW 5
17 DIN
DS3234
16 VBAT
RST 6
15 GND
N.C. 7
14 N.C.
N.C. 8
13 N.C.
N.C. 9
12 N.C.
N.C. 10
11 N.C.
SO
______________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
DS3234
General Description
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground......-0.3V to +6.0V
Operating Temperature Range
(noncondensing) .............................................-40°C to +85°C
Junction Temperature ......................................................+125°C
Storage Temperature Range ...............................-40°C to +85°C
Soldering Temperature
(leads, 10s) ...........................................................+260°C/10s
Soldering Temperature (reflow, 2 times max) .......See IPC/JEDEC
J-STD-020 Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER
MIN
TYP
MAX
VCC
2.0
3.3
5.5
VBAT
2.0
3.0
3.8
Logic 1 Input CS, SCLK, DIN
VIH
0.7 x
VCC
VCC +
0.3
Logic 0 Input CS, SCLK, DIN,
RST
VIL
2.0V ≤ VCC ≤ 3.63V
-0.3
+0.2 x
VCC
3.63V < VCC ≤ 5.5V
-0.3
+0.7
Supply Voltage
Pullup Voltage INT/SQW
SYMBOL
VPU
CONDITIONS
VCC = 0V
5.5
UNITS
V
V
V
V
ELECTRICAL CHARACTERISTICS
(VCC = 2.0V to 5.5V, VCC = active supply (see Table 1), TA = -40°C to +85°C, unless otherwise noted.) (Typical values are at VCC =
3.3V, VBAT = 3.0V, and TA = +25°C, unless otherwise noted. TCXO operation guaranteed from 2.3V to 5.5V on VCC and 2.3V to 3.8V on
VBAT.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Active Supply Current
ICCA
SCLK = 4MHz, BSY = 0
(Notes 3, 4)
VCC = 3.63V
400
VCC = 5.5V
700
120
ICCS
CS = VIH, 32kHz output off,
SQW output off
(Note 4)
VCC = 3.63V
Standby Supply Current
VCC = 5.5V
160
SPI bus inactive, 32kHz
output off, SQW output off
VCC = 3.63V
500
VCC = 5.5V
600
Temperature Conversion Current
Power-Fail Voltage
VBAT Leakage Current
ICCSCONV
UNITS
µA
µA
VPF
2.45
µA
2.575
2.70
V
25
100
nA
IBATLKG
(VCC = 2.0V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 1 and 2)
Logic 1 Output, 32kHz
IOH = -500µA
IOH = -250µA
IOH = -125µA
2
VOH
VCC > 3.63V,
3.63V > VCC > 2.7V,
2.7V > (VCC or VBAT) > 2.0V
(BB32kHz = 1)
_____________________________________________________________________
0.85 x VCC
V
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
(VCC = 2.0V to 5.5V, VCC = active supply (see Table 1), TA = -40°C to +85°C, unless otherwise noted.) (Typical values are at VCC =
3.3V, VBAT = 3.0V, and TA = +25°C, unless otherwise noted. TCXO operation guaranteed from 2.3V to 5.5V on VCC and 2.3V to 3.8V on
VBAT.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.4
V
Logic 0 Output, 32kHz
VOL
IOL = 1mA
Logic 1 Output, DOUT
VOH
IOH = -1.0mA
Logic 0 Output, DOUT, INT/SQW
VOL
IOL = 3mA
0.4
V
Logic 0 Output, RST
VOL
IOL = 1.0mA
0.4
V
Output Leakage Current 32kHz,
INT/SQW, DOUT
ILO
Output high impedance
+1
µA
Input Leakage DIN, CS, SCLK
ILI
RST Pin I/O Leakage
IOL
0.85 x VCC
-1
RST high impedance (Note 5)
V
0
-1
+1
µA
-200
+10
µA
TCXO (VCC = 2.3V to 5.5V, VBAT = 2.3V to 3.8V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 1 and 2)
Output Frequency
fOUT
VCC = 3.3V or VBAT = 3.3V
32.768
0°C to +40°C
Frequency Stability vs.
Temperature
Frequency Stability vs. Voltage
Trim Register Frequency
Sensitivity per LSB
Temperature Accuracy
Crystal Aging
∆f/fOUT
VCC = 3.3V or
VBAT = 3.3V
-40°C to 0°C and
+40°C to +85°C
+2
-3.5
+3.5
1
∆f/V
∆f/LSB
Specified at:
-40°C
0.7
+25°C
0.1
+70°C
0.4
+85°C
0.8
Temp
∆f/fOUT
kHz
-2
-3
After reflow,
not production tested
ppm/V
ppm
+3
First year
±1.0
0–10 years
±5.0
ppm
°C
ppm
ELECTRICAL CHARACTERISTICS
(VCC = 0V, VBAT = 2.0V to 3.8V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Battery Current
(Note 4)
IBAT
Temperature Conversion Current
ITC
Data-Retention Current
IBATTC
CONDITIONS
MIN
TYP
MAX
VBAT = 3.4V
1.5
2.3
VBAT = 3.8V
1.5
2.5
EOSC = 0, BBSQW = 0
UNITS
µA
EOSC = 0, BBSQW = 0
400
µA
EOSC = 1
100
nA
_____________________________________________________________________
3
DS3234
ELECTRICAL CHARACTERISTICS (continued)
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.0V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SCLK Clock Frequency
SYMBOL
fSCL
CONDITIONS
MIN
TYP
MAX
2.7V ≤ VCC ≤ 5.5V
4
2.0V ≤ VCC < 2.7V
2
UNITS
MHz
Data to SCLK Setup
tDC
30
ns
SCLK to Data Hold
tCDH
30
ns
SCLK to CS Setup
tCCS
SCLK to Data Valid (Note 6)
tCDD
SCLK Low Time
tCL
SCLK High Time
tCH
SCLK Rise and Fall
tR, tF
CS to SCLK Setup
tCC
SCLK to CS Hold
tCCH
CS Inactive Time
tCWH
30
ns
2.7V ≤ VCC ≤ 5.5V
80
2.0V ≤ VCC < 2.7V
160
2.7V ≤ VCC ≤ 5.5V
110
2.0V ≤ VCC < 2.7V
220
2.7V ≤ VCC ≤ 5.5V
110
2.0V ≤ VCC < 2.7V
220
ns
ns
200
400
2.7V ≤ VCC ≤ 5.5V
100
2.0V ≤ VCC < 2.7V
200
ns
ns
ns
ns
400
ns
CS to Output High Impedance
tCDZ
Pushbutton Debounce
PBDB
250
ms
tRST
250
ms
Reset Active Time
Oscillator Stop Flag (OSF) Delay
Temperature Conversion Time
tOSF
(Note 7)
40
(Note 8)
100
tCONV
ns
ms
125
200
ms
TYP
MAX
UNITS
POWER-SWITCH CHARACTERISTICS
(TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
VCC Fall Time; VPF(MAX) to
VPF(MIN)
tVCCF
300
µs
VCC Rise Time; VPF(MIN) to
VPF(MAX)
tVCCR
0
µs
Recovery at Power-Up
tREC
(Note 9)
125
300
ms
TYP
CAPACITANCE
(TA = +25°C)
MAX
UNITS
Capacitance on All Input Pins
PARAMETER
CIN
(Note 10)
10
pF
Capacitance on All Output Pins
CIO
Outputs high impedance (Note 10)
10
pF
4
SYMBOL
CONDITIONS
_____________________________________________________________________
MIN
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
RST
PBDB
tRST
Power-Switch Timing
VCC
VPF(MAX)
VPF
VPF(MIN)
tVCCF
VPF
tVCCR
tREC
RST
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may
cause loss of data.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Limits at -40°C are guaranteed by design and not production tested.
All voltages are referenced to ground.
Measured at VIH = 0.8 x VCC or VIL = 0.2 x VCC, 10ns rise/fall time, DOUT = no load.
Current is the averaged input current, which includes the temperature conversion current. CRATE1 = CRATE0 = 0.
The RST pin has an internal 50kΩ (nominal) pullup resistor to VCC.
Measured at VOH = 0.8 x VCC or VOL = 0.2 x VCC. Measured from the 50% point of SCLK to the VOH minimum of DOUT.
With 50pF load.
The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
0V ≤ VCC ≤ VCC(MAX) and 2.3V ≤ VBAT ≤ VBAT(MAX).
Note 9: This delay only applies if the oscillator is enabled and running. If the EOSC bit is 1, tREC is bypassed and RST immediately
goes high.
Note 10: Guaranteed by design and not production tested.
_____________________________________________________________________
5
DS3234
Pushbutton Reset Timing
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
DS3234
Timing Diagram—SPI Read Transfer
CS tCCS
tCC
tR
tF
SCLK
tCL
tCDZ
tCH
tCDH
tCDD
tDC
DIN
A6
W/R
A0
DOUT
D7
HIGH IMPEDANCE
WRITE ADDRESS BYTE
D0
READ DATA BYTE
NOTE: SCLK CAN BE EITHER POLARITY, SHOWN FOR CPOL = 1.
Timing Diagram—SPI Write Transfer
tCWH
CS
tCC
SCLK
DIN
tCDH
tDC
W/R
tCCH
tF
tR
tCL
tCH
A6
A0
WRITE ADDRESS BYTE
DOUT
6
D7
D0
WRITE DATA BYTE
HIGH IMPEDANCE
_____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
BATTERY CURRENT
vs. SUPPLY VOLTAGE
VCC = 0V
BB32kHz = 0
2350
SUPPLY CURRENT (nA)
SUPPLY CURRENT (µA)
125
100
75
50
DS3234 toc02
INPUTS = GND
RST ACTIVE
2600
DS3234 toc01
150
BBSQW = 1
2100
1850
1600
1350
1100
25
600
0
3.3
3.8
4.8
4.3
3.3
2.8
3.8
VCC (V)
SUPPLY VOLTAGE (VBAT)
BATTERY CURRENT
vs. TEMPERATURE
FREQUENCY DEVIATION
vs. TEMPERATURE vs. AGING VALUE
VCC = 0V
BB32kHz = 0
BBSQW = 0
VBAT = 3.4V
750
65
DS3234 toc03
850
800
2.3
5.3
AGING = -128
55
VBAT = 3.0V
700
650
DS3234 toc04
2.8
FREQUENCY DEVIATION (ppm)
2.3
45
AGING = -33
35
25
AGING = 0
15
5
-5
-15
AGING = 127
-25
AGING = 32
-35
-45
600
-20
0
20
40
TEMPERATURE (°C)
60
-40
80
-20
0
20
40
60
80
TEMPERATURE (°C)
ICCA vs. DOUT LOAD
DS3234 toc05
-40
500
SUPPLY CURRENT (µA)
SUPPLY CURRENT (nA)
BBSQW = 0
850
450
400
SCLK = 4MHz
350
300
250
200
0
10
20
30
40
CAPACITANCE (pF)
_____________________________________________________________________
7
DS3234
Typical Operating Characteristics
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Pin Description
PIN
NAME
1
CS
2, 7–14
N.C.
3
32kHz
4
VCC
8
FUNCTION
Active-Low Chip Select Input. Used to select or deselect the device.
No Connection. Not connected internally. Must be connected to ground.
32kHz Push-Pull Output. If disabled with either EN32kHz = 0 or BB32kHz = 0, the state of the 32kHz pin will be
low.
DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1µF to 1.0µF capacitor.
5
Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor. It can be
left open if not used. This multifunction pin is determined by the state of the INTCN bit in the Control Register
(0Eh). When INTCN is set to logic 0, this pin outputs a square wave and its frequency is determined by RS2
INT/SQW
and RS1 bits. When INTCN is set to logic 1, then a match between the timekeeping registers and either of the
alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the INTCN bit is set to logic 1
when power is first applied, the pin defaults to an interrupt output with alarms disabled.
6
RST
Active-Low Reset. This pin is an open-drain input/output. It indicates the status of VCC relative to the
VPF specification. As VCC falls below VPF, the RST pin is driven low. When VCC exceeds VPF, for tRST, the RST
pin is driven high impedance. The active-low, open-drain output is combined with a debounced pushbutton input
function. This pin can be activated by a pushbutton reset request. It has an internal 50kΩ nominal value pullup
resistor to VCC. No external pullup resistors should be connected. If the crystal oscillator is disabled, tRST is
bypassed and RST immediately goes high.
15
GND
Ground
16
VBAT
Backup Power-Supply Input. If VBAT is not used, connect to ground. Diodes placed in series between the VBAT
pin and the battery can cause improper operation. UL recognized to ensure against reverse charging when
used with a lithium battery. Go to www.maxim-ic.com/qa/info/ul.
17
DIN
SPI Data Input. Used to shift address and data into the device.
18, 20
SCLK
SPI Clock Input. Used to control timing of data into and out of the device. Either clock polarity can be used. The
clock polarity is determined by the device based on the state of SCLK when CS goes low. Pins 18 and 20 are
electrically connected together internally.
19
DOUT
SPI Data Output. Data is output on this pin when the device is in read mode; CMOS push-pull driver.
_____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
VCC
X1
RST
OSCILLATOR AND
CAPACITOR ARRAY
CONTROL LOGIC/
DIVIDER
X2
PUSHBUTTON RESET;
SQUARE-WAVE BUFFER;
INT/SQW CONTROL
N
32kHz
DS3234
VCC
VBAT
POWER CONTROL
TEMPERATURE
SENSOR
CONTROL AND STATUS
REGISTERS
GND
INT/SQW
N
SRAM
CS
SCLK
SCLK
SPI INTERFACE AND
ADDRESS REGISTER
DECODE
DIN
CLOCK AND CALENDAR
REGISTERS
USER BUFFER
(7 BYTES)
DOUT
Detailed Description
The DS3234 is a TCXO and RTC with integrated crystal
and 256 bytes of SRAM. An integrated sensor periodically samples the temperature and adjusts the oscillator
load to compensate for crystal drift caused by temperature variations. The DS3234 provides user-selectable
sample rates. This allows the user to select a temperature sensor sample rate that allows for various temperature rates of change, while minimizing current
consumption by temperature sensor sampling. The user
should select a sample rate based upon the expected
temperature rate of change, with faster sample rates for
applications where the ambient temperature changes
significantly over a short time. The TCXO provides a stable and accurate reference clock, and maintains the
RTC to within ±2 minutes per year accuracy from -40°C
to +85°C. The TCXO frequency output is available at the
32kHz pin. The RTC is a low-power clock/calendar with
_____________________________________________________________________
9
DS3234
Block Diagram
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
two programmable time-of-day alarms and a programmable square-wave output. The INT/SQW provides either
an interrupt signal due to alarm conditions or a squarewave output. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The
date at the end of the month is automatically adjusted for
months with fewer than 31 days, including corrections for
leap year. The clock operates in either the 24-hour or 12hour format with AM/PM indicator. Access to the internal
registers is possible through an SPI bus interface.
A temperature-compensated voltage reference and
comparator circuit monitors the level of VCC to detect
power failures and to automatically switch to the backup
supply when necessary. When operating from the backup supply, access is inhibited to minimize supply current. Oscillator, time and date, and TCXO operations can
continue while the backup supply powers the device.
The RST pin provides an external pushbutton function
and acts as an indicator of a power-fail event.
Operation
The block diagram shows the main elements of the
DS3234. The eight blocks can be grouped into four
functional groups: TCXO, power control, pushbutton
function, and RTC. Their operations are described separately in the following sections.
both V PF and V BAT, the internal clock registers are
blocked from any access. If VPF is less than VBAT, the
device power is switched from VCC to VBAT when VCC
drops below V PF . If V PF is greater than V BAT , the
device power is switched from VCC to VBAT when VCC
drops below VBAT. After VCC returns above both VPF
and VBAT, read and write access is allowed after RST
goes high (Table 1).
Table 1. Power Control
SUPPLY CONDITION
READ/WRITE
ACCESS
ACTIVE
SUPPLY
RST
VCC < VPF, VCC < VBAT
No
VBAT
Active
VCC < VPF, VCC > VBAT
Yes
VCC
Active
VCC > VPF, VCC < VBAT
Yes
VCC
Inactive
VCC > VPF, VCC > VBAT
Yes
VCC
Inactive
To preserve the battery, the first time VBAT is applied to
the device, the oscillator does not start up until VCC
crosses VPF. After the first time VCC is ramped up, the
oscillator starts up and the VBAT source powers the
oscillator during power-down and keeps the oscillator
running. When the DS3234 switches to VBAT, the oscillator may be disabled by setting the EOSC bit.
32kHz TCXO
Pushbutton Reset Function
The temperature sensor, oscillator, and control logic form
the TCXO. The controller reads the output of the on-chip
temperature sensor and uses a lookup table to determine
the capacitance required, adds the aging correction in
the AGE register, and then sets the capacitance selection
registers. New values, including changes to the AGE register, are loaded only when a change in the temperature
value occurs. The temperature is read on initial application of VCC and once every 64 seconds (default, see the
description for CRATE1 and CRATE0 in the Control/Status
Register section) afterwards.
The DS3234 provides for a pushbutton switch to be connected to the RST output pin. When the DS3234 is not in
a reset cycle, it continuously monitors the RST signal for a
low going edge. If an edge transition is detected, the
DS3234 debounces the switch by pulling the RST low.
After the internal timer has expired (PBDB), the DS3234
continues to monitor the RST line. If the line is still low, the
DS3234 continuously monitors the line looking for a rising
edge. Upon detecting release, the DS3234 forces the
RST pin low and holds it low for tRST.
Power Control
The power control function is provided by a temperature-compensated voltage reference and a comparator
circuit that monitors the VCC level. The device is fully
accessible and data can be written and read when VCC
is greater than VPF. However, when VCC falls below
10
The same pin, RST, is used to indicate a power-fail condition. When VCC is lower than VPF, an internal power-fail
signal is generated, which forces the RST pin low. When
VCC returns to a level above VPF, the RST pin is held low
for tREC to allow the power supply to stabilize. If the
EOSC bit is set to logic 1 (to disable the oscillator in battery-backup mode), the reset signal is kept active for
tREC plus the startup time of the oscillator (typ 1 second).
____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
SRAM
The DS3234 provides 256 bytes of general-purpose battery-backed read/write memory. The SRAM can be written or read whenever VCC is above either VPF or VBAT.
Address Map
Figure 1 shows the address map for the DS3234 timekeeping registers. During a multibyte access, when the
address pointer reaches the end of the register space
(13h read, 93h write), it wraps around to the beginning
(00h read, 80h write). The DS3234 does not respond to a
read or write to any reserved address, and the internal
address pointer does not increment. Address pointer
operation when accessing the 256-byte SRAM data is
covered in the description of the SRAM address and data
registers. On the falling edge of CS, or during a multibyte
access when the address pointer increments to location
00h, the current time is transferred to a second set of registers. The time information is read from these secondary
registers, while the internal clock registers continue to
increment normally. If the time and date registers are
read using a multibyte read, this eliminates the need to
reread the registers in case the main registers update
during a read.
SPI Interface
The DS3234 operates as a slave device on the SPI serial bus. Access is obtained by selecting the part by the
CS pin and clocking data into/out of the part using the
SCLK and DIN/DOUT pins. Multiple byte transfers are
supported within one CS low period. The SPI on the
DS3234 interface is accessible whenever VCC is above
either VBAT or VPF.
Clock and Calendar
The time and calendar information is obtained by reading the appropriate register bytes. Figure 1 illustrates
the RTC registers. The time and calendar data are set
or initialized by writing the appropriate register bytes.
The contents of the time and calendar registers are in
binary-coded decimal (BCD) format. The DS3234 can
be run in either 12-hour or 24-hour mode. Bit 6 of the
hours register is defined as the 12- or 24-hour mode
select bit. When high, 12-hour mode is selected. In 12hour mode, bit 5 is the AM/PM bit with logic-high being
PM. In 24-hour mode, bit 5 is the second 10-hour bit
(20–23 hours). The century bit (bit 7 of the month register) is toggled when the years register overflows from
99 to 00.
The day-of-week register increments at midnight.
Values that correspond to the day of week are userdefined but must be sequential (i.e., if 1 equals
Sunday, then 2 equals Monday, and so on). Illogical
time and date entries result in undefined operation.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the
internal registers update. When reading the time and date
registers, the user buffers are synchronized to the internal
registers on the falling edge of CS or and when the register pointer rolls over to zero. The time information is read
from these secondary registers, while the clock continues
to run. This eliminates the need to reread the registers in
case the main registers update during a read.
The countdown chain is reset whenever the seconds
register is written. Write transfers occur on the acknowledge from the DS3234. Once the countdown chain is
reset, to avoid rollover issues the remaining time and
date registers must be written within 1 second. The 1Hz
square-wave output, if enabled, transitions high 500ms
after the seconds data transfer.
____________________________________________________________________
11
DS3234
Real-Time Clock
With the clock source from the TCXO, the RTC provides
seconds, minutes, hours, day, date, month, and year
information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either
the 24-hour or 12-hour format with an AM/PM indicator.
The clock provides two programmable time-of-day
alarms and a programmable square-wave output. The
INT/SQW pin either generates an interrupt due to alarm
condition or outputs a square-wave signal and the
selection is controlled by the bit INTCN.
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Figure 1. Address Map for DS3234 Timekeeping Registers and SRAM
ADDRESS
READ/WRITE
MSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
FUNCTION
RANGE
00h
80h
0
10 Seconds
Seconds
Seconds
00–59
01h
81h
0
10 Minutes
Minutes
Minutes
00–59
02h
82h
0
12/24
Hour
Hours
1-12 +AM /PM
00-23
03h
83h
0
0
Day
1-7
04h
84h
0
0
Date
Date
01-31
Month
Month/
Century
01-12 + Century
Year
Year
00-99
00-59
05h
85h
06h
86h
Century
AM/PM
10 hr
10 hr
0
0
0
Day
10 Date
0
0
10 Mo
10 Year
07h
87h
A1M1
10 Seconds
Seconds
Alarm 1
Seconds
08h
88h
A1M2
10 Minutes
Minutes
Alarm 1
Minutes
00-59
09h
89h
A1M3
12/24
Hour
Alarm 1
Hours
1-12 +AM /PM
00-23
0Ah
8Ah
A1M4
DY/DT
Day
Date
Alarm 1 Day
Alarm 1 Date
1-7
01-31
0Bh
8Bh
A2M2
Minutes
Alarm 2
Minutes
00-59
0Ch
8Ch
A2M3
12/24
Hour
Alarm 2
Hours
1-12 +AM /PM
00-23
0Dh
8Dh
A2M4
DY/DT
Day
Date
Alarm 2 Day
Alarm 2 Date
1-7
01-31
0Eh
8Eh
EOSC
BBSQW
A1IE
Control
—
—
—
AM/PM
0Fh
8Fh
OSF
10h
90h
SIGN
11h
91h
12h
92h
13h
93h
14h–17h
94h–97h
10 hr
10 hr
0
10 Date
10 Minutes
AM/PM
10 hr
10 hr
0
10 Date
CONV
RS2
RS1
BB32kHz CRATE1 CRATE0 EN32kHz
INTCN
A2IE
BSY
A2F
A1F
Control/
Status
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Crystal Aging
Offset
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Temp MSB
Read Only
DATA
DATA
0
0
0
0
0
0
Temp LSB
Read Only
0
0
0
0
0
0
0
BB_TD
Disable
Temp
Conversions
—
—
—
—
—
—
—
—
—
Reserved
—
—
—
18h
98h
A7
A6
A5
A4
A3
A2
A1
A0
SRAM
Address
19h
99h
D7
D6
D5
D4
D3
D2
D1
D0
SRAM Data
Note: Unless otherwise specified, the registers’ state is not defined when power is first applied. Bits defined as 0 cannot be written
to 1 and will always read 0.
12
____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
The DY/DT bits (bit 6 of the alarm day/date registers)
control whether the alarm value stored in bits 0 to 5 of
that register reflects the day of the week or the date of
the month. If DY/DT is written to logic 0, the alarm will
be the result of a match with date of the month. If
DY/DT is written to logic 1, the alarm will be the result of
a match with day of the week.
When the RTC register values match alarm register settings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is
set to logic 1. If the corresponding Alarm Interrupt
Enable ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the
INTCN bit is set to logic 1, the alarm condition activates
the INT/SQW signal. The match is tested on the onceper-second update of the time and date registers.
The DS3234 contains two time-of-day/date alarms. Alarm
1 can be set by writing to registers 07h to 0Ah. Alarm 2
can be set by writing to registers 0Bh to 0Dh. The alarms
can be programmed (by the alarm enable and INTCN
bits of the control register) to activate the INT/SQW output
on an alarm match condition. Bit 7 of each of the time-ofday/date alarm registers are mask bits (Table 2). When all
the mask bits for each alarm are logic 0, an alarm only
occurs when the values in the timekeeping registers
match the corresponding values stored in the time-ofday/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or
date. Table 2 shows the possible settings. Configurations
not listed in the table will result in illogical operations.
Table 2. Alarm Mask Bits
DY/DT
ALARM 1 REGISTER MASK BITS (BIT 7)
ALARM RATE
A1M4
A1M3
A1M2
A1M1
X
1
1
1
1
Alarm once per second
X
1
1
1
0
Alarm when seconds match
X
1
1
0
0
Alarm when minutes and seconds match
X
1
0
0
0
Alarm when hours, minutes, and seconds match
0
0
0
0
0
Alarm when date, hours, minutes, and seconds match
1
0
0
0
0
Alarm when day, hours, minutes, and seconds match
DY/DT
ALARM 2 REGISTER MASK BITS (BIT 7)
ALARM RATE
A2M4
A2M3
A2M2
X
1
1
1
Alarm once per minute (00 seconds of every minute)
X
1
1
0
Alarm when minutes match
X
1
0
0
Alarm when hours and minutes match
0
0
0
0
Alarm when date, hours, and minutes match
1
0
0
0
Alarm when day, hours, and minutes match
____________________________________________________________________
13
DS3234
Alarms
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Control Register (0Eh/8Eh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
EOSC
BBSQW
CONV
RS2
RS1
INTCN
A2IE
A1IE
POR*:
0
0
0
1
1
1
0
0
*POR is defined as the first application of power to the device, either VBAT or VCC.
Special-Purpose Registers
The DS3234 has two additional registers (control and
control/status) that control the real-time clock, alarms,
and square-wave output.
Control Register (0Eh/8Eh)
Bit 7: Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscillator is stopped when the DS3234 switches to battery
power. This bit is clear (logic 0) when power is first
applied. When the DS3234 is powered by VCC, the
oscillator is always on regardless of the status of the
EOSC bit.
Bit 6: Battery-Backed Square-Wave Enable
(BBSQW). When set to logic 1, this bit enables the
square-wave or interrupt output when VCC is absent and
the DS3234 is being powered by the VBAT pin. When
BBSQW is logic 0, the INT/SQW pin goes high impedance when VCC falls below the power-fail trip point. This
bit is disabled (logic 0) when power is first applied.
Bit 5: Convert Temperature (CONV). Setting this bit to
1 forces the temperature sensor to convert the temperature into digital code and execute the TCXO algorithm
to update the capacitance array to the oscillator. This
can only happen when a conversion is not already in
progress. The user should check the status bit BSY
before forcing the controller to start a new TCXO execution. A user-initiated temperature conversion does
not affect the internal 64-second (default interval)
update cycle. This bit is disabled (logic 0) when power
is first applied.
A user-initiated temperature conversion does not affect
the BSY bit for approximately 2ms. The CONV bit
remains at a 1 from the time it is written until the conversion is finished, at which time both CONV and BSY go
to 0. The CONV bit should be used when monitoring
the status of a user-initiated conversion.
14
Bits 4 and 3: Rate Select (RS2 and RS1). These bits
control the frequency of the square-wave output when
the square wave has been enabled. The following table
shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1
(8.192kHz) when power is first applied.
SQUARE-WAVE OUTPUT FREQUENCY
SQUARE-WAVE OUTPUT
FREQUENCY
RS2
RS1
0
0
1Hz
0
1
1.024kHz
1
0
4.096kHz
1
1
8.192kHz
Bit 2: Interrupt Control (INTCN). This bit controls the
INT/SQW signal. When the INTCN bit is set to logic 0, a
square wave is output on the INT/SQW pin. When the
INTCN bit is set to logic 1, a match between the timekeeping registers and either of the alarm registers activates the INT/SQW (if the alarm is also enabled). The
corresponding alarm flag is always set regardless of
the state of the INTCN bit. The INTCN bit is set to logic
1 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to
logic 1, this bit permits the alarm 2 flag (A2F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A2IE bit is set to logic 0 or INTCN is set to
logic 0, the A2F bit does not initiate an interrupt signal.
The A2IE bit is disabled (logic 0) when power is first
applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to
logic 1, this bit permits the alarm 1 flag (A1F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A1IE bit is set to logic 0 or INTCN is set to
logic 0, the A1F bit does not initiate the INT/SQW signal. The A1IE bit is disabled (logic 0) when power is
first applied.
____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
OSF
BB32kHz
CRATE1
CRATE0
EN32kHz
BSY
A2F
A1F
POR*:
1
0
0
0
1
0
0
0
*POR is defined as the first application of power to the device, either VBAT or VCC.
Control/Status Register (0Fh/8Fh)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator either is stopped or was
stopped for some period and may be used to judge the
validity of the timekeeping data. This bit is set to logic 1
any time that the oscillator stops. The following are
examples of conditions that can cause the OSF bit to
be set:
1) The first time power is applied.
2) The voltages present on both VCC and VBAT are
insufficient to support oscillation.
3) The EOSC bit is turned off in battery-backed mode.
4) External influences on the crystal (i.e., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0.
Bit 6: Battery-Backed 32kHz Output (BB32kHz). This
bit enables the 32kHz output when powered from VBAT
(provided EN32kHz is enabled). If BB32kHz = 0, the
32kHz output is low when the part is powered by VBAT.
This bit is disabled (logic 0) when power is first applied.
Bits 5 and 4: Conversion Rate (CRATE1 and
CRATE0). These two bits control the sample rate of the
TCXO. The sample rate determines how often the temperature sensor makes a conversion and applies compensation to the oscillator. Decreasing the sample rate
decreases the overall power consumption by decreasing the frequency at which the temperature sensor
operates. However, significant temperature changes
that occur between samples may not be completely
compensated for, which reduce overall accuracy.
These bits are set to logic 0 when power is first applied.
Bit 3: Enable 32kHz Output (EN32kHz). This bit indicates the status of the 32kHz pin. When set to logic 1,
the 32kHz pin is enabled and outputs a 32.768kHz
square-wave signal. When set to logic 0, the 32kHz pin is
low. The initial power-up state of this bit is logic 1, and a
32.768kHz square-wave signal appears at the 32kHz pin
after a power source is applied to the DS3234. This bit is
enabled (logic 1) when power is first applied.
Bit 2: Busy (BSY). This bit indicates the device is busy
executing TCXO functions. It goes to logic 1 when the
conversion signal to the temperature sensor is asserted
and then is cleared when the conversion is complete.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag
bit indicates that the time matched the alarm 2 registers. If the A2IE bit and INTCN bit are set to logic 1, the
INT/SQW pin is driven low while A2F is active. A2F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag
bit indicates that the time matched the alarm 1 registers. If the A1IE bit and the INTCN bit are set to logic 1,
the INT/SQW pin is driven low while A1F is active. A1F
is cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
SAMPLE RATE
(seconds)
CRATE1
CRATE0
0
0
64
0
1
128
1
0
256
1
1
512
____________________________________________________________________
15
DS3234
Control/Status Register (0Fh/8Fh)
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Aging Offset (10h/90h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
POR*:
0
0
0
0
0
0
0
0
Temperature Register (MSB) (11h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
POR*:
0
0
0
0
0
0
0
0
Temperature Register (LSB) (12h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
DATA
DATA
0
0
0
0
0
0
POR*:
0
0
0
0
0
0
0
0
*POR is defined as the first application of power to the device, either VBAT or VCC.
Aging Offset Register (10h/90h)
The aging offset register provides an 8-bit code to add
to or subtract from the oscillator capacitor array. The
data is encoded in two’s complement, with bit 7 representing the SIGN bit. One LSB represents the smallest
capacitor to be switched in or out of the capacitance
array at the crystal pins. The offset register is added to
the capacitance array during a normal temperature
conversion, if the temperature changes from the previous conversion, or during a manual user conversion
(setting the CONV bit). To see the effects of the aging
register on the 32kHz output frequency immediately, a
manual conversion should be performed after each
aging offset register change.
Positive aging values add capacitance to the array,
slowing the oscillator frequency. Negative values
remove capacitance from the array, increasing the
oscillator frequency.
16
The change in ppm per LSB is different at different temperatures. The frequency vs. temperature curve is shifted by the values used in this register. At +25°C, one
LSB typically provides about 0.1ppm change in frequency. These bits are all set to logic 0 when power is
first applied.
Temperature Registers (11h–12h)
Temperature is represented as a 10-bit code with a resolution of 0.25°C and is accessible at location 11h and
12h. The temperature is encoded in two’s complement
format, with bit 7 in the MSB representing the SIGN bit.
The upper 8 bits are at location 11h and the lower 2 bits
are in the upper nibble at location 12h. Upon power
reset, the registers are set to a default temperature of
0°C and the controller starts a temperature conversion.
New temperature readings are stored in this register.
____________________________________________________________________
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
0
0
0
0
0
0
0
BB_TD
POR*:
0
0
0
0
0
0
0
0
*POR is defined as the first application of power to the device, either VBAT or VCC.
SRAM Address (18h/98h)
NAME:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
A7
A6
A5
A4
A2
A1
A1
A0
SRAM Data (19h/99h)
NAME:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
D7
D6
D5
D4
D2
D1
D1
D0
Note: These registers do not default to any specific value.
Temperature Control
Register (13h/93h)
Bit 0: Battery-Backed Temperature Conversion
Disable (BB_TD). The battery-backed tempconv disable bit prevents automatic temperature conversions
when the device is powered by the VBAT supply. This
reduces the battery current at the expense of frequency accuracy.
SRAM Address Register
(18h/98h)
The SRAM address register provides the 8-bit address
of the 256-byte memory array. The desired memory
address should be written to this register before the
data register is accessed. The contents of this register
are incremented automatically if the data register is
accessed more than once during a single transfer.
When the contents of the address register reach 0FFh,
the next access causes the register to roll over to 00h.
SRAM Data Register (19h/99h)
The SRAM data register provides the data to be written
to or the data read from the 256-byte memory array.
During a read cycle, the data in this register is that
found in the memory location in the SRAM address register (18h/98h). During a write cycle, the data in this register is placed in the memory location in the SRAM
address register (18h/98h). When the SRAM data register is read or written, the internal register pointer
remains at 19h/99h and the SRAM address register
increments after each byte that is read or written, allowing multibyte transfers.
SPI Serial Data Bus
The DS3234 provides a 4-wire SPI serial data bus to communicate in systems with an SPI host controller. The
DS3234 supports both single byte and multiple byte data
transfers for maximum flexibility. The DIN and DOUT pins
are the serial data input and output pins, respectively.
The CS input is used to initiate and terminate a data
transfer. The SCLK pin is used to synchronize data movement between the master (microcontroller) and the slave
devices (see Table 3). The shift clock (SCLK), which is
generated by the microcontroller, is active only during
address and data transfer to any device on the SPI bus.
Input data (DIN) is latched on the internal strobe edge
and output data (DOUT) is shifted out on the shift edge
(Figure 2). There is one clock for each bit transferred.
Address and data bits are transferred in groups of eight.
CS
DATA LATCH (WRITE/INTERNAL STROBE)
SHIFT DATA OUT (READ)
SCLK WHEN CPOL = 0
DATA LATCH (WRITE/INTERNAL STROBE)
SHIFT DATA OUT (READ)
SCLK WHEN CPOL = 1
NOTE 1: CPHA BIT POLARITY (IF APPLICABLE) MAY NEED TO BE SET ACCORDINGLY.
NOTE 2: CPOL IS A BIT SET IN THE MICROCONTROLLER'S CONTROL REGISTER.
NOTE 3: DOUT REMAINS AT HIGH IMPEDANCE UNTIL 8 BITS OF DATA ARE READY TO BE
SHIFTED OUT DURING A READ.
Figure 2. Serial Clock as a Function of Microcontroller ClockPolarity Bit
____________________________________________________________________
17
DS3234
Temperature Control (13h/93h)
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Address and data bytes are shifted MSB first into the
serial data input (DIN) and out of the serial data output
(DOUT). Any transfer requires the address of the byte
to specify a write or read, followed by one or more
bytes of data. Data is transferred out of the DOUT pin
for a read operation and into the DIN for a write operation (Figures 3 and 4).
The address byte is always the first byte entered after
CS is driven low. The most significant bit of this byte
determines if a read or write takes place. If the MSB is
0, one or more read cycles occur. If the MSB is 1, one
or more write cycles occur.
Table 3. SPI Pin Function
CS
SCLK
DIN
DOUT
Disable
H
Input Disabled
Input Disabled
High Impedance
Write
L
Data Bit Latch
High Impedance
Read
L
X
Next Data Bit Shift**
Read Invalid Location
L
Don’t Care
High Impedance
MODE
*CPOL = 1, SCLK Rising
CPOL = 0, SCLK Falling
CPOL = 1, SCLK Falling
CPOL = 0, SCLK Rising
Don’t Care
*CPOL is the clock-polarity bit set in the control register of the host microprocessor.
**DOUT remains at high impedance until 8 bits of data are ready to be shifted out during a read.
CS
SCLK
DIN
R/W
DOUT
A6
A5
A4
A3
A2
A1
A0
A2
A1
A0
D7
D6
D7
D6
D5
D4
D3
D2
D1
D0
HIGH IMPEDANCE
Figure 3. SPI Single-Byte Write
CS
SCLK
DIN
R/W
DOUT
A6
A5
A4
A3
HIGH IMPEDANCE
D5
D4
Figure 4. SPI Single-Byte Read
18
____________________________________________________________________
D3
D2
D1
D0
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
DS3234
CS
SCLK
DIN
WRITE
ADDRESS
BYTE
DATA BYTE 0
DATA BYTE 1
DATA BYTE N
DIN
ADDRESS
BYTE
READ
DOUT
HIGH IMPEDANCE
DATA
BYTE 0
DATA
BYTE 1
DATA
BYTE N
Figure 5. SPI Multiple-Byte Burst Transfer
Data transfers can occur one byte at a time or in multiple-byte burst mode. After CS is driven low, an address
is written to the DS3234. After the address, one or more
data bytes can be written or read. For a single-byte
transfer, one byte is read or written and then CS is driven high. For a multiple-byte transfer, however, multiple
bytes can be read or written after the address has been
written (Figure 5). Each read or write cycle causes the
RTC register address to automatically increment, which
continues until the device is disabled. The address
wraps to 00h after incrementing to 13h (during a read)
and wraps to 80h after incrementing to 93h (during a
write). An updated copy of the time is loaded into the
user buffers upon the falling edge of CS and each time
the address pointer increments from 13h to 00h.
Because the internal and user copies of the time are
only synchronized on these two events, an alarm condition can occur internally and activate the INT/SQW pin
independently of the user data.
If the SRAM is accessed by reading (address 19h) or
writing (address 99h) the SRAM data register, the contents of the SRAM address register are automatically
incremented after the first access, and all data cycles
will use the SRAM data register.
Handling, PC Board Layout,
and Assembly
The DS3234 package contains a quartz tuning-fork
crystal. Pick-and-place equipment can be used, but
precautions should be taken to ensure that excessive
shock and vibration are avoided. Ultrasonic cleaning
should be avoided to prevent damage to the crystal.
Avoid running signal traces under the package, unless
a ground plane is placed between the package and the
signal line. All N.C. (no connect) pins must be connected to ground.
____________________________________________________________________
19
Chip Information
TRANSISTOR COUNT: 48,000
SUBSTRATE CONNECTED TO GROUND
PROCESS: CMOS
Thermal Information
Theta-JA: +55°C/W
Theta-JC: +24°C/W
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/DallasPackInfo).
56-G4009-001.EPS
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Dallas Semiconductor Corporation.
Marichu Quijano
is a registered trademark of Maxim Integrated Products, Inc.
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