TI1 DS3651 Quad high speed mos sense amplifier Datasheet

DS1651,DS3651
DS1651/DS3651 Quad High Speed MOS Sense Amplifiers
Literature Number: SNLS371
DS1651/DS3651
Quad High Speed MOS Sense Amplifiers
General Description
Features
The DS1651/DS3651 is TTL compatible high speed circuits
intended for sensing in a broad range of MOS memory system applications. Switching speeds have been enhanced
over conventional sense amplifiers by application of Schottky technology, and TRI-STATE ® strobing is incorporated, offering a high impedance output state for bused organization.
n
n
n
n
n
n
The DS1651/DS3651 has active pull-up outputs and offers
open collector outputs providing implied “AND” operations.
Connection Diagram
High speed
TTL compatible
Input sensitivity — ± 7 mV
TRI-STATE outputs for high speed buses
Standard supply voltages — ± 5V
Pin and function compatible with MC3430
Truth Table
Dual-in-Line Package
Input
Strobe
Output
DS3651
VID ≥ 7 mW
TA = 0˚C to +70˚C
L
H
H
Open
−7 mV ≤ VID ≤ +7 mV
TA = 0˚C to +70˚C
L
H
X
Open
VID ≤ −7 mV
TA = 0˚C to +70˚C
L
H
L
Open
L = Low logic state
H = High logic state
Open = TRI-STATE
X = Indeterminate state
DS007528-1
Top View
Order Number DS1651J, DS3651J or DS3651N
See NS Package Number J16A or N16A
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS007528
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DS1651/DS3651 Quad High Speed MOS Sense Amplifiers
June 1999
Typical Applications
A Typical MOS Memory Sensing Application for a 4k work by 4-bit
Memory Arrangement Employing 1103 Type Memory Devices
DS007528-2
Note: Only 4 devices are required for a 4k word by 16-bit memory system.
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2
Absolute Maximum Ratings (Note 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
DS1651
DS3651
Supply Voltage (VEE)
DS1651
DS3651
Operating Temperature (TA)
DS1651
DS3651
Output Load Current, (IOL)
Differential Mode Input
Voltage Range, (VIDR)
Common-Mode Input
Voltage Range, (VICR)
Input Voltage Range
(Any Input to GND), (VIR)
Power Supply Voltages
+7 VDC
VCC
VEE
−7 VDC
Differential-Mode Input Signal Voltage
± 6 VDC
Range, VIDR
Common-Mode Input Voltage Range,
± 5 VDC
VICR
Strobe Input Voltage, VI(S)
5.5 VDC
Strobe Temperature Range
−65˚C to +150˚C
Maximum Power Dissipation (Note 1) at 25˚C
Cavity Package
1509 mW
Molded Package
1476 mW
Lead Temp. (Soldering, 10 seconds)
300˚C
Min
Max
Unit
4.5
4.75
5.5
5.25
V
V
−4.5
−4.75
−5.5
−5.25
V
V
−55
0
+125
+70
16
˚C
˚C
mA
−5.0
+5.0
V
−3.0
+3.0
V
−5.0
+3.0
V
Electrical Characteristics
VCC = 5 VDC, VEE = −5 VDC, Min ≤ TA ≤ Max, unless otherwise noted (Notes 3, 4)
Symbol
VIS
Parameter
Input Sensitivity (Note 6)
(Common-Mode Voltage
Range)
VICR = −3V ≤ VIN ≤ +3V
Conditions
Min
Typ
Min ≤ VCC ≤ Max
Min ≥ VEE ≥ Max
VIO
Input Offset Voltage
IIB
Input Bias Current
IIO
Input Offset Current
VIL(S)
Strobe Input Voltage
(Low State)
VIH(S)
Strobe Input Voltage
(High State)
IIL(S)
Strobe Current (Low State)
VCC = Max, VEE = Max, VIN = 0.4V
IIL(S)
Strobe Current (High State)
VCC = Max,
VEE = Max
Max
Unit
± 7.0
mV
2
VCC = Max, VEE = Max
mV
20
0.5
µA
0.8
2
VIN = 2.4V
−1.6
DS3651
DS1651
VIN = VCC
VOH
Output Voltage (High States)
VCC = Min,
VEE = Min
IO = −400 µA
VOL
Output Voltage (Low State)
VCC = Min,
VEE = Min
IO = 16 mA
DS1651/DS3651
V
V
VIN = VCC
VIN = 2.4V
µA
mA
40
µA
1
mA
100
µA
1
mA
2.4
V
DS3651
0.45
DS1651
0.50
IOS
Output Current Short Circuit
VCC = Max, VEE = Max, (Note 5)
DS1651/DS3651
IOFF
Output Disable Leakage
Current
VCC = Max, VEE = Max
DS3651
40
µA
DS1651
100
µA
ICC
High Logic Level Supply
Current
VCC = Max, VEE = Max
45
60
mA
IEE
High Logic Level Supply
Current
VCC = Max, VEE = Max
−17
−30
mA
3
−18
−70
V
mA
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Switching Characteristics
VCC = 5 VDC, VEE = −5 VDC, TA = 25˚C unless otherwise noted.
Typ
Max
Units
tPHL(D)
Symbol
High-to-Low Logic Level Propagation
Delay Time (Differential Inputs)
Parameter
5 mV + VIS,
(Figure 2)
Conditions
DS1651/
DS3651
Min
23
45
ns
tPLH(D)
Low-to-High Logic Level Propagation
Delay Time (Differential Inputs)
5 mV + VIS,
(Figure 2)
DS1651/
DS3651
22
55
ns
tPOH(S)
TRI-STATE to High Logic Level
Propagation Delay Time (Strobe)
(Figure 1)
DS1651/
DS3651
16
21
ns
tPHO(S)
High Logic Level to TRI-STATE
Propagation Delay Time (Strobe)
(Figure 1)
DS1651/
DS3651
7
18
ns
tPOL(S)
TRI-STATE to Low Logic Level
Propagation Delay Time (Strobe)
(Figure 1)
DS1651/
DS3651
19
27
ns
tPLO(S)
Low Logic Level to TRI-STATE
Propagation Delay Time (Strobe)
(Figure 1)
DS1651/
DS3651
14
29
ns
Note 1: Derate cavity package 10.1 mW/˚C above 25˚C; derate molded package 11.8 mW/˚C above 25˚C.
Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they
are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 3: Unless otherwise specified min/max limits apply across the 0˚C to +70˚C range for the DS3651 and across the −55˚C to +125˚C range for the DS1651. All
typical values are for TA = 25˚C, VCC = 5V and VEE = −5V.
Note 4: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 5: Only one output at a time should be shorted.
Note 6: A parameter which is of primary concern when designing with sense amplifiers is, what is the minimum differential input voltage required at the sense amplifier input terminals to guarantee a given output logic state. This parameter is commonly referred to as threshold voltage. It is well known that design considerations
of threshold voltage are plagued by input offset currents, bias currents, network source resistances, and voltage gain. As a design convenience, the DS1651 and
DS3651 are specified to a parameter called input sensitivity (VIS). This parameter takes into consideration input offset currents and bias currents, and guarantees
a minimum input differential voltage to cause a given output logic state with respect to a maximum source impedance of 200Ω at each input.
Switching Time Waveform
DS007528-3
Note: Output of channel B shown under test, other channels are tested similarly.
Delay
V1
V2
S1
S2
CL
tPLO(S))
100 mV
GND
Closed
Closed
15 pF
50 pF
tPOL(S)
100 mV
GND
Closed
Open
tPHO(S)
GND
100 mV
Closed
Closed
15 pF
tPOH(S)
GND
100 mV
Open
Closed
50 pF
CL includes jig and probe capacitance.
EIN waveform characteristics: tTLH and tTHL ≤ 10 ns measured 10% to 90%
PRR = 1 MHz
Duty cycle = 50%
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4
AC Test Circuits
tPLO(S)
tPHO(S)
DS007528-5
DS007528-4
tPOH(S)
tPOL(S)
DS007528-7
DS007528-6
FIGURE 1. Strobe Propagation Delay tPLO(S), tPOL(S), tPHL(S) and tPOH(S)
DS007528-8
Note: Output of channel B shown under test, other channels are tested similarly.
S1 at “B” for DS1651/DS3651, CL = 50 pF total for DS1651/DS3651.
DS007528-9
EIN waveform characteristics:
tTLH and tTHL ≤ 10 ns measured 10% to 90%
PRR = 1 MHz, duty cycle = 500 ns
FIGURE 2. Differential Input Propagation Delay tPLH(D) and tPHL(D)
5
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Schematic Diagrams
DS1651/DS3651
DS007528-10
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6
Typical Applications
Level Detector with Hysteresis
Transfer Characteristics
and Equations for
Level Detector with Hysteresis
DS007528-11
DS007528-12
7
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Typical Applications
(Continued)
4-Bit Parallel A/D Converter
DS007528-14
20 = (A + B) (C + D) (E + F) (H + J) (K + L) (M + N) (P + R) (S)
21 = (B + D) (F + J) (L + N) (R)
22 = (D + J) (N)
23 = J
Conversion time ) 50 ns
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8
Physical Dimensions
inches (millimeters) unless otherwise noted
Ceramic Dual-in-Line Package (J)
Order Number DS1651J, DS1653J, DS3651J or DS3653J
NS Package Number J16A
Molded Dual-in-Line Package (N)
Order Number DS3651N or DS3653N
NS Package Number N16A
9
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DS1651/DS3651 Quad High Speed MOS Sense Amplifiers
Notes
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