MOTOROLA DSPA56011 24-bit dvd digital signal processor Datasheet

MOTOROLA
Order this document by:
DSP56011/D
SEMICONDUCTOR TECHNICAL DATA
DSP56011
Advance Information
24-BIT DVD DIGITAL SIGNAL PROCESSOR
8
15
Parallel
Host
Interface
(HI)
Serial
Audio
Interface
(SAI)
General
Purpose
I/O
(GPIO)
PR
Internal
Data
Bus
Switch
OnCETM Port
Clock
PLL Gen.
Program
Interrupt
Controller
4
3
EXTAL
Serial
Host
Interface
(SHI)
16-Bit Bus
24-Bit Bus
2
Digital
Audio
Transmitter
(DAX)
Address
Generation
Unit
EL
24-Bit
DSP56000
Core
5
9
IM
Expansion
Area
IN
AR
Y
The DSP56011 is a high-performance programmable Digital Signal Processor (DSP) developed
for Digital Versatile Disc (DVD), High-Definition Television (HDTV), and Advanced Set-top
audio decoding. The DSP56011 is optimized with audio-specific peripherals and customized
memory configuration, and may be programmed with Motorola’s certified software for Dolby
AC-3 5.1 Channel Surround, Dolby Pro Logic, and MPEG1 Layer 2. These applications use
Motorola’s 24-bit DSP56000 architecture and are the highest quality solutions available. Flexible
peripheral modules and interface software allow simple connection to a wide variety of video/
system decoders. In addition, the DSP56011 offers switchable memory space configuration, a
large user-definable Program ROM and two independent data RAMs and ROMs, a Serial Audio
Interface (SAI), Serial Host Interface (SHI), Parallel Host Interface (HI) with Direct Memory
Access (DMA) for communicating with other processors, dedicated I/O lines, on-chip Phase
Lock Loop (PLL), On-Chip Emulation (OnCE™) port, and on-chip Digital Audio Transmitter
(DAX). Figure 1 shows the functional blocks of the DSP56011.
Program
Memory
X Data
Memory
Y Data
Memory
PAB
XAB
YAB
GDB
PDB
XDB
YDB
Program
Program
Decode
Address
Controller
Generator
Program Control Unit
Data ALU
24 × 24 + 56 → 56-Bit MAC
Two 56-Bit Accumulators
4
IRQA, IRQB, NMI, RESET
Figure 1 DSP56011 Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preliminary Information
Rev. 1
© MOTOROLA, INC. 1996, 1997
AA1271
DSP56011
TABLE OF CONTENTS
SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 1-1
SECTION 2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
SECTION 3
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
SECTION 4
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
SECTION 5
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
AR
Y
SECTION 1
FOR TECHNICAL ASSISTANCE:
1-800-521-6274
Email:
[email protected]
http://www.motorola-dsp.com
IM
Internet:
IN
Telephone:
Data Sheet Conventions
This data sheet uses the following conventions:
Used to indicate a signal that is active when pulled low (For example, the RESET
pin is active when low.)
EL
OVERBAR
Means that a high true (active high) signal is high or that a low true (active low)
signal is low
“deasserted”
Means that a high true (active high) signal is low or that a low true (active low)
signal is high
PR
“asserted”
Examples:
Note:
Signal/Symbol
Logic State
Signal State
Voltage
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
Preliminary Information
ii
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
DSP56011
Features
FEATURES
Digital Signal Processing Core
Efficient, object-code compatible, 24-bit DSP56000 family DSP engine
47.5 Million Instructions Per Second (MIPS) with 21.05 ns instruction cycle at 95 MHz
–
Highly parallel instruction set with unique DSP addressing modes
–
Two 56-bit accumulators including extension byte
–
Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
–
Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles
–
56-bit addition/subtraction in 1 instruction cycle
–
Fractional and integer arithmetic with support for multi-precision arithmetic
–
Hardware support for block-floating point Fast Fourier Transforms (FFT)
–
Hardware nested DO loops
–
Zero-overhead fast interrupts (2 instruction cycles)
–
PLL-based clocking with a wide range of frequency multiplications (1 to 4096) and
power saving clock divider (2i : i = 0 to 15), which reduces clock noise
–
Four 24-bit internal data buses and three 16-bit internal address buses for
simultaneous accesses to one program and two data memories
IM
IN
AR
Y
–
PR
EL
•
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
iii
DSP56011
Features
Memory
Modified Harvard architecture allows simultaneous access to program and data
memories
•
12800 × 24-bit on-chip Program ROM1
•
4096 × 24-bit on-chip X-data RAM and 3584 × 24-bit on-chip X-data ROM1
•
4352 × 24-bit on-chip Y-data RAM and 2048 × 24-bit on-chip Y-data ROM1
•
512 × 24-bit on-chip Program RAM and 64 × 24-bit bootstrap ROM
•
As much as 2304 × 24 bits of X- and Y-data RAM can be switched to Program RAM,
giving a total of 2816 × 24 bits of Program RAM
AR
Y
•
Table 1 lists the memory configurations of the DSP56011.
Table 1 DSP56011 Internal Memory Configurations
No Switch
(PEA = 0, PEB = 0)
Switch A
(PEA = 1, PEB = 0)
Switch B
(PEA = 0, PEB = 1)
Switch A+B
(PEA = 1, PEB = 1)
Program RAM
0.5 K
1.25 K
2.0 K
2.75 K
X data RAM
4.0 K
3.25 K
3.25 K
2.5 K
Program ROM
X data ROM
4.25 K
4.25 K
3.5 K
3.5 K
12.5 K
12.5 K
12.5 K
12.5 K
3.5 K
3.5 K
3.5 K
3.5 K
2.0 K
2.0 K
2.0 K
2.0 K
PR
EL
Y data ROM
IM
Y data RAM
IN
Memory Type
1.These ROMs may be factory programmed with data/program provided by the application developer.
Preliminary Information
iv
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
DSP56011
Features
Peripheral and Support Circuits
–
Two receivers and three transmitters
–
Master or slave capability
–
I2S, Sony, and Matshushita audio protocol implementations
–
Two sets of SAI interrupt vectors
Y
•
SAI includes:
SHI features:
AR
•
–
Single master capability
–
SPI and I2C protocols
–
10-word receive FIFO
–
Support for 8-, 16- and 24-bit words.
Byte-wide Parallel Host Interface with DMA support capable of reconfiguration as fifteen
General Purpose Input/Output (GPIO) lines
•
DAX features one serial transmitter capable of supporting S/PDIF, IEC958, CP-340, and
AES/EBU formats.
•
Eight dedicated, independent, programmable GPIO lines
•
On-chip peripheral registers memory mapped in data memory space
•
OnCE port for unobtrusive, processor speed-independent debugging
•
Software programmable PLL-based frequency synthesizer for the core clock
•
Power saving Wait and Stop modes
EL
IM
IN
•
Fully static, HCMOS design from specified operating frequency down to dc
•
100-pin plastic Thin Quad Flat Pack (TQFP) surface-mount package
•
5 V power supply
PR
•
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
v
DSP56011
Documentation
DOCUMENTATION
Table 2 lists the documents that provide a complete description of the DSP56011 and are
required to design properly with the part. Documentation is available from a local Motorola
distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or
through the Motorola DSP home page on the Internet (the source for the latest information).
Document Name
Description
Y
Table 2 Additional DSP56011 Documentation
Order Number
Detailed description of the 56000-family architecture
and the 24-bit core processor and instruction set
DSP56KFAMUM/AD
DSP56011 User’s
Manual
Detailed description of memory, peripherals, and
interfaces
DSP56011UM/AD
DSP56011
Technical Data
Electrical and timing specifications, and pin and
package descriptions
DSP56011/D
PR
EL
IM
IN
AR
DSP56000 Family
Manual
Preliminary Information
vi
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
SECTION
1
Y
SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
AR
The input and output signals of the DSP56011 are organized into ten functional
groups, as shown in Table 1-1 and as illustrated in Figure 1-1.
Table 1-1 DSP56011 Functional Signal Groupings
Power (VCC)
Number of
Signals
IN
Functional Group
Detailed
Description
13
Table 1-2
17
Table 1-3
4
Table 1-4
4
Table 1-5
15
Table 1-6
Serial Host Interface (SHI)
5
Table 1-7
Serial Audio Interface (SAI)
9
Table 1-8
Table 1-9
General Purpose Input/Output (GPIO)
8
Table 1-10
Digital Audio Transmitter (DAX)
2
Table 1-11
OnCE Port
4
Table 1-12
Ground (GND)
PLL
IM
Interrupt and Mode Control
Port B
EL
Host Interface (HI)
PR
Figure 1-1 is a diagram of DSP56011 signals by functional group.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
1-1
Signal/Connection Descriptions
Signal Groupings
DSP56011
PLOCK
PCAP
PINIT
EXTAL
Grounds:
PLL
Internal Logic
A
D
HI
SHI
PLL
8
Serial Host
Interface (SHI)
IM
General Purpose
Input/Output (GPIO)
PR
EL
Interrupt/
Mode
Control
Port B GPIO
PB0–PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
SPI Mode
MOSI
SS
MISO
SCK
HREQ
I2C Mode
HA0
HA2
SDA
SCL
HREQ
WSR
SCKR
SDI0
SDI1
WST
SCKT
SDO0
SDO1
SDO2
Serial Audio
Interface (SAI)
Rec0
Rec1
Tran0
Tran1
Tran2
MODA/IRQA
MODB/IRQB
MODC/NMI
RESET
HI
H0–H7
HOA0
HOA1
HOA2
HR/W
HEN
HOREQ
HACK
Y
4
3
2
4
3
Host
Interface
(HI) Port
AR
GNDP
GNDQ
GNDA
GNDD
GNDH
GNDS
4
2
1
3
2
Power Inputs:
PLL
Internal Logic
A
D
HI
SHI
IN
VCCP
VCCQ
VCCA
VCCD
VCCH
VCCS
Digital Audio
Transmitter (DAX)
OnCE™
Port
8
GPIO0–GPIO7
ADO
ACI
Debug
DSI
DSCK
DSO
DR
Non-Debug
OS0
OS1
DSO
DR
Figure 1-1 Signals Identified by Functional Group
Preliminary Information
1-2
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Signal/Connection Descriptions
Power
POWER
Table 1-2 Power Inputs
Power Name
Description
PLL Power—VCCP is VCC dedicated for Phase Lock Loop (PLL) use. The voltage
should be well-regulated and the input should be provided with an extremely
low impedance path to the VCC power rail. VCCP should be bypassed to GNDP
by a 0.1 µF capacitor located as close as possible to the chip package.
VCCQ
Quiet Power—VCCQ is an isolated power for the internal processing logic. This
input must be tied externally to all other chip power inputs. The user must
provide adequate external decoupling capacitors.
VCCA
A Power—VCCA is an isolated power for sections of the internal chip logic. This
input must be tied externally to all other chip power inputs. The user must
provide adequate external decoupling capacitors.
VCCD
D Power—VCCD is an isolated power for sections of the internal chip logic. This
input must be tied externally to all other chip power inputs. The user must
provide adequate external decoupling capacitors.
VCCH
Host Power—VCCH is an isolated power for the HI I/O drivers. This input must
be tied externally to all other chip power inputs. The user must provide adequate
external decoupling capacitors.
VCCS
Serial Host Power—VCCS is an isolated power for the SHI I/O drivers. This
input must be tied externally to all other chip power inputs. The user must
provide adequate external decoupling capacitors.
PR
EL
IM
IN
AR
Y
VCCP
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
1-3
Signal/Connection Descriptions
Ground
GROUND
Table 1-3 Grounds
Ground Name
Description
PLL Ground—GNDP is ground dedicated for PLL use. The connection should be
provided with an extremely low-impedance path to ground. VCCP should be
bypassed to GNDP by a 0.1 µF capacitor located as close as possible to the chip
package.
GNDQ
Internal Logic Ground—GNDQ is an isolated ground for the internal processing
logic. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
GNDA
A Ground—GNDA is an isolated ground for sections of the internal logic. This
connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
GNDD
D Ground—GNDD is an isolated ground for sections of the internal logic. This
connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
GNDH
Host Ground—GNDH is an isolated ground for the HI I/O drivers. This
connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
GNDS
Serial Host Ground—GNDS is an isolated ground for the SHI I/O drivers. This
connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
PR
EL
IM
IN
AR
Y
GNDP
Preliminary Information
1-4
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Signal/Connection Descriptions
Phase Lock Loop (PLL)
PHASE LOCK LOOP (PLL)
Table 1-4 Phase Lock Loop Signals
Signal Name
State During
Reset
Output
Indeterminate
Signal Description
Phase Locked—PLOCK is an output signal that, when
driven high, indicates that the PLL has achieved phase
lock. After Reset, PLOCK is driven low until lock is
achieved.
AR
Y
PLOCK
Type
Note:
Input
Input
PLL Capacitor—PCAP is an input connecting an off-chip
capacitor to the PLL filter. Connect one capacitor
terminal to PCAP and the other terminal to VCCP.
IN
PCAP
PLOCK is a reliable indicator of the PLL lock
state only after the chip has exited the Reset
state. During hardware reset, the PLOCK state is
determined by PINIT and the current PLL lock
condition.
If the PLL is not used, PCAP may be tied to VCC, GND,
or left floating.
Input
PLL Initial—During assertion of RESET, the value of
PINIT is written into the PLL Enable (PEN) bit of the PLL
Control Register, determining whether the PLL is
enabled or disabled.
Input
Input
External Clock/Crystal Input—EXTAL interfaces the
internal crystal oscillator input to an external crystal or
an external clock.
PR
EL
EXTAL
Input
IM
PINIT
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
1-5
Signal/Connection Descriptions
Interrupt and Mode Control
INTERRUPT AND MODE CONTROL
Table 1-5 Interrupt and Mode Control
MODA
Input
State During
Reset
Signal Description
Input (MODA) Mode Select A—This input signal has three functions:
•
•
•
Y
Type
to work with the MODB and MODC signals to
select the DSP’s initial operating mode,
to allow an external device to request a DSP
interrupt after internal synchronization, and
to turn on the internal clock generator when the
DSP is in the Stop processing state, causing the DSP
to resume processing.
AR
Signal
Name
Input
PR
EL
IRQA
IM
IN
MODA is read and internally latched in the DSP when the
processor exits the Reset state. The logic state present on the
MODA, MODB, and MODC pins selects the initial DSP
operating mode. Several clock cycles after leaving the Reset
state, the MODA signal changes to the external interrupt
request IRQA. The DSP operating mode can be changed by
software after reset.
External Interrupt Request A (IRQA)—The IRQA input is a
synchronized external interrupt request. It may be
programmed to be level-sensitive or negative-edge
triggered. When the signal is edge-triggered, triggering
occurs at a voltage level and is not directly related to the fall
time of the interrupt signal. However, as the fall time of the
interrupt signal increases, the probability that noise on
IRQA will generate multiple interrupts also increases.
While the DSP is in the Stop mode, asserting IRQA gates on
the oscillator and, after a clock stabilization delay, enables
clocks to the processor and peripherals. Hardware reset
causes this input to function as MODA.
Preliminary Information
1-6
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Signal/Connection Descriptions
Interrupt and Mode Control
Table 1-5 Interrupt and Mode Control (Continued)
MODB
Type
Input
State During
Reset
Signal Description
Input (MODB) Mode Select B—This input signal has two functions:
•
•
to work with the MODA and MODC signals to
select the DSP’s initial operating mode, and
to allow an external device to request a DSP
interrupt after internal synchronization.
Y
Signal
Name
Input
External Interrupt Request B (IRQB)—The IRQB input is a
synchronized external interrupt request. It may be
programmed to be level-sensitive or negative-edge
triggered. When the signal is edge-triggered, triggering
occurs at a voltage level and is not directly related to the fall
time of the interrupt signal. However, as the fall time of the
interrupt signal increases, the probability that noise on IRQB
will generate multiple interrupts also increases. Hardware
reset causes this input to function as MODB.
PR
EL
IM
IRQB
IN
AR
MODB is read and internally latched in the DSP when the
processor exits the Reset state. The logic state present on the
MODA, MODB, and MODC pins selects the initial DSP
operating mode. Several clock cycles after leaving the Reset
state, the MODB signal changes to the external interrupt
request IRQB. The DSP operating mode can be changed by
software after reset.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
1-7
Signal/Connection Descriptions
Interrupt and Mode Control
Table 1-5 Interrupt and Mode Control (Continued)
MODC
Type
Input, edgetriggered
State During
Reset
Signal Description
Input (MODC) Mode Select C—This input signal has two functions:
•
•
to work with the MODA and MODB signals to
select the DSP’s initial operating mode, and
to allow an external device to request a DSP
interrupt after internal synchronization.
Y
Signal
Name
Input
Active
PR
EL
RESET
Non-Maskable Interrupt Request—The NMI input is a
negative-edge triggered external interrupt request. This is a
level 3 interrupt that can not be masked out. Triggering
occurs at a voltage level and is not directly related to the fall
time of the interrupt signal. However, as the fall time of the
interrupt signal increases, the probability that noise on NMI
will generate multiple interrupts also increases. Hardware
reset causes this input to function as MODC.
Input, edgetriggered
IM
NMI
IN
AR
MODC is read and internally latched in the DSP when the
processor exits the Reset state. The logic state present on the
MODA, MODB, and MODC pins selects the initial DSP
operating mode. Several clock cycles after leaving the Reset
state, the MODC signal changes to the Non-Maskable
Interrupt request, NMI. The DSP operating mode can be
changed by software after reset.
Reset—This input causes a direct hardware reset of the
processor. When RESET is asserted, the DSP is initialized and
placed in the Reset state. A Schmitt-trigger input is used for
noise immunity. When the reset signal is deasserted, the initial
DSP operating mode is latched from the MODA, MODB, and
MODC signals. The DSP also samples the PINIT signal and
writes its status into the PEN bit of the PLL Control Register.
When the DSP comes out of the Reset state, deassertion
occurs at a voltage level and is not directly related to the rise
time of the RESET signal. However, the probability that
noise on RESET will generate multiple resets increases with
increasing rise time of the RESET signal.
For proper hardware reset to occur, the clock must be active,
since a number of clock ticks are required for proper
propagation of the hardware Reset state.
Preliminary Information
1-8
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Signal/Connection Descriptions
Host Interface (HI)
HOST INTERFACE (HI)
Table 1-6 Host Interface
H0–H7
Type
Input/
Output
State During
Reset
Signal Description
AR
Signal Name
Y
The HI provides a fast parallel data to 8-bit port, which may be connected directly to
the host bus. The HI supports a variety of standard buses, and can be directly
connected to a number of industry standard microcomputers, microprocessors, DSPs,
and DMA hardware.
Input
Host Data Bus (H0–H7)—This data bus transfers data
between the host processor and the DSP56011.
IN
When configured as a Host Interface port, the H0–H7
signals are tri-stated as long as HEN is deasserted. The
signals are inputs unless HR/W is high and HEN is
asserted, in which case H0–H7 become outputs, allowing
the host processor to read the DSP56011 data. H0–H7
become outputs when HACK is asserted during HOREQ
assertion.
Port B GPIO 0–7 (PB0–PB7)—These signals are General
Purpose I/O signals (PB0–PB7) when the Host Interface is
not selected.
IM
PB0–PB7
After reset, the default state for these signals is GPIO input.
Input
Input
EL
HOA0–HOA2
Input/
Output
PR
PB8–PB10
Host Address0–Host Address 2 (HOA0–HOA2)—These
inputs provide the address selection for each Host
Interface register.
Port B GPIO 8–10 (PB8–PB10)—These signals are General
Purpose I/O signals (PB8–PB10) when the Host Interface is
not selected.
After reset, the default state for these signals is GPIO
input.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
1-9
Signal/Connection Descriptions
Host Interface (HI)
Table 1-6 Host Interface (Continued)
PB11
State During
Reset
Input
Input
Signal Description
Host Read/Write—This input selects the direction of data
transfer for each host processor access. If HR/W is high
and HEN is asserted, H0–H7 are outputs and DSP data is
transferred to the host processor. If HR/W is low and HEN
is asserted, H0–H7 are inputs and host data is transferred
to the DSP. HR/W must be stable when HEN is asserted.
Y
HR/W
Type
Input/
Output
Port B GPIO 11 (PB11)—This signal is a General Purpose
I/O signal (PB11) when the Host Interface is not being
used.
AR
Signal Name
After reset, the default state for this signal is GPIO input.
Input
Input
Host Enable—This input enables a data transfer on the
host data bus. When HEN is asserted and HR/W is high,
H0–H7 become outputs and the host processor may read
DSP56011 data. When HEN is asserted and HR/W is low,
H0–H7 become inputs. Host data is latched inside the DSP
on the rising edge of HEN. Normally, a chip select signal
derived from host address decoding and an enable strobe
are used to generate HEN.
PB12
IM
IN
HEN
Input/
Output
Port B GPIO 12 (PB12)—This signal is a General Purpose
I/O signal (PB12) when the Host Interface is not being
used.
After reset, the default state for this signal is GPIO input.
Opendrain
Output
Input
PR
EL
HOREQ
PB13
Input/
Output
Host Request—This signal is used by the Host Interface to
request service from the host processor, DMA controller,
or a simple external controller.
Note:
HOREQ should always be pulled high when it is
not in use.
Port B GPIO 13 (PB13)—This signal is a General Purpose
(not open-drain) I/O signal (PB13) when the Host
Interface is not selected.
After reset, the default state for this signal is GPIO input.
Preliminary Information
1-10
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Signal/Connection Descriptions
Host Interface (HI)
Table 1-6 Host Interface (Continued)
HACK
Type
State During
Reset
Input
Input
Signal Description
Host Acknowledge—This input has two functions. It
provides a host acknowledge handshake signal for DMA
transfers and it receives a host interrupt acknowledge
compatible with MC68000 Family processors.
PB14
HACK should always be pulled high when it is
not in use.
AR
Note:
Y
Signal Name
Input/
Output
Port B GPIO 14 (PB14)—This signal is a General Purpose
I/O signal (PB14) when the Host Interface is not selected.
PR
EL
IM
IN
After reset, the default state for this signal is GPIO input.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
1-11
Signal/Connection Descriptions
Serial Host Interface (SHI)
SERIAL HOST INTERFACE (SHI)
The SHI has five I/O signals that can be configured to allow the SHI to operate in
either SPI or I2C mode.
Table 1-7 Serial Host Interface (SHI) Signals
Input or
Output
SCL
Input or
Output
Signal Description
Tri-stated
SPI Serial Clock—The SCK signal is an output when the SPI
is configured as a master, and a Schmitt-trigger input when
the SPI is configured as a slave. When the SPI is configured as
a master, the SCK signal is derived from the internal SHI
clock generator. When the SPI is configured as a slave, the
SCK signal is an input, and the clock signal from the external
master synchronizes the data transfer. The SCK signal is
ignored by the SPI if it is defined as a slave and the Slave
Select (SS) signal is not asserted. In both the master and slave
SPI devices, data is shifted on one edge of the SCK signal and
is sampled on the opposite edge where data is stable. Edge
polarity is determined by the SPI transfer protocol. The
maximum allowed internally generated bit clock frequency is
fosc/4 for the SPI mode, where fosc is the clock on EXTAL.
The maximum allowed externally generated bit clock
frequency is fosc/3 for the SPI mode.
IM
IN
SCK
State
during
Reset
Y
Signal
Type
AR
Signal
Name
PR
EL
I2C Serial Clock—SCL carries the clock for I2C bus
transactions in the I2C mode. SCL is a Schmitt-trigger input
when configured as a slave, and an open-drain output when
configured as a master. SCL should be connected to VCC
through a pull-up resistor. The maximum allowed internally
generated bit clock frequency is fosc/6 for the I2C mode
where fosc is the clock on EXTAL. The maximum allowed
externally generated bit clock frequency is fosc/5 for the I2C
mode.
An external pull-up resistor is not required.
Preliminary Information
1-12
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Signal/Connection Descriptions
Serial Host Interface (SHI)
Table 1-7 Serial Host Interface (SHI) Signals (Continued)
Signal
Name
Signal
Type
Input or
Output
SDA
Input or
opendrain
Output
MOSI
Input or
Output
Signal Description
Tri-stated
SPI Master-In-Slave-Out—When the SPI is configured as a
master, MISO is the master data input line. The MISO signal
is used in conjunction with the MOSI signal for transmitting
and receiving serial data. This signal is a Schmitt-trigger
input when configured for the SPI Master mode, an output
when configured for the SPI Slave mode, and tri-stated if
configured for the SPI Slave mode when SS is deasserted. An
external pull-up resistor is not required for SPI operation.
AR
Y
MISO
State
during
Reset
IM
IN
I2C Data and Acknowledge—In I2C mode, SDA is a Schmitttrigger input when receiving and an open-drain output when
transmitting. SDA should be connected to VCC through a
pull-up resistor. SDA carries the data for I2C transactions.
The data in SDA must be stable during the high period of
SCL. The data in SDA is only allowed to change when SCL is
low. When the bus is free, SDA is high. The SDA line is only
allowed to change during the time SCL is high in the case of
start and stop events. A high to low transition of the SDA line
while SCL is high is an unique situation, which is defined as
the start event. A low to high transition of SDA while SCL is
high is an unique situation, which is defined as the stop
event.
SPI Master-Out-Slave-In—When the SPI is configured as a
master, MOSI is the master data output line. The MOSI signal
is used in conjunction with the MISO signal for transmitting
and receiving serial data. MOSI is the slave data input line
when the SPI is configured as a slave. This signal is a Schmitttrigger input when configured for the SPI Slave mode.
EL
Tri-stated
Input
PR
HA0
I2C Slave Address 0—This signal uses a Schmitt-trigger
input when configured for the I2C mode. When configured
for I2C Slave mode, the HA0 signal is used to form the slave
device address. HA0 is ignored when it is configured for the
I2C Master mode.
An external pull-up resistor is not required.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
1-13
Signal/Connection Descriptions
Serial Host Interface (SHI)
Table 1-7 Serial Host Interface (SHI) Signals (Continued)
Signal
Name
Signal
Type
Input
HA2
Input
Signal Description
Tri-stated
SPI Slave Select—This signal is an active low Schmitt-trigger
input when configured for the SPI mode. When configured
for the SPI Slave mode, this signal is used to enable the SPI
slave for transfer. When configured for the SPI Master mode,
this signal should be kept deasserted (pulled high). If it is
asserted while configured as SPI master, a bus error
condition is flagged.
AR
Y
SS
State
during
Reset
IN
I2C Slave Address 2—This signal uses a Schmitt-trigger
input when configured for the I2C mode. When configured
for the I2C Slave mode, the HA2 signal is used to form the
slave device address. HA2 is ignored in the I2C Master mode.
If SS is deasserted, the SHI ignores SCK clocks and keeps the
MISO output signal in the high-impedance state.
This signal is tri-stated during hardware, software, or
individual reset (thus, there is no need for an external pull-up
in this state).
Input or
Output
Tri-stated
Host Request—This signal is an active low Schmitt-trigger
input when configured for the Master mode, but an active
low output when configured for the Slave mode.
IM
HREQ
PR
EL
When configured for the Slave mode, HREQ is asserted to
indicate that the SHI is ready for the next data word transfer
and deasserted at the first clock pulse of the new data word
transfer. When configured for the Master mode, HREQ is an
input and when asserted by the external slave device, it will
trigger the start of the data word transfer by the master. After
finishing the data word transfer, the master will await the
next assertion of HREQ to proceed to the next transfer.
This signal is tri-stated during hardware, software, personal
reset, or when the HREQ1–HREQ0 bits in the HCSR are
cleared (no need for external pull-up in this state).
Preliminary Information
1-14
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Signal/Connection Descriptions
Serial Audio Interface (SAI)
SERIAL AUDIO INTERFACE (SAI)
The SAI is composed of separate receiver and transmitter sections.
Y
SAI Receive Section
The receive section of the SAI has four dedicated signals.
SDI0
Signal
Type
Input
State
during
Reset
Tristated
Signal Description
Serial Data Input 0—This is the receiver 0 serial data input.
IN
Signal
Name
AR
Table 1-8 Serial Audio Interface (SAI) Receive Signals
This signal is high impedance during hardware or software
reset, while receiver 0 is disabled (R0EN = 0), or while the chip
is in the Stop state. No external pull-up resistor is required.
SDI1
Input
Tristated
Serial Data Input 1—This is the receiver 1 serial data input.
Input or
Output
Tristated
Receive Serial Clock—SCKR is an output if the receiver
section is programmed as a master, and a Schmitt-trigger
input if programmed as a slave.
EL
SCKR
IM
This signal is high impedance during hardware or software
reset, while receiver 1 is disabled (R1EN = 0), or while the chip
is in the Stop state. No external pull-up resistor is required.
SCKR is high impedance if all receivers are disabled (personal
reset) and during hardware or software reset, or while the chip
is in the Stop state. No external pull-up is necessary.
Input or
Output
PR
WSR
Tristated
Receive Word Select—WSR is an output if the receiver section
is programmed as a master, and a Schmitt-trigger input if
programmed as a slave. WSR is used to synchronize the data
word and to select the left/right portion of the data sample.
WSR is high impedance if all receivers are disabled (personal
reset), during hardware reset, during software reset, or while
the chip is in the stop state. No external pull-up is necessary.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
1-15
Signal/Connection Descriptions
Serial Audio Interface (SAI)
SAI Transmit Section
The transmit section of the SAI has five dedicated signals.
Table 1-9 Serial Audio Interface (SAI) Transmit Signals
Signal
Type
State
during
Reset
Signal Description
Y
Signal
Name
Output
Driven
high
Serial Data Output 0—SDO0 is the transmitter 0 serial output.
SDO0 is driven high if transmitter 0 is disabled, during
personal reset, hardware reset and software reset, or when the
chip is in the Stop state.
SDO1
Output
Driven
high
Serial Data Output 1—SDO1 is the transmitter 1 serial output.
SDO1 is driven high if transmitter 1 is disabled, during
personal reset, hardware reset and software reset, or when the
chip is in the Stop state.
SDO2
Output
Driven
high
SCKT
Input
or
Output
Tristated
IN
AR
SDO0
Serial Data Output 2—SDO2 is the transmitter 2 serial output.
SDO2 is driven high if transmitter 2 is disabled, during
personal reset, hardware reset and software reset, or when the
chip is in the Stop state.
EL
IM
Transmit Serial Clock—This signal provides the clock for the
Serial Audio Interface (SAI). The SCKT signal can be an output
if the transmit section is programmed as a master, or a Schmitttrigger input if the transmit section is programmed as a slave.
When the SCKT is an output, it provides an internally
generated SAI transmit clock to external circuitry. When the
SCKT is an input, it allows external circuitry to clock data out
of the SAI.
PR
SCKT is tri-stated if all transmitters are disabled (personal
reset), during hardware reset, software reset, or while the chip
is in the Stop state. No external pull-up is necessary.
WST
Input
or
Output
Tristated
Transmit Word Select—WST is an output if the transmit
section is programmed as a master, and a Schmitt-trigger input
if programmed as a slave. WST is used to synchronize the data
word and select the left/right portion of the data sample.
WST is tri-stated if all transmitters are disabled (personal reset),
during hardware or software reset, or while the chip is in the
Stop state. No external pull-up is necessary.
Preliminary Information
1-16
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Signal/Connection Descriptions
General Purpose Input/Output (GPIO)
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
Table 1-10 General Purpose I/O (GPIO) Signals
Input or
Output
(standard or
open-drain)
State during
Reset
Disconnected
internally
Signal Description
General Purpose Input/Output—These signals
are used for control and handshake functions
between the DSP and external circuitry. Each
GPIO signal may be individually programmed to
be one of four states:
• Not connected
• Input
• Standard output
• Open-drain output
IN
AR
GPIO0–
GPIO7
Signal Type
Y
Signal
Name
DIGITAL AUDIO INTERFACE (DAX)
Table 1-11 Digital Audio Interface (DAX) Signals
State During
Reset
Output
Input
PR
ACI
Signal Description
Output, driven Digital Audio Data Output—This signal is an
high
audio and non-audio output in the form of AES/
EBU, CP340 and IEC958 data in a biphase mark
format. The signal is driven high when the DAX is
disabled, and during hardware or software reset.
EL
ADO
Type
IM
Signal Name
Tri-stated
Audio Clock Input—This is the DAX clock input.
When programmed to use an external clock, this
input supplies the DAX clock. The external clock
frequency must 256, 384, or 512 times the audio
sampling frequency (256 x Fs, 384 x Fs or 512 x Fs,
respectively). The ACI signal is high impedance
(tri-stated) only during hardware or software reset.
If the DAX is not used, connect the ACI signal to
ground through an external pull-down resistor to
ensure a stable logic level at the input.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
1-17
Signal/Connection Descriptions
OnCE Port
OnCE PORT
Table 1-12 On-Chip Emulation Port (OnCE) Signals
Input
OS0
Output
Low
Output
Signal Description
Debug Serial Input—In Debug mode, serial data or
commands are provided as inputs to the OnCE controller via
the DSI signal. Data is latched on the falling edge of the DSCK
serial clock. Data is always shifted into the OnCE serial port
Most Significant Bit (MSB) first. When switching from output
to input, the signal is tri-stated.
Y
DSI
State
during
Reset
AR
Signal
Type
Chip Status 0—When the chip is not in Debug mode, this signal
is an output that works with the OS1 signal to provide
information about the chip status.
IN
Signal
Name
Note:
Input
Low
Output
Debug Serial Clock—The DSCK signal is used in Debug mode
and supplies the serial input clock to the OnCE module to shift
data into and out of the OnCE serial port. (Data is clocked into
the OnCE port on the falling edge and is clocked out of the
OnCE serial port on the rising edge.) The debug serial clock
frequency must be no greater than 1/8 of the processor clock
frequency. When switching from input to output, the signal is
tri-stated.
EL
IM
DSCK
If the OnCE interface is in use, an external pull-down resistor
should be attached to this pin. If the OnCE interface is not in
use, the resistor is not required.
OS1
Output
Chip Status 1—When the chip is not in Debug mode, this signal
is an output that works with the OS0 signal to provide
information about the chip status.
PR
Note:
If the OnCE interface is in use, an external pull-down resistor
should be attached to this pin. If the OnCE interface is not in
use, the resistor is not required.
Preliminary Information
1-18
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Signal/Connection Descriptions
OnCE Port
Table 1-12 On-Chip Emulation Port (OnCE) Signals (Continued)
Signal
Name
Output
State
during
Reset
Pulled
high
Signal Description
Debug Serial Output—Data contained in one of the OnCE
controller registers is provided through the DSO output signal,
as specified by the last command received from the external
command controller. Data is always shifted out the OnCE
serial port MSB first. Data is clocked out of the OnCE serial
port on the rising edge of DSCK.
AR
Y
DSO
Signal
Type
Input
Debug Request—A Debug Request (DR) input from an
external command controller allows the user to enter the
Debug mode of operation. When DR is asserted, it causes the
DSP to finish the current instruction being executed, save the
instruction pipeline information, enter the Debug mode, and
wait for commands to be entered from the DSI line. While in
Debug mode, the DR signal lets the user reset the OnCE
controller by asserting it and deasserting it after receiving an
acknowledge signal.
IM
Input
EL
DR
IN
The DSO signal also provides acknowledge pulses to the
external command controller. When the chip enters the Debug
mode, the DSO signal will be pulsed low to indicate
(acknowledge) that the OnCE is waiting for commands. After
the OnCE receives a read command, the DSO signal is pulsed
low to indicate that the requested data is available and the
OnCE serial port is ready to receive clocks in order to deliver
the data. After the OnCE receives a write command, the DSO
signal is pulsed low to indicate that the OnCE serial port is
ready to receive the data to be written; after the data is written,
another acknowledge pulse is provided.
PR
Note:
It may be necessary to reset the OnCE controller in cases
where synchronization between the OnCE controller and
external circuitry is lost.
DR must be deasserted after the OnCE responds with an
acknowledge on the DSO signal and before sending the first
OnCE command. Asserting DR causes the chip to exit the Stop
or Wait state. Having DR asserted during the deassertion of
RESET causes the DSP to enter Debug mode.
Note:
If the OnCE interface is not in use, attach an external pull-up
resistor to the DR input.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
1-19
Signal/Connection Descriptions
PR
EL
IM
IN
AR
Y
OnCE Port
Preliminary Information
1-20
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
SECTION
2
Y
SPECIFICATIONS
INTRODUCTION
MAXIMUM RATINGS
IN
AR
The DSP56011 is fabricated in high density CMOS with Transistor-Transistor Logic
(TTL) compatible inputs and outputs. The DSP56011 specifications are preliminary
and are from design simulations, and may not be fully tested or guaranteed at this
early stage of the product life cycle. For design convenience, timings for 81 MHz and
95 MHz operation are included. Finalized specifications will be published after full
characterization and device qualifications are complete.
IM
CAUTION
PR
EL
This device contains circuitry protecting
against damage due to high static voltage or
electrical fields; however, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either GND or VCC).
Note: In the calculation of timing requirements, adding a maximum value of one
specification to a minimum value of another specification does not yield a
reasonable sum. A maximum specification is calculated using a worst case
variation of process parameter values in one direction. The minimum
specification is calculated using the worst case for the same parameters in the
opposite direction. Therefore, a “maximum” value for a specification will
never occur in the same device that has a “minimum” value for another
specification; adding a maximum to a minimum represents a condition that
can never exist.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-1
Specifications
Thermal characteristics
Table 2-1 Maximum Ratings
Rating1
Symbol
Value1, 2
Unit
Supply Voltage
VCC
V
All input voltages
VIN
−0.3 to +7.0
GND − 0.5 to VCC + 0.5
V
Current drain per pin excluding VCC and GND
I
10
mA
Operating temperature range
TJ
–40 to +105
˚C
˚C
1.
2.
GND = 0 V, VCC = 5.0 V ± 5%, TJ = –40°C to +105°C, CL = 50 pF + 2 TTL Loads
Absolute maximum ratings are stress ratings only, and functional operation at the maximum is
not guaranteed. Stress beyond the maximum rating may affect device reliability or cause
permanent damage to the device.
IN
THERMAL CHARACTERISTICS
AR
Notes:
−55 to +125
TSTG
Y
Storage temperature
Table 2-2 Thermal Characteristics
Characteristic
Symbol
TQFP Value
Unit
RθJA or θJA
47
˚C/W
Junction-to-case thermal resistance2
RθJC or θJC
5.8
˚C/W
Thermal characterization parameter
ΨJT
1.6
˚C/W
1.
Junction-to-ambient thermal resistance is based on measurements on a horizontal-single-sided
printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment
and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111)
Measurements were done with parts mounted on thermal test boards conforming to
specification EIA/JESD51-3.
Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G3088, with the exception that the cold plate temperature is used for the case temperature.
EL
Notes:
IM
Junction-to-ambient thermal resistance1
PR
2.
Preliminary Information
2-2
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
DC Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS
Table 2-3 DC Electrical Characteristics
Min
Typ
Max
Unit
Supply voltage
VCC
4.75
5.0
5.25
V
Input high voltage
• EXTAL
• RESET
• MODA, MODB, MODC
• ACI, SHI inputs1
• All other inputs
VIHC
VIHR
VIHM
VIHS
VIH
4.0
2.5
3.5
0.7 × VCC
2.0
—
—
—
—
—
VCC
VCC
VCC
VCC
VCC
V
V
V
V
V
Input low voltage
• EXTAL
• MODA, MODB, MODC
• ACI, SHI inputs1
• All other inputs
VILC
VILM
VILS
VIL
–0.5
–0.5
–0.5
–0.5
—
—
—
—
0.6
2.0
0.3 × VCC
0.8
V
V
V
V
Y
Symbol
IN
AR
Characteristics
Input leakage current
• EXTAL, RESET, MODA, MODB,
MODC, DR
• Other Input Pins (@ 2.4 V/0.4 V)
IIN
High impedance (off-state) input current
(@ 2.4 V / 0.4 V)
ITSI
Output high voltage (IOH = –0.4 mA)
Output low voltage (IOL = 3.2 mA)
SCK/SCL IOL = 6.7 mA
MISO/SDA IOL = 6.7 mA
HOREQ IOL = 6.7 mA
—
1
µA
–10
—
10
µA
–10
—
10
µA
VOH
2.4
—
—
V
VOL
—
—
0.4
V
ICCI
ICCW
ICCS
—
—
—
155
22
TBD
—
TBD
TBD
mA
mA
mA
—
1.2
2.0
mA
—
10
—
pF
EL
IM
–1
Internal Supply Current @ 95 MHz
• Normal mode4
• Wait mode
• Stop mode2
PLL supply current @ 95 MHz
PR
capacitance3
Input
Notes:
1.
2.
3.
4.
CIN
The SHI inputs are: MOSI/HA0, SS/HA2, MISO/SDA, SCK/SCL, and HREQ.
In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signals are
disabled during Stop state.
Periodically sampled and not 100% tested
Maximum values can be derived using the methodology described in Section 4. Actual maximums are
application dependent and may vary widely.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-3
Specifications
AC Electrical Characteristics
AC ELECTRICAL CHARACTERISTICS
AR
Y
The timing waveforms in the AC Electrical Characteristics are tested with a VIL
maximum of 0.5 V and a VIH minimum of 2.4 V for all inputs, except EXTAL,
RESET, MODA, MODB, MODC, ACI, and SHI inputs (MOSI/HA0, SS/HA2,
MISO/SDA, SCK/SCL, HREQ). These inputs are tested using the input levels set
forth in the DC Electrical Characteristics. AC timing specifications that are
referenced to a device input signal are measured in production with respect to the
50% point of the respective input signal’s transition. DSP56011 output levels are
measured with the production test machine VOL and VOH reference levels set at
0.8 V and 2.0 V, respectively.
All output delays are given for a 50 pF load unless otherwise specified.
For load capacitance greater than 50 pF, the drive capability of the output pins
typically decreases linearly:
IN
1. At 1.5 ns per 10 pF of additional capacitance at all output pins except
MOSI/HA0, MISO/SDA, SCK/SCL, HREQ
IM
2. At 1.0 ns per 10 pF of additional capacitance at output pins MOSI/HA0,
MISO/SDA, SCK/SCL, HREQ (in SPI mode only)
INTERNAL CLOCKS
Table 2-4 Internal Clocks
Expression
Symbol
EL
Characteristics
Internal operation frequency
Minimum
Maximum
0
95 MHz
ETHminimum
0.48 × TC
0.467 × TC
ETHmaximum
0.52 × TC
0.533 × TC
ETLminimum
0.48 × TC
0.467 × TC
ETLmaximum
0.52 × TC
0.533 × TC
F
TH
Internal clock low period
• with PLL disabled (see Note)
• with PLL enabled and MF ≤ 4
• with PLL enabled and MF > 4
TL
Internal clock cycle time
TC
(DF × ETC)/MF
ICYC
2 × TC
PR
Internal clock high period
• with PLL disabled1
• with PLL enabled and MF ≤ 4
• with PLL enabled and MF > 4
Instruction cycle time
Note:
See Table 2-5 on page 2-5 for External Clock (ET) specifications.
Preliminary Information
2-4
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
External Clock Operation
EXTERNAL CLOCK OPERATION
The DSP56011 system clock is externally supplied via the EXTAL pin. Timings shown
in this document are valid for clock rise and fall times of 3 ns maximum. The 81 MHz
speed allows the DSP56011 to take advantage of the 27 MHz system clock in DVD
applications.
Y
Table 2-5 External Clock (EXTAL)
81 MHz
No.
Characteristics
Sym.
Unit
Max
Min
Max
0
81
0
95
MHz
5.8
∞
4.9
∞
ns
5.2
235500
4.5
235500
ns
5.8
∞
4.9
∞
ns
5.2
235500
4.5
235500
ns
12.3
12.3
∞
409600
10.5
10.5
∞
409600
ns
ns
24.7
24.7
∞
819200
21.0
21.0
∞
819200
ns
ns
AR
Min
Frequency of external clock EXTAL
EF
External clock input high—EXTAL
• With PLL disabled
(46.7%–53.3% duty cycle)
• With PLL enabled
(42.5%–57.5% duty cycle)
ETH
IN
1
External clock input low—EXTAL
• With PLL disabled
(46.7%–53.3% duty cycle)
• With PLL enabled
(42.5%–57.5% duty cycle)
ETL
External clock cycle time
• With PLL disabled
• With PLL enabled
ETC
Instruction cycle time = ICYC = 2 × TC
• With PLL disabled
• With PLL enabled
ICYC
IM
2
3
EL
4
Note:
95 MHz
EXTAL input high and input low are measured at 50% of the input transition.
PR
EXTAL
1
ETH
2
3
ETC
ETL
4
AA0250
Figure 2-1 External Clock Timing
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-5
Specifications
Phase Lock Loop (PLL) Characteristics
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Table 2-6 Phase Lock Loop (PLL) Characteristics
Characteristics
Expression
Min
Max
Unit
MF × EF
10
f
MHz
MF × CPCAP
@ MF ≤ 4
@ MF > 4
Note:
Y
PLL external capacitor (PCAP pin to
VCCP)
AR
VCO frequency when PLL enabled
MF × 340
MF × 380
MF × 480
MF × 970
pF
pF
Cpcap is the value of the PLL capacitor (connected between PCAP pin and VCCP) for MF = 1.
The recommended value for Cpcap is 400 pF for MF ≤ 4 and 540 pF for MF > 4.
The maximum VCO frequency is limited to the internal operation frequency, defined in Table 2-4.
IN
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing
All Frequencies
10
Minimum RESET assertion width:
• PLL disabled
• PLL enabled1
Unit
Min
Max
25 × TC
2500 × ETC
—
—
ns
ns
21
—
ns
Mode select setup time
EL
14
Characteristics
IM
No.
Mode select hold time
0
—
ns
16
Minimum edge-triggered interrupt request assertion
width
13
—
ns
16a
Minimum edge-triggered interrupt request
deassertation width
13
—
ns
12 × TC + TH
11 × TC + TH
—
—
ns
ns
PR
15
18
Delay from IRQA, IRQB, NMI assertion to GPIO valid
caused by first interrupt instruction execution
• GPIO0–GPIO7
• PB0–PB14
Preliminary Information
2-6
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
RESET, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (Continued)
All Frequencies
No.
Characteristics
Unit
Min
TL – 31
(2 × TC) + TL –
31
Duration of IRQA assertion for recovery from stop
state
27
Duration for level-sensitive IRQA assertion to ensure
interrupt service (when exiting Stop mode)
• Stable external clock, OMR Bit 6 = 1
• Stable external clock, PCTL Bit 17 = 1
ns
6 × TC+ TL
12
—
—
ns
ns
This timing requirement is sensitive to the quality of the external PLL capacitor connected to the
PCAP pin. For capacitor values less than or equal to 2 nF, asserting RESET according to this timing
requirement will ensure proper processor initialization for capacitors with a delta C/C less than
0.5%. (This is typical for ceramic capacitors.) For capacitor values greater than 2 nF, asserting
RESET according to this timing requirement will ensure proper processor initialization for
capacitors with a delta C/C less than 0.01%. (This is typical for Teflon, polystyrene, and
polypropylene capacitors.) However, capacitors with values greater than 2 nF with a delta C/C
greater than 0.01% may require longer RESET assertion to ensure proper initialization.
When using fast interrupts and IRQA and IRQB are defined as level-sensitive, timing 22 applies to
prevent multiple interrupt service. To avoid these timing restrictions, negative-edge-triggered
configuration is recommended when using fast interrupts. Long interrupts are recommended
when using level-sensitive configuration.
EL
2.
—
IM
1.
ns
ns
12
IN
25
Notes:
Y
Delay from General Purpose Output valid to interrupt
request deassertion for level sensitive fast interrupts—
if second interrupt instruction is:2
• Single cycle
• Two cycles
AR
22
Max
VIHR
PR
RESET
10
AA0251
Figure 2-2 Reset Timing
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-7
Specifications
RESET, Stop, Mode Select, and Interrupt Timing
RESET
VIHR
14
15
VIHM
VIH
MODA, MODB
MODC
IRQA, IRQB,
NMI
VILM
VIL
Y
AA0252
AR
Figure 2-3 Operating Mode Select Timing
IRQA, IRQB,
NMI
16
IRQA, IRQB,
NMI
IN
16A
AA0253
General
Purpose
I/O
(Output)
IM
Figure 2-4 External Interrupt Timing (Negative-Edge Triggered)
18
General Purpose I/O
EL
IRQA
IRQB
NMI
22
AA0254
Figure 2-5 External Level-Sensitive Fast Interrupt Timing
25
PR
IRQA
AA0255
Figure 2-6 Recovery from Stop State Using IRQA
27
IRQA
AA0256
Figure 2-7 Recovery from Stop State Using IRQA Interrupt Service
Preliminary Information
2-8
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
Host Interface (HI) Timing
HOST INTERFACE (HI) TIMING
Note: Active low lines should be “pulled up” in a manner consistent with the AC
and DC specifications.
Table 2-8 Host I/O Timing (All Frequencies)
HEN/HACK assertion width1
• CVR, ICR, ISR, RXL read
• IVR, RXH/M read
• Write
Min
Max
Unit
Y
31
Characteristics
TC + 31
26
13
—
—
—
ns
13
2 × TC + 31
2 × TC + 31
2 × TC + 31
—
—
—
—
ns
ns
ns
ns
AR
Num
HEN/HACK deassertion width1
• After TXL writes2
• After RXL reads3
• Between two CVR, ICR, or ISR reads
33
Host data input setup time before HEN/HACK
deassertion
4
—
ns
34
Host data input hold time after HEN/HACK
deassertion
3
—
ns
35
HEN/HACK assertion to output data active from
high impedance
0
—
ns
36
HEN/HACK assertion to output data valid
—
26
ns
37
HEN/HACK deassertion to output data high
impedance5
—
18
ns
38
Output data hold time after HEN/HACK
Deassertion6
2.5
—
ns
EL
IM
IN
32
HR/W low setup time before HEN assertion
0
—
ns
40
HR/W low hold time after HEN deassertion
3
—
ns
41
HR/W high setup time to HEN assertion
0
—
ns
42
HR/W high hold time after HEN/HACK deassertion
3
—
ns
43
HOA0–HOA2 setup time before HEN assertion
0
—
ns
44
HOA0–HOA2 Hold Time After HEN Deassertion
3
—
ns
3
45
ns
TL + TC + TH
TL + TC
0
—
—
—
ns
ns
ns
PR
39
deassertion4
45
DMA HACK assertion to HOREQ
46
DMA HACK deassertion to HOREQ assertion4,5
• For DMA RXL read
• For DMA TXL write
• All other cases
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-9
Specifications
Host Interface (HI) Timing
Num
Characteristics
Min
Max
Unit
47
Delay from HEN deassertion to HOREQ assertion for
RXL read4,5
TL + TC + TH
—
ns
48
Delay from HEN deassertion to HOREQ assertion for
TXL write4,5
TL + TC
—
ns
49
Delay from HEN assertion to HOREQ deassertion for
RXL read, TXL write4,5
Y
Table 2-8 Host I/O Timing (All Frequencies) (Continued)
3.
4.
5.
6.
See Host Port Considerations in Section 4 Design Considerations.
This timing is applicable only if a write to the TXL is followed by writing the TXL, TXM, or TXH
registers without first polling the TXDE or HOREQ flags, or waiting for HOREQ to be asserted.
This timing is applicable only if a read from the RXL is followed by reading the RXL, RXM or RXH
registers without first polling the RXDF or HOREQ flags, or waiting for HOREQ to be asserted.
HOREQ is pulled up by a 1 kΩ resistor.
Specifications are periodically sampled and not 100% tested.
May decrease to 0 ns for future versions
HOREQ
(Output)
41
HR/W
(Input)
32
IM
31
HACK
(Input)
ns
AR
1.
2.
58
IN
Notes:
3
42
36
EL
35
H0–H7
(Output)
37
38
Data Valid
AA1275
PR
Figure 2-8 Host Interrupt Vector Register (IVR) Read
Preliminary Information
2-10
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
Host Interface (HI) Timing
HOREQ
(Output)
49
RXH
Read
RXM
Read
RXL
Read
32
31
43
44
Address Valid
Address Valid
41
42
HR/W
(Input)
36
37
35
38
H0–H7
(Output)
Address Valid
AR
HA2–HA0
(Input)
Y
HEN
(Input)
47
Data
Valid
Data
Valid
IN
Data
Valid
AA1276
HOREQ
(Output)
HEN
(Input)
IM
Figure 2-9 Host Read Cycle (Non-DMA Mode)
TXH
Write
48
TXM
Write
TXL
Write
32
31
EL
43
HA2–HA0
(Input)
49
44
Address Valid
39
Address Valid
Address Valid
40
PR
HR/W
(Input)
34
33
H0–H7
(Output)
Data
Valid
Data
Valid
Data
Valid
AA1277
Figure 2-10 Host Write Cycle (Non-DMA Mode)
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-11
Specifications
Host Interface (HI) Timing
HOREQ
(Output)
45
46
31
32
46
RXM
Read
36
RXL
Read
Y
RXH
Read
HACK
(Input)
37
38
AR
35
Data
Valid
H0–H7
(Output)
46
Data
Valid
Data
Valid
AA1278
HOREQ
(Output)
45
IN
Figure 2-11 Host DMA Read Cycle
46
46
31
TXH
Write
TXM
Write
IM
HACK
(Input)
33
TXL
Write
34
Data
Valid
Data
Valid
Data
Valid
AA1279
EL
H0–H7
(Output)
46
32
PR
Figure 2-12 Host DMA Write Cycle
Preliminary Information
2-12
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
Serial Audio Interface (SAI) Timing)
SERIAL AUDIO INTERFACE (SAI) TIMING)
Table 2-9 Serial Audio Interface (SAI) Timing
81 MHz
Characteristics
Mode
95 MHz
Expression
Master
4 × TC
Slave
3 × TC + 5
112 Serial Clock high period
Master
0.5 × TSAICC – 8
Max
Min
Max
49.4
—
42
—
ns
42
—
36.5
—
ns
16.7
—
13
—
ns
AR
111 Minimum Serial Clock cycle =
TSAICC (min)
Unit
Min
Y
No.
0.35 × TSAICC
14.7
—
12.8
—
ns
0.5 × TSAICC – 8
16.7
—
13
—
ns
0.35 × TSAICC
14.7
—
12.8
—
ns
8
—
8
—
8
ns
Slave
0.15 × TSAICC
—
6.3
—
5.5
ns
115 Data input valid to SCKR edge
(data input setup time)
Master
26
26
—
26
—
ns
Slave
4
4
—
4
—
ns
116 SCKR edge to data input not
valid (data input hold time)
Master
0
0
—
0
—
ns
Slave
14
14
—
14
—
ns
117 SCKR edge to word select output
valid (WSR out delay time)
Master
20
—
20
—
20
ns
118 Word select input valid to SCKR
edge (WSR in setup time)
Slave
12
12
—
12
—
ns
119 SCKR edge to word select input
not valid (WSR in hold time)
Slave
12
12
—
12
—
ns
121 SCKT edge to data output valid
(data out delay time)
Master
13
—
13
—
13
ns
Slave1
40
—
40
—
40
ns
Slave2
TH + 34
—
40.2
—
39.25
ns
122 SCKT edge to word select output
valid (WST output delay time)
Master
19
—
19
—
19
ns
123 Word select input valid to SCKT
edge (WST in setup time)
Slave
12
12
—
12
—
ns
124 SCKT edge to word select input
not valid (WST in hold time)
Slave
12
12
—
12
—
ns
Slave
113 Serial Clock low period
Master
Slave
Master
PR
EL
IM
IN
114 Serial Clock rise/fall time
Notes:
1.
2.
When the Frequency Ratio between Parallel and Serial clocks is 1:4 or greater
When the Frequency Ratio between Parallel and Serial clocks is 1:3 – 1:4
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-13
Specifications
Serial Audio Interface (SAI) Timing)
111
112
114
114
113
SCKR
(RCKP = 1)
111
114
SCKR
(RCKP = 0)
114
Y
113
SDI0–SDI1
(Data Input)
AR
112
115
116
Valid
119
IN
118
WSR
(Input)
IM
WSR
(Output)
Valid
117
AA0269
PR
EL
Figure 2-13 SAI Receiver Timing
Preliminary Information
2-14
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
Serial Audio Interface (SAI) Timing)
111
112
114
114
113
SCKT
(TCKP = 1)
111
114
SCKT
(TCKP = 0)
114
Y
113
SDO0–SDO2)
(Data Output)
AR
112
121
124
IN
123
WST
(Input)
IM
WST
(Output)
Valid
122
AA0270
PR
EL
Figure 2-14 SAI Transmitter Timing
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-15
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
SERIAL HOST INTERFACE (SHI) SPI PROTOCOL TIMING
Table 2-10 Serial Host Interface (SHI) SPI Protocol Timing
Characteristics
Mode
— Tolerable spike width
on Clock or Data input
81 MHz
Filter
Mode
Unit
Min Max Min Max
Bypassed
Narrow
Wide
—
—
—
0
20
100
—
—
—
0
20
100
AR
141 Minimum Serial Clock
cycle = tSPICC(min)
95 MHz
Expression
ns
ns
ns
Y
No.
Frequency
below 33 MHz1
Master
Bypassed
4 × TC
—
—
—
—
ns
•
Frequency above Master
33 MHz1
Bypassed
6 × TC
74.1
—
63
—
ns
Narrow
1000
1000
—
1000
—
ns
Slave
Wide
2000
2000
—
2000
—
ns
Bypassed
3 × TC
37
—
31.5
—
ns
Narrow
3 × TC + 25
62
—
56.5
—
ns
Wide
3 × TC + 85
122
—
116.5
—
ns
Bypassed
3 × TC + 79
116
—
110.5
—
ns
Narrow
3 × TC + 431
468
—
462.5
—
ns
Wide
3 × TC + 1022
1059
—
1053.5
—
ns
0.5 × TSPICC –10 27.0
—
21.5
—
ns
IM
CPHA = 0, CPHA =
12
IN
•
CPHA = 1
Slave
142 Serial Clock high period
Slave
EL
CPHA = 0, CPHA = 12
Master
PR
CPHA = 1
Slave
143 Serial Clock low period
CPHA = 0, CPHA =
CPHA = 1
12
Bypassed
TC + 8
20.3
—
18.5
—
ns
Narrow
TC + 31
43.3
—
41.5
—
ns
Wide
TC + 43
55.3
—
53.5
—
ns
Bypassed
TC + TH + 40
58.5
—
55.75
—
ns
Narrow
TC + TH + 216
235
—
231.75
—
ns
Wide
TC + TH + 511
536
—
526.75
—
ns
0.5 × TSPICC –10 27.0
—
21.5
—
ns
Master
Slave
Slave
Bypassed
TC + 8
20.3
—
18.5
—
ns
Narrow
TC + 31
43.3
—
41.5
—
ns
Wide
TC + 43
55.3
—
53.5
—
ns
Bypassed
TC + TH + 40
58.5
—
55.75
—
ns
Narrow
TC + TH + 216
235
—
231.75
—
ns
Wide
TC + TH + 511
536
—
526.75
—
ns
Preliminary Information
2-16
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
Table 2-10 Serial Host Interface (SHI) SPI Protocol Timing (Continued)
Mode
146 SS assertion to first SCK
edge
CPHA = 0
CPHA = 1
CPHA = 13
10
—
10
—
10
ns
Slave
2000
—
2000
—
2000
ns
Bypassed
TC + TH + 35
53.5
—
50.75
—
ns
Narrow
TC + TH + 35
53.5
—
50.75
—
ns
Wide
TC + TH + 35
53.5
—
50.75
—
ns
Slave
Slave
Bypassed
6
6
—
6
—
ns
Narrow
0
0
—
0
—
ns
Wide
0
0
—
0
—
ns
Bypassed
TC + 6
18.3
—
16.5
—
ns
Narrow
TC + 70
82.4
—
80.5
—
ns
Wide
TC + 197
209
—
207.5
—
ns
Bypassed
2
2
—
2
—
ns
Narrow
66
66
—
66
—
ns
Wide
193
193
—
193
—
ns
Bypassed
0
0
—
0
—
ns
Narrow
MAX {(37 –TC),
0}
25
—
26.5
—
ns
Wide
MAX {(52 –TC),
0}
40
—
41.5
—
ns
Bypassed
0
0
—
0
—
ns
Narrow
MAX {(38 –TC),
0}
26
—
27.5
—
ns
Wide
MAX {(53 –TC),
0}
41
—
42.5
—
ns
Bypassed
2 × TC + 17
41.7
—
38
—
ns
Narrow
2 × TC + 18
42.7
—
39
—
ns
Wide
2 × TC + 28
52.7
—
49
—
ns
Bypassed
2 × TC + 17
41.7
—
38
—
ns
Narrow
2 × TC + 18
42.7
—
39
—
ns
Wide
2 × TC + 28
52.7
—
49
—
ns
4
4
—
4
—
ns
IM
Slave
Master
EL
148 Data input valid to SCK
edge (data input setup
time)
PR
Slave
149 SCK edge to data input
not valid
(data in hold time)
Master
Slave
150 SS assertion to data out
active
Unit
Min Max Min Max
Master
Slave
147 Last SCK edge to SS not
asserted
CPHA = 0
95 MHz
Expression
Y
144 Serial Clock rise/fall
time
81 MHz
Filter
Mode
AR
Characteristics
IN
No.
Slave
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-17
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
Table 2-10 Serial Host Interface (SHI) SPI Protocol Timing (Continued)
Mode
151 SS deassertion to data
tri-stated4
Slave
152 SCK edge to data out
valid (data out delay
time)
Master
CPHA = 0, CPHA =
12
Slave
Unit
Min Max Min Max
24
—
24
—
24
ns
Bypassed
41
—
41
—
41
ns
Narrow
214
Wide
504
—
214
—
214
ns
—
504
—
504
ns
Bypassed
41
—
41
—
41
ns
Narrow
214
—
214
—
214
ns
Wide
504
—
504
—
504
ns
Bypassed
TC + TH + 40
—
58.5
—
55.75
ns
Narrow
TC + TH + 216
—
235
—
231.75
ns
Wide
TC + TH + 511
—
536
—
536
ns
Bypassed
0
0
—
0
—
ns
Narrow
57
57
—
57
—
ns
Wide
163
163
—
163
—
ns
Bypassed
0
0
—
0
—
ns
Narrow
57
57
—
57
—
ns
Wide
163
163
—
163
—
ns
TC + TH + 35
—
53.5
—
50.75
ns
—
75
—
68.75
ns
IM
153 SCK edge to data out not Master
valid (data out hold
time)
Slave
Slave
157 First SCK sampling edge
to HREQ output
deassertation
Slave
PR
EL
154 SS assertion to data
output valid
CPHA = 0
158 Last SCK sampling edge
to HREQ output not
deasserted
CPHA = 1
Slave
159 SS deassertion to HREQ
output not deasserted
CPHA = 0
Slave
95 MHz
Expression
IN
CPHA = 1
Slave
81 MHz
Filter
Mode
Y
Characteristics
AR
No.
Bypassed 3 × TC + TH + 32
Narrow
3 × TC + TH +
209
—
252
—
245.75
ns
Wide
3 × TC + TH +
507
—
550
—
543.75
ns
Bypassed
2 × TC + TH + 6 36.9
—
32.25
—
ns
Narrow
2 × TC + TH + 63 93.9
—
89.25
—
ns
200
—
195.25
—
ns
2 × TC + TH + 7 37.9
—
33.25
—
ns
Wide
2 × TC + TH +
169
Preliminary Information
2-18
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
Table 2-10 Serial Host Interface (SHI) SPI Protocol Timing (Continued)
Mode
160 SS deassertion pulse
width
CPHA = 0
161 HREQ input assertion to
first SCK edge
TC + 4
16.3
—
14.5
—
ns
Master
0.5 × TSPICC+
2 × TC + 6
67.7
—
58.5
—
ns
0
—
0
—
ns
0
—
0
—
ns
2.
0
For an internal clock frequency below 33 MHz, the minimum permissible internal clock to SCK frequency
ratio is 4:1.
For an internal clock frequency above 33 MHz, the minimum permissible internal clock to SCK frequency
ratio is 6:1.
In CPHA = 1 mode, the SPI slave supports data transfers at TSPICC = 3 × TC, if the user assures that the
HTX is written at least TC ns before the first edge of SCK of each word.In CPHA = 1 mode, the SPI slave
supports data transfers at TsPICC = 3 × TC, if the user assures that the HTX is written at least TC ns before
the first edge of SCK of each word.
When CPHA = 1, the SS line may remain active low between successive transfers.
Periodically sampled, not 100% tested
PR
EL
3.
4.
Master
0
IN
1.
Unit
Min Max Min Max
IM
Notes:
95 MHz
Expression
Slave
162 HREQ input deassertion Master
to last SCK sampling
edge (HREQ input setup
time) CPHA = 1
163 First SCK edge to HREQ
input not asserted
(HREQ input hold time)
81 MHz
Filter
Mode
Y
Characteristics
AR
No.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-19
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
SS
(Input)
143
141
142
144
144
SCK (CPOL = 0)
(Output)
144
148
149
MISO
(Input)
MSB
Valid
149
148
LSB
Valid
152
MOSI
(Output)
144
AR
SCK (CPOL = 1)
(Output)
141
Y
142
143
153
161
LSB
163
IM
HREQ
(Input)
IN
MSB
AA0271
PR
EL
Figure 2-15 SPI Master Timing (CPHA = 0)
Preliminary Information
2-20
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
SS
(Input)
143
141
142
144
144
SCK (CPOL = 0)
(Output)
142
SCK (CPOL = 1)
(Output)
Y
141
144
143
144
149
MISO
(Input)
148
AR
148
149
MSB
Valid
LSB
Valid
152
MOSI
(Output)
153
161
IN
MSB
LSB
162
163
IM
HREQ
(Input)
AA0272
PR
EL
Figure 2-16 SPI Master Timing (CPHA = 1)
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-21
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
SS
(Input)
143
141
142
144
147
144
160
SCK (CPOL = 0)
(Input)
142
144
154
152 153
153
150
MISO
(Output)
144
AR
143
SCK (CPOL = 1)
(Input)
141
Y
146
MSB
148
151
LSB
148
MOSI
(Input)
IN
149
MSB
Valid
LSB
Valid
157
IM
HREQ
(Output)
149
159
AA0273
PR
EL
Figure 2-17 SPI Slave Timing (CPHA = 0)
Preliminary Information
2-22
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
SS
(Input)
143
141
142
144
147
144
146
142
144
143
144
AR
SCK (CPOL = 1)
(Input)
Y
SCK (CPOL = 0)
(Input)
152
152
150
MISO
(Output)
153
151
MSB
148
LSB
148
MOSI
(Input)
IN
149
MSB
Valid
157
IM
HREQ
(Output)
149
LSB
Valid
158
AA0274
PR
EL
Figure 2-18 SPI Slave Timing (CPHA = 1)
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-23
Specifications
Serial Host Interface (SHI) I2C Protocol Timing
SERIAL HOST INTERFACE (SHI) I2C PROTOCOL TIMING
RP (min) = 1.5 kΩ
Table 2-11 SHI I2C Protocol Timing
Y
Standard I2C
(CL = 400 pF, RP = 2 kΩ, 100 kHz)
All Frequencies
No.
Characteristics
Symbol
Unit
Max
Tolerable spike width on SCL or SDA filters
bypassed
—
0
ns
Narrow filters enabled
—
20
ns
—
100
ns
AR
Min
Minimum SCL Serial Clock cycle
TSCL
10.0
—
µs
172
Bus free time
TBUF
4.7
—
µs
173
Start condition setup time
TSU;STA
4.7
—
µs
174
Start condition hold time
THD;STA
4.0
—
µs
175
SCL low period
TLOW
4.7
—
µs
176
SCL high period
THIGH
4.0
—
µs
177
SCL and SDA rise time
TR
—
1.0
µs
178
SCL and SDA fall time
TF
—
0.3
µs
IM
IN
171
EL
Wide filters enabled
Data setup time
TSU;DAT
250
—
ns
180
Data hold time
THD;DAT
0.0
—
ns
182
SCL low to data output valid
TVD;DAT
—
3.4
µs
183
Stop condition setup time
TSU;STO
4.0
—
µs
PR
179
Preliminary Information
2-24
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
Serial Host Interface (SHI) I2C Protocol Timing
Programming the Serial Clock
The Programmed Serial Clock Cycle, t I2CCP , is specified by the value of the HDM5–
HDM0 and HRS bits of the HCKR (SHI Clock control Register).
The expression for t I2CCP is:
Y
t I2CCP = [TC × 2 × (HDM[5:0] + 1) × (7 × (1 – HRS) + 1)]
where
HRS is the Prescaler Rate Select bit. When HRS is cleared, the fixed divideby-eight prescaler is operational. When HRS is set, the prescaler is
bypassed.
–
MDM5–HDM0 are the Divider Modulus Select bits.
–
A divide ratio from 1 to 64 (HDM5–HDM0 = 0 to $3F) may be selected.
AR
–
IN
In I2C mode, you may select a value for the Programmed Serial Clock Cycle from:
6 × TC (if HDM[5:0] = $02 and HRS = 1)
to
1024 × TC (if HDM[5:0] = $3F and HRS = 0)
PR
EL
IM
The DSP56011 provides an improved I2C bus protocol. In addition to supporting the
100 kHz I2C bus protocol, the SHI in I2C mode supports data transfers at up to 1000
kHz. The actual maximum frequency is limited by the bus capacitances (CL),the pullup resistors (RP), (which affect the rise and fall time of SDA and SCL, see Table 2-12
on page 2-26), and by the input filters.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-25
Specifications
Serial Host Interface (SHI) I2C Protocol Timing
Considerations for Programming the SHI Clock Control Register
(HCKR)—Clock Divide Ratio
The master must generate a bus free time greater than T172 slave when operating
with a DSP56011 SHI I2C slave. Table 2-12 describes a few examples.
Y
Table 2-12 Considerations for Programming the SHI Clock control Register (HCKR)
Conditions to be Considered
Slave
Operating
Freq.
CL = 50 pF,
RP = 2 kΩ
81 MHz
81 MHz
CL = 50 pF,
RP = 2 kΩ
95 MHz
95 MHz
Bypassed
Narrow
Wide
Slave
Filter
Mode
T172
Slave
Min.
Permissible
tI CCP
T172
Master
Maximum
I2C Serial
Frequency
Bypassed 36 ns
Narrow 60 ns
Wide
95 ns
52 × TC
56 × TC
62 × TC
41 ns
66 ns
103 ns
1010 kHz
825 kHz
634 kHz
60 × TC
64 × TC
71 × TC
35 ns
56 ns
92.8 ns
1030 kHz
843 kHz
645 kHz
2
IN
Bus Load
Master
Filter
Mode
AR
Master
Operating
Freq.
Resulting Limitations
Bypassed
Narrow
Wide
Bypassed 32 ns
Narrow 56 ns
Wide
91 ns
IM
Example: for CL = 50 pF, RP = 2 kΩ, f = 81 MHz, Bypassed filter mode: The master,
when operating with a DSP56011 SHI I2C slave with an 81 MHz operating frequency,
must generate a bus free time greater than 36 ns (T172 slave). Thus, the minimum
permissible TI2CCP is 52 × TC, which gives a bus free time of at least 41 ns (T172
master). This implies a maximum I2C serial frequency of 1010 kHz.
EL
In general, bus performance may be calculated from the CL and RP of the bus,
the input filter modes and operating frequencies of the master and the slave.
Table 2-13 on page 2-27 contains the expressions required to calculate all relevant
performance timing for a given CL and RP.
PR
Note: T177 (tr) is computed using the values of CL and RP and T178 (TF) is
computed using the value of CL. The two values are used in computing many
of the other timing values in Table 2-13 on page 2-27.
Preliminary Information
2-26
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
Serial Host Interface (SHI) I2C Protocol Timing
Table 2-13 SHI Improved I2C Protocol Timing
Improved I2C (CL = 50 pF, RP = 2 kΩ)
Sym.
Mode
— Tolerable spike
width on SCL or
SDA
TSCL
Bypassed
Narrow
Wide
0
20
100
Unit
Min Max Min
0
20
100
—
—
—
0
20
100
ns
ns
ns
T I CCP + 3 × TC +
72 +TR
989
—
971.5
—
ns
Narrow
T I CCP + 3 × TC +
245 + TR
1212
—
1186.5
—
ns
Wide
T I CCP + 3 × TC +
535 + TR
1576
—
1550
—
ns
Bypassed 4 × TC + TH + 172 + 466
TR
—
457.3
—
ns
Narrow
4 × TC + TH + 366 + 660
TR
—
651.3
—
ns
Wide
4 × TC + TH + 648 + 942
TR
—
933.3
—
ns
Master Bypassed 0.5 × T I CCP – 42 – TR 41.1
—
35
—
ns
Narrow
0.5 × T I CCP – 42 – TR 65.8
—
56
—
ns
Wide
0.5 × T I CCP – 42 – TR 103
—
92.8
—
ns
Master Bypassed
2
2
2
IM
Slave
172 Bus free time
TBUF
2
2
35.7
—
32
—
ns
Narrow
2 × TC + 35
59.7
—
56
—
ns
Wide
2 × TC + 70
94.7
—
91
—
ns
Bypassed
12
12
—
12
—
ns
Narrow
50
50
—
50
—
ns
Wide
150
150
—
150
—
ns
THD;STA Master Bypassed 0.5 × T I CCP + 12 – TF 313
—
307
—
ns
Narrow
0.5 × T I CCP + 12 – TF 338
—
328
—
ns
Wide
0.5 × T I CCP + 12 – TF 375
—
364.8
—
ns
EL
2 × TC + 11
TSU;STA
Slave
PR
174 Start condition
hold time
2
Bypassed
Slave
173 Start condition
setup time
Max
—
—
—
IN
171 SCL Serial Clock
cycle
Expression
Y
Characteristic
95 MHz3
AR
No.
81 MHz2
Filter
Mode
2
Slave
2
2
Bypassed
2 × TC + TH + 21
51.9
—
47.25
—
ns
Narrow
2 × TC + TH + 100
131
—
126.25
—
ns
Wide
2 × TC + TH + 200
231
—
226.25
—
ns
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-27
Specifications
Serial Host Interface (SHI) I2C Protocol Timing
Table 2-13 SHI Improved I2C Protocol Timing (Continued)
Improved I2C (CL = 50 pF, RP = 2 kΩ)
Sym.
175 SCL low period
TLOW
Mode
Narrow
0.5 × T I CCP + 18 – TF 344
—
334
—
ns
Wide
0.5 × T I CCP + 18 – TF 381
—
370.75
—
ns
2
2
—
333
—
ns
Narrow
2 × TC + 286 + TR
548.6
—
545
—
ns
Wide
2 × TC + 586 + TR
849
—
845
—
ns
Master Bypassed 0.5 × T I CCP +2 × TC 365
+ 19
—
355
—
ns
Narrow
0.5 × T I CCP +2 × TC 514
+ 144
—
501
—
ns
Wide
0.5 × T I CCP + 2 × TC 763
+ 356
—
749.8
—
ns
2
2
2
2 × TC + TH – 1
30
—
25.25
—
ns
Narrow
2 × TC + TH + 18
49
—
44.25
—
ns
Wide
2 × TC + TH + 30
61
—
56.25
—
ns
1.7 × RP ×
(CL + 20)1
—
238
—
238
ns
2000
—
2000
—
2000
ns
20 + 0.1 × (CL– 50)1
—
20
—
20
ns
2000
—
2000
—
2000
ns
Bypassed
TC + 8
20
—
18.5
—
ns
Narrow
TC + 60
72
—
70.5
—
ns
Wide
TC + 74
86
—
84.5
—
ns
Bypassed
Narrow
Wide
0
0
0
0
0
0
—
—
—
0
0
0
—
—
—
ns
ns
ns
IM
Bypassed
EL
TF
PR
Input
180 Data hold time
TSU;DAT
THD;DAT
ns
337
Input
179 Data setup time
—
2 × TC + 74 + TR
TR
178 SCL fall time
Output
313
Bypassed
Slave
177 SCL rise time
Output
Max
—
2
IN
THIGH
Min Max Min
Master Bypassed 0.5 × T I CCP + 18 – TF 319
Slave
176 SCL high period
Unit
Expression
Y
Characteristic
95 MHz3
AR
No.
81 MHz2
Filter
Mode
Preliminary Information
2-28
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
Serial Host Interface (SHI) I2C Protocol Timing
Table 2-13 SHI Improved I2C Protocol Timing (Continued)
Improved I2C (CL = 50 pF, RP = 2 kΩ)
182 SCL low to data
output valid
Mode
TVD;DAT
Expression
Bypassed
2 × TC + 71 + TR
—
Narrow
2 × TC + 244 + TR
—
507
—
503
ns
Wide
2 × TC + 535 + TR
—
798
—
794
ns
0.5 × T I CCP + TC +
TH + 11
351
—
341.75
—
ns
Narrow
0.5 × T I CCP + TC +
TH + 69
433
—
420.75
—
ns
Wide
0.5 × T I CCP + TC +
TH + 183
584
—
571.5
—
ns
Bypassed
11
11
—
11
—
ns
Narrow
50
50
—
50
—
ns
Wide
150
150
—
150
—
ns
0
0
—
0
—
ns
Narrow
0
0
—
0
—
ns
Wide
0
0
—
0
—
ns
Bypassed
3 × TC + TH + 32
—
75
—
68.75
ns
Narrow
3 × TC + TH + 209
—
252
—
245.75 ns
Wide
3 × TC + TH + 507
—
550
—
543.7
ns
Bypassed
2 × TC + TH + 6
37
—
32.25
—
ns
Narrow
2 × TC + TH + 63
93.9
—
89.25
—
ns
Wide
2 × TC + TH + 169
200
—
195.25
—
ns
T I CCP + 2 × TC + 6
673
—
657
—
ns
Narrow
T I CCP + 2 × TC + 6
722
—
699
—
ns
Wide
T I CCP + 2 × TC + 6
796
—
772.5
—
ns
0
0
—
0
—
ns
Unit
Min Max Min
TSU;STO Master Bypassed
2
2
2
IN
183 Stop condition
setup time
Sym.
Slave
Master Bypassed
IM
184 HREQ input
deassertion to
last SCL edge
(HREQ in setup
time)
Slave
187 Last SCL edge to
HREQ output not
deasserted
Slave
PR
EL
186 First SCL
sampling edge to
HREQ output
deassertation
188 HREQ input
assertion to first
SCL edge
189 First SCL edge to
HREQ input not
asserted (HREQ
input hold time)
Master Bypassed
Master
334
Max
—
330
ns
Y
Characteristic
95 MHz3
AR
No.
81 MHz2
Filter
Mode
2
2
2
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-29
Specifications
Serial Host Interface (SHI) I2C Protocol Timing
Table 2-13 SHI Improved I2C Protocol Timing (Continued)
Improved I2C (CL = 50 pF, RP = 2 kΩ)
Characteristic
Notes:
1.
2.
Sym.
Mode
81 MHz2
Unit
Expression
Min Max Min
Max
CL is in pF, RP is in kΩ, and result is in ns.
A T I CCP of 52 × TC (the maximum permitted for the given bus load) was used for the calculations in the
Bypassed filter mode. A T I CCP of 56 × TC (the maximum permitted for the given bus load) was used for the
calculations in the Narrow filter mode. A T I CCP of 62 × TC (the maximum permitted for the given bus
load) was used for the calculations in the Wide filter mode.
A T I CCP of 60 × TC (the maximum permitted for the given bus load) was used for the calculations in the
Bypassed filter mode. A T I CCP of 64 × TC (the maximum permitted for the given bus load) was used for the
calculations in the Narrow filter mode. A T I CCP of 71 × TC (the maximum permitted for the given bus
load) was used for the calculations in the Wide filter mode.
2
2
AR
2
3.
95 MHz3
Y
No.
Filter
Mode
2
2
2
173
176
SCL
177
172
175
Stop
180
178
179
IM
SDA
IN
171
Start
MSB
174
186
189
ACK
182
Stop
183
184
EL
188
LSB
187
HREQ
AA0275
PR
Figure 2-19 I2C Timing
Preliminary Information
2-30
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
General Purpose Input/Output (GPIO) Timing
GENERAL PURPOSE INPUT/OUTPUT (GPIO) TIMING
Table 2-14 GPIO Timing
All Frequencies
No.
Characteristics
Expression
Unit
Min
Max
—
26
ns
2
—
ns
EXTAL edge to GPIO output valid (GPIO output
delay time)
26
202
EXTAL edge to GPIO output not valid (GPIO
output hold time)
2
203
GPIO input valid to EXTAL Edge (GPIO input
setup time)
10
10
—
ns
204
EXTAL edge to GPIO input not valid (GPIO input
hold time)
6
6
—
ns
EXTAL
(Input)
IM
(see Note)
IN
AR
Y
201
201
202
GPIO0–GPIO7
PB0–PB14
(Output)
203
EL
GPIO0–GPIO7
PB0–PB14
(Input)
Valid
Valid when the ratio between EXTAL frequency and internal clock frequency equals 1
PR
Note:
204
AA1284
Figure 2-20 GPIO Timing
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-31
Specifications
Digital Audio Transmitter (DAX) Timing
DIGITAL AUDIO TRANSMITTER (DAX) TIMING
Table 2-15 56011 Digital Audio Transmitter Timing
All Frequencies
No.
Characteristic
Unit
Min
Max
—
25
MHz
40
—
ns
0.5 × TC
—
ns
0.5 × TC
—
ns
—
35
ns
220
ACI Period
221
ACI High Duration
222
ACI Low Duration
223
ACI Rising Edge to ADO Valid
In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the
DSP56011 internal clock frequency. For example, if the DSP56011 is running at 40 MHz internally,
the ACI frequency should be less than 20 MHz.
IN
Note:
AR
Y
ACI Frequency (see Note)
IM
ACI
220
221
222
223
AA1280
EL
ADO
PR
Figure 2-21 Digital Audio Transmitter Timing
Preliminary Information
2-32
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
On-Chip Emulation (OnCE) Timing
ON-CHIP EMULATION (OnCE) TIMING
Table 2-16 OnCE Timing
All Frequencies
No.
Characteristics
Unit
Min
Max
—
DSCK low
40
231
DSCK high
40
232
DSCK cycle time
200
233
DR asserted to DSO (ACK) asserted
234
DSCK high to DSO valid
235
DSCK high to DSO invalid
236
DSI valid to DSCK low (setup)
237
DSCK Low to DSI Invalid (Hold)
238
Last DSCK low to OS0–OS1, ACK active
239
DSO (ACK) asserted to first DSCK high
240
DSO (ACK) assertion width
241
DSO (ACK) asserted to OS0–OS1 high
impedance1
242
OS0–OS1 valid to second EXTAL transition
243
Second EXTAL transition to OS0–OS1 invalid
244
Last DSCK low of read register to first DSCK high
of next command
ns
—
ns
AR
—
5 TC
—
ns
—
42
ns
3
—
ns
15
—
ns
3
—
ns
3 TC + TL
—
ns
2 TC
—
ns
4 TC + TH – 3
5 TC + 7
ns
—
0
ns
TC – 21
—
ns
0
—
ns
7 TC + 10
—
ns
IN
IM
EL
ns
Y
230
Last DSCK low to DSO invalid (hold)
3
—
ns
246
DR assertion to second EXTAL transition for
wake up from Wait state
10
TC – 10
ns
247
Second EXTAL transition to DSO after wake up
from Wait state
17 TC
—
ns
15
12 TC – 15
ns
13 TC + 15
—
17 TC
—
PR
245
248
249
DR assertion width
• To recover from Wait
• To recover from Wait and enter Debug
mode
DR assertion to DSO (ACK) valid (enter Debug
mode) after asynchronous recovery from Wait
state
ns
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-33
Specifications
On-Chip Emulation (OnCE) Timing
Table 2-16 OnCE Timing (Continued)
All Frequencies
Characteristics
Unit
Min
Max
15
15
15
65548 TC + TL
20 TC + TL
13 TC + TL
250A DR assertion width to recover from Stop2
• Stable External Clock, OMR Bit 6 = 0
• Stable External Clock, OMR Bit 6 = 1
• Stable External Clock, PCTL Bit 17 = 1
Notes:
65549 TC + TL
21 TC + TL
14 TC + TL
—
—
—
DR assertion to DSO (ACK) valid (enter Debug
mode) after recovery from Stop state2
• Stable External Clock, OMR Bit 6 = 0
• Stable External Clock, OMR Bit 6 = 1
• Stable External Clock, PCTL Bit 17= 1
65553 TC + TL
25 TC + TL
18 TC + TL
—
—
—
ns
AR
251
DR assertion width to recover from Stop and enter
Debug mode2
• Stable External Clock, OMR Bit 6 = 0
• Stable External Clock, OMR Bit 6 = 1
• Stable External Clock, PCTL Bit 17= 1
1.
2.
IN
250B
ns
Y
No.
ns
Maximum TL
Periodically sampled, not 100% tested
IM
246
246
230
DSCK
(input)
231
EL
232
AA0277
Figure 2-22 DSP56011 OnCE Serial Clock Timing
PR
DR
(Input)
DSO
(Output)
233
240
ACK
AA0278
Figure 2-23 DSP56011 OnCE Acknowledge Timing
Preliminary Information
2-34
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
On-Chip Emulation (OnCE) Timing
DSCK
(Input)
(Last)
(OS1)
DSO
(Output)
236
237
(ACK)
238
DSI
(Input)
Y
Note:
(OS0)
(Note 1)
High Impedance, external pull-down resistor
AA0279
DSCK
(Input)
(Last)
234
235
(Note 1)
245
(OS0)
IN
DSO
(Output)
Note:
AR
Figure 2-24 DSP56011 OnCE Data I/O to Status Timing
High Impedance, external pull-down resistor
AA0280
IM
Figure 2-25 DSP56011 OnCE Read Timing
239
OS1
(Output)
(see Note)
241
(DSCK Input)
240
EL
DSO
(Output)
(DSO Output)
(DSI Input)
OS0
(Output)
(see Note)
236
PR
241
Note:
237
High Impedance, external pull-down resistor
AA1281
Figure 2-26 DSP56011 OnCE Data I/O Status Timing
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-35
Specifications
On-Chip Emulation (OnCE) Timing
EXTAL (Note 2)
242
OS0–OS1
(Output)
(Note 1)
1. High Impedance, external pull-down resistor
2. Valid when the ratio between EXTAL frequency and clock frequency equals 1
Y
Note:
243
AA0282
AR
Figure 2-27 DSP56011 OnCE EXTAL to Status Timing
DSCK
(Input)
(Next Command)
244
IN
AA0283
Figure 2-28 DSP56011 OnCE DSCK Next Command After Read Register Timing
T0, T2
EXTAL
T1, T3
DR
(Input)
IM
248
246
EL
DSO
(Output)
247
AA0284
PR
Figure 2-29 Synchronous Recovery from Wait State
248
DR
(Input)
249
DSO
(Output)
AA0285
Figure 2-30 Asynchronous Recovery from Wait State
Preliminary Information
2-36
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Specifications
On-Chip Emulation (OnCE) Timing
250
DR
(Input)
251
DSO
(Output)
Y
AA0286
PR
EL
IM
IN
AR
Figure 2-31 Asynchronous Recovery from Stop State
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-37
Specifications
PR
EL
IM
IN
AR
Y
On-Chip Emulation (OnCE) Timing
Preliminary Information
2-38
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
SECTION
3
PIN-OUT AND PACKAGE INFORMATION
Y
PACKAGING
PR
EL
IM
IN
AR
This sections provides information about the available packages for this product,
including diagrams of the package pinouts and tables describing how the signals
described in Section 1 are allocated. The DSP56011 is available in a 100-pin Thin
Quad Flat Pack (TQFP) package.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
3-1
Packaging
Pin-out and Package Information
TQFP Package Description
51
76
IN
50
IM
GPIO7
GPIO6
GNDD
GPIO5
GPIO4
VCCD
GPIO3
GPIO2
GNDD
GPIO1
GPIO0
GNDQ
VCCQ
not connected
not connected
GNDA
not connected
VCCA
not connected
not connected
GNDA
not connected
not connected
not connected
VCCA
AR
75
Y
DR
not connected
not connected
not connected
not connected
DSCK/OS1
DSI/OS0
DSO
SDI0
SDI1
WSR
GNDS
VCCQ
GNDQ
SCKR
WST
SCKT
VCCS
SDO0
SDO1
SDO2
GNDS
HREQ
SS/HA2
MOSI/HA0
Top and bottom views of the TQFP package are shown in Figure 3-1 and Figure 3-2
with their pin-outs.
(Top View)
26
PR
not connected
not connected
GNDA
not connected
not connected
H7/PB7
H6/PB6
GNDH
HOA2/PB10
VCCH
HOA1/PB9
HR/W/PB11
HEN/PB12
VCCQ
GNDQ
HACK/PB14
GNDH
HOA0/PB8
H5/PB5
VCCH
H4/PB4
H3/PB3
GNDH
H2/PB2
H1/PB1
1
100
25
EL
Orientation Mark
VCCS
MODC/NMI
MODB/IRQB
MODA/IRQA
RESET
MISO/SDA
GNDS
SCK/SCL
EXTAL
VCCP
PCAP
GNDP
PINIT
GNDQ
VCCQ
PLOCK
not connected
not connected
not connected
ACI
ADO
VCCH
GNDH
HOREQ/PB13
H0/PB0
AA1282
Figure 3-1 DSP56011 Thin Quad Flat Pack (TQFP), Top View
Preliminary Information
3-2
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Packaging
76
GPIO7
GPIO6
GNDD
GPIO5
GPIO4
VCCD
GPIO3
GPIO2
GNDD
GPIO1
GPIO0
GNDQ
VCCQ
not connected
not connected
GNDA
not connected
VCCA
not connected
not connected
GNDA
not connected
not connected
not connected
VCCA
IN
AR
Y
50
Orientation Mark
25
(Bottom View)
100
EL
H1/PB1
H2/PB2
GNDH
H3/PB3
H4/PB4
VCCH
H5/PB5
HOA0/PB8
GNDH
HACK/PB14
GNDQ
VCCQ
HEN/PB12
HR/W/PB11
HOA1/PB9
VCCH
HOA2/PB10
GNDH
H6/PB6
H7/PB7
not connected
not connected
GNDA
not connected
not connected
26
1
IM
VCCS
MODC/NMI
MODB/IRQB
MODA/IRQA
RESET
MISO/SDA
GNDS
SCK/SCL
EXTAL
VCCP
PCAP
GNDP
PINIT
GNDQ
VCCQ
PLOCK
not connected
not connected
not connected
ACI
ADO
VCCH
GNDH
HOREQ/PB13
H0/PB0
75
WSR
SDI1
SDI0
DSO
DSI/OS0
DSCK/OS1
not connected
not connected
not connected
not connected
DR
SCKT
WST
SCKR
GNDQ
VCCQ
GNDS
SDO2
SDO1
SDO0
VCCS
51
MOSI/HA0
SS/HA2
HREQ
GNDS
Pin-out and Package Information
AA1283
PR
Figure 3-2 DSP56011 Thin Quad Flat Pack (TQFP), Bottom View
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
3-3
Packaging
Pin-out and Package Information
Table 3-1 Signal by Pin Number
Signal Name
Pin
#
Signal Name
Pin #
Signal Name
Pin
#
Signal Name
1
not connected
26
H0/PB0
51
MOSI/HA0
76
GPIO7
2
not connected
27
HOREQ/
PB13
52
SS/HA2
77
GPIO6
3
GNDA
28
GNDH
53
HREQ
78
GNDD
4
not connected
29
VCCH
54
GNDS
79
GPIO5
5
not connected
30
ADO
6
H7/PB7
31
ACI
7
H6/PB6
32
8
GNDH
9
AR
Y
Pin #
SDO2
80
GPIO4
56
SDO1
81
VCCD
not connected
57
SDO0
82
GPIO3
33
not connected
58
VCCS
83
GPIO2
HOA2/PB10
34
not connected
59
SCKT
84
GNDD
10
VCCH
35
PLOCK
60
WST
85
GPIO1
11
HOA1/PB9
36
VCCQ
61
SCKR
86
GPIO0
12
HR/W/PB11
37
GNDQ
62
GNDQ
87
GNDQ
13
HEN/PB12
38
PINIT
63
VCCQ
88
VCCQ
14
VCCQ
39
GNDP
64
GNDS
89
not connected
15
GNDQ
40
PCAP
65
WSR
90
not connected
16
HACK/PB14
41
VCCP
66
SDI1
91
GNDA
EL
IM
IN
55
GNDH
42
EXTAL
67
SDI0
92
not connected
18
HOA0/PB8
43
SCK/SCL
68
DSO
93
VCCA
19
H5/PB5
44
GNDS
69
DSI/OS0
94
not connected
20
VCCH
45
MISO/SDA
70
DSCK/OS1
95
not connected
21
H4/PB4
46
RESET
71
not connected
96
GNDA
22
H3/PB3
47
MODA/
IRQA
72
not connected
97
not connected
23
GNDH
48
MODB/IRQB
73
not connected
98
not connected
24
H2/PB2
49
MODC/NMI
74
not connected
99
not connected
25
H1/PB1
50
VCCS
75
DR
100
VCCA
PR
17
Preliminary Information
3-4
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Packaging
Pin-out and Package Information
Table 3-2 Signal by Name
Pin
#
Signal Name
Pin #
Signal Name
Pin
#
Signal Name
Pin #
ACI
31
GPIO7
76
not connected
32
PB14
16
ADO
30
H0
26
not connected
33
PCAP
40
DR
75
H1
25
not connected
34
PINIT
38
DSCK
70
H2
24
not connected
DSI
69
H3
22
not connected
DSO
68
H4
21
EXTAL
42
H5
19
GNDA
3
H6
7
GNDA
91
H7
6
GNDA
96
HA0
51
GNDD
78
HA2
52
not connected
GNDD
84
HACK
16
GNDH
8
HEN
GNDH
17
HOA0
PLOCK
35
72
RESET
46
AR
71
73
SCK
43
not connected
74
SCKR
61
not connected
89
SCKT
59
not connected
90
SCL
43
not connected
92
SDA
45
94
SDI0
67
not connected
95
SDI1
66
13
not connected
97
SDO0
57
18
not connected
98
SDO1
56
IN
not connected
IM
GNDH
Y
Signal Name
23
HOA1
11
not connected
99
SDO2
55
28
HOA2
9
OS0
69
SS
52
39
HOREQ
27
OS1
70
VCCA
93
15
HREQ
53
PB0
26
VCCA
100
37
HR/W
12
PB1
25
VCCD
81
GNDQ
62
IRQA
47
PB2
24
VCCH
10
GNDQ
87
IRQB
48
PB3
22
VCCH
20
GNDS
44
MISO
45
PB4
21
VCCH
29
GNDS
64
MODA
47
PB5
19
VCCP
41
GNDS
54
MODB
48
PB6
7
VCCQ
14
GPIO0
86
MODC
49
PB7
6
VCCQ
36
GPIO1
85
MOSI
51
PB8
18
VCCQ
63
GPIO2
83
NMI
49
PB9
11
VCCQ
88
GPIO3
82
not connected
1
PB10
9
VCCS
50
GPIO4
80
not connected
2
PB11
12
VCCS
58
GPIO5
79
not connected
4
PB12
13
WSR
65
GPIO6
77
not connected
5
PB13
27
WST
60
GNDH
GNDP
GNDQ
PR
EL
GNDQ
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
3-5
Packaging
Pin-out and Package Information
4X
0.2 T L-M N
G
0.2 T L-M N
4X 25 TIPS
76
100
CL
1
X
X = L, M, OR N
AB
75
AB
VIEW Y
M
B V
Y
L
AR
BASE METAL
F
3X VIEW
Y
V1
B1
25
J
U
D
51
PLATING
0.08 M T L-M N
26
S1
A
4X
4X
θ2
0.08 T
100X
SEATING
PLANE
θ3
EL
T
IM
S
IN
N
A1
C
50
SECTION AB-AB
ROTATED 90 CLOCKWISE
NOTES:
1. DIMENSIONS AND TOLERANCES PER ASME Y14.5M,
1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT THE
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
PER SIDE. DIMENSIONS A AND B INCLUDE MOLD
MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE LEAD WIDTH TO EXCEED 0.35. MINIMUM
SPACE BETWEEN PROTRUSION AND ADJACENT
LEAD OR PROTRUSION 0.07.
VIEW AA
0.05
PR
(W)
θ1
2X
R R1
0.25
C2
GAGE PLANE
(K)
E
θ
C1
(Z)
VIEW AA
CASE 983-02
ISSUE E
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
R1
S
S1
U
V
V1
W
Z
θ
θ1
θ2
θ3
MILLIMETERS
MIN
MAX
14.00 BSC
7.00 BSC
14.00 BSC
7.00 BSC
--1.70
0.05
0.20
1.30
1.50
0.10
0.30
0.45
0.75
0.15
0.23
0.50 BSC
0.07
0.20
0.50 REF
0.08
0.20
16.00 BSC
8.00 BSC
0.09
0.16
16.00 BSC
8.00 BSC
0.20 REF
1.00 REF
0°
7°
0°
—
12° REF
12° REF
Figure 3-3 100-pin Thin Quad Flat Pack (TQFP) Mechanical Information
Preliminary Information
3-6
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Packaging
Ordering Drawings
ORDERING DRAWINGS
Complete mechanical information regarding DSP56011 packaging is available by
facsimile through Motorola's Mfax™ system. Call the following number to obtain
information by facsimile:
Y
(602) 244-6609
AR
The Mfax automated system requests the following information:
•
The receiving facsimile telephone number including area code or country
code
•
The caller’s Personal Identification Number (PIN)
The type of information requested:
–
Instructions for using the system
–
A literature order form
–
Specific part technical information or data sheets
–
Other information described by the system messages
IM
•
IN
Note: For first time callers, the system provides instructions for setting up a PIN,
which requires entry of a name and telephone number.
A total of three documents may be ordered per call.
PR
EL
The DSP56011 100-pin TQFP package mechanical drawing is referenced as 983-02.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
3-7
Packaging
PR
EL
IM
IN
AR
Y
Ordering Drawings
Preliminary Information
3-8
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
SECTION
4
AR
THERMAL DESIGN CONSIDERATIONS
Y
DESIGN CONSIDERATIONS
An estimation of the chip junction temperature, TJ, in °C can be obtained from the
equation:
Where:
IN
Equation 1: T J = T A + ( P D × R θJA )
IM
TA = ambient temperature ˚C
RθJA = package junction-to-ambient thermal resistance ˚C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case
thermal resistance and a case-to-ambient thermal resistance:
Equation 2: R θJA = R θJC + R θCA
EL
Where:
RθJA = package junction-to-ambient thermal resistance ˚C/W
RθJC = package junction-to-case thermal resistance ˚C/W
RθCA = package case-to-ambient thermal resistance ˚C/W
PR
RθJC is device-related and cannot be influenced by the user. The user controls the
thermal environment to change the case-to-ambient thermal resistance, RθCA. For
example, the user can change the air flow around the device, add a heat sink, change
the mounting arrangement on the printed circuit board, or otherwise change the
thermal dissipation capability of the area surrounding the device on a printed circuit
board. This model is most useful for ceramic packages with heat sinks; some 90% of
the heat flow is dissipated through the case to the heat sink and out to the ambient
environment. For ceramic packages, in situations where the heat flow is split between
a path to the case and an alternate path through the printed circuit board, analysis of
the device thermal performance may need the additional modeling capability of a
system level thermal simulation tool.
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
4-1
Design Considerations
Thermal Design Considerations
The thermal performance of plastic packages is more dependent on the temperature
of the printed circuit board to which the package is mounted. Again, if the
estimations obtained from RθJA do not satisfactorily answer whether the thermal
performance is adequate, a system level model may be appropriate.
A complicating factor is the existence of three common ways for determining the
junction-to-case thermal resistance in plastic packages:
To minimize temperature variation across the surface, the thermal resistance
is measured from the junction to the outside surface of the package (case)
closest to the chip mounting area when that surface has a proper heat sink.
•
To define a value approximately equal to a junction-to-board thermal
resistance, the thermal resistance is measured from the junction to where the
leads are attached to the case.
•
If the temperature of the package case (TT) is determined by a thermocouple,
the thermal resistance is computed using the value obtained by the equation
(TJ – TT)/PD.
IN
AR
Y
•
PR
EL
IM
As noted above, the junction-to-case thermal resistances quoted in this data sheet are
determined using the first definition. From a practical standpoint, that value is also
suitable for determining the junction temperature from a case thermocouple reading
in forced convection environments. In natural convection, using the junction-to-case
thermal resistance to estimate junction temperature from a thermocouple reading on
the case of the package will estimate a junction temperature slightly hotter than
actual temperature. Hence, the new thermal metric, Thermal Characterization
Parameter or ΨJT, has been defined to be (TJ – TT)/PD. This value gives a better
estimate of the junction temperature in natural convection when using the surface
temperature of the package. Remember that surface temperature readings of
packages are subject to significant errors caused by inadequate attachment of the
sensor to the surface and to errors caused by heat loss to the sensor. The
recommended technique is to attach a 40-gauge thermocouple wire and bead to the
top center of the package with thermally conductive epoxy.
Preliminary Information
4-2
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Design Considerations
Electrical Design Considerations
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
IN
AR
Y
This device contains protective circuitry to
guard against damage due to high static
voltage or electrical fields. However, normal
precautions are advised to avoid application
of any voltages higher than maximum rated
voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Use the following list of recommendations to assure correct DSP operation:
Provide a low-impedance path from the board power supply to each VCC pin
on the DSP, and from the board ground to each GND pin.
•
Use at least four 0.01–0.1 µF bypass capacitors positioned as close as possible
to the four sides of the package to connect the VCC power source to GND.
•
Ensure that capacitor leads and associated printed circuit traces that connect
to the chip VCC and GND pins are less than 0.5 in per capacitor lead.
•
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for
VCC and GND.
EL
IM
•
Because the DSP output signals have fast rise and fall times, PCB trace lengths
should be minimal. This recommendation particularly applies to the address
and data buses as well as the IRQA, IRQB, and NMI pins. Maximum Printed
Circuit Board (PCB) trace lengths on the order of 6 inches are recommended.
•
Consider all device loads as well as parasitic capacitance due to PCB traces
when calculating capacitance. This is especially critical in systems with higher
capacitive loads that could create higher transient currents in the VCC and
GND circuits.
•
All inputs must be terminated (i.e., not allowed to float) using CMOS levels,
except as noted in Section 1.
•
Take special care to minimize noise levels on the VCCP and GNDP pins.
•
If multiple DSP56011 devices are on the same board, check for cross-talk or
excessive spikes on the supplies due to synchronous operation of the devices.
PR
•
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
4-3
Design Considerations
Power Consumption Considerations
POWER CONSUMPTION CONSIDERATIONS
Current consumption is described by the formula:
where:
AR
Equation 3: I = C × V × f
Y
Power dissipation is a key issue in portable DSP applications. Some of the factors
which affect current consumption are described in this section. Most of the current
consumed by CMOS devices is Alternating Current (AC), which is charging and
discharging the capacitances of the pins and internal nodes.
C = node/pin capacitance
V = voltage swing
f = frequency of node/pin toggle
Example 4-1 Current Consumption
Equation 4:
IN
For an I/O pin loaded with 50 pF capacitance, operating at 5.5 V, and with a 81 MHz clock, toggling
at its maximum possible rate (20 MHz), the current consumption is:
I = 50 × 10
– 12
6
× 5.5 × 20 × 10 = 5.5mA
IM
The Maximum Internal Current (ICCImax) value reflects the typical possible
switching of the internal buses on best-case operation conditions, which is not
necessarily a real application case. The Typical Internal Current (ICCItyp) value
reflects the average switching of the internal buses on typical operating conditions.
EL
For applications that require very low current consumption:
Minimize the number of pins that are switching.
•
Minimize the capacitive load on the pins.
•
Connect the unused inputs to pull-up or pull-down resistors.
•
Disable unused peripherals.
•
Disable unused pin activity.
PR
•
Preliminary Information
4-4
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Design Considerations
Power Consumption Considerations
MAIN
p:MAIN
#$180000,x:$FFFD
#0,r0
#0,r4
#0,r5
#$00FF,m0
#$00FF,m4
AR
#256
r0,x:(r0)+
#256
r4,y:(r4)+
a
l:(r0)+,a
#30
x0,y0,a
x:(r0)+,x0
a,p:(r5)
TP1
y:(r4)+,y0
MAIN
PR
EL
IM
TP1
p:RESET
jmp
org
movep
move
move
move
move
move
nop
rep
move
rep
mov
clr
move
rep
mac
move
jmp
nop
jmp
IN
org
Y
Current consumption test code:
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
4-5
Design Considerations
Power-Up Considerations
POWER-UP CONSIDERATIONS
To power-up the device properly, ensure that the following conditions are met:
Stable power is applied to the device according to the specifications in Table
2-3 (DC Electrical Characteristics).
•
The external clock oscillator is active and stable.
•
RESET is asserted according to the specifications in Table 2-7 (Reset, Stop,
Mode Select, and Interrupt Timing).
•
The following input pins are driven to valid voltage levels: DR, PINIT,
MODA, MODB, and MODC.
AR
Y
•
IN
Care should be taken to ensure that the maximum ratings for all input voltages obey
the restrictions on Table 2-1 (Maximum Ratings), at all phases of the power-up
procedure. This may be achieved by powering the external clock, hardware reset, and
mode selection circuits from the same power supply that is connected to the power
supply pins of the chip.
PR
EL
IM
At the beginning of the hardware reset procedure, the device might consume
significantly more current than the specified typical supply current. This is because of
contentions among the internal nodes being affected by the hardware reset signal
until they reach their final hardware reset state.
Preliminary Information
4-6
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
Design Considerations
Host Port Considerations
HOST PORT CONSIDERATIONS
AR
Host Programming Considerations
Y
Careful synchronization is required when reading multi-bit registers that are written
by another asynchronous system. This is a common problem when two
asynchronous systems are connected. The situation exists in the Host Interface. The
following paragraphs present considerations for proper operation.
Unsynchronized Reading of Receive Byte Registers—When reading receive
byte registers, RXH or RXL, the host program should use interrupts or poll the
RXDF flag which indicates that data is available. This assures that the data in
the receive byte registers will be stable.
•
Overwriting Transmit Byte Registers—The host program should not write to
the transmit byte registers, TXH or TXL, unless the TXDE bit is set, indicating
that the transmit byte registers are empty. This guarantees that the transmit
byte registers will transfer valid data to the HRX register.
•
Synchronization of Status Bits from DSP to Host—HC, HOREQ, DMA, HF3,
HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside the
DSP and read by the host processor (refer to the User’s Manual for descriptions
of these status bits). The host can read these status bits very quickly without
regard to the clock rate used by the DSP, but the state of the bit could be
changing during the read operation. Generally, this is not a system problem,
since the bit will be read correctly in the next pass of any host polling routine.
IM
IN
•
PR
EL
However, if the host asserts HEN for more than timing number 31, with
a minimum cycle time of timing number 31 + 32, then these status bits are
guaranteed to be stable. Exercise care when reading status bits HF3 and HF2
as an encoded pair. If the DSP changes HF3 and HF2 from 00 to 11, there is a
small probability that the host could read the bits during the transition and
receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has
significance, the host could read the wrong combination. Therefore, read the
bits twice and check for consensus.
•
Overwriting the Host Vector—The host program should change the Host
Vector register only when the Host Command bit (HC) is clear. This change
will guarantee that the DSP interrupt control logic will receive a stable vector.
•
Cancelling a Pending Host Command Exception—The host processor may
elect to clear the HC bit to cancel the host command exception request at any
time before it is recognized by the DSP. Because the host does not know
exactly when the exception will be recognized (due to exception processing
synchronization and pipeline delays), the DSP may execute the host
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
4-7
Design Considerations
Host Port Considerations
command exception after the HC bit is cleared. For these reasons, the HV bits
must not be changed at the same time that the HC bit is cleared.
Variance in the Host Interface Timing—The Host Interface (HI) may vary
(e.g. due to the PLL lock time at reset). Therefore, a host which attempts to
load (bootstrap) the DSP should first make sure that the part has completed its
HI port programming (e.g., by setting the INIT bit in ICR then polling it and
waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ
together with the INIT and then polling INIT, ISR, and the HOREQ pin).
AR
DSP Programming Considerations
Y
•
Synchronization of Status Bits from Host to DSP—DMA, HF1, HF0, and
HCP, HTDE, and HRDF status bits are set or cleared by the host processor
side of the interface. These bits are individually synchronized to the DSP
clock. (Refer to the User’s Manual for descriptions of these status bits.)
•
Reading HF0 and HF1 as an Encoded Pair—Care must be exercised when
reading status bits HF0 and HF1 as an encoded pair, (i.e., the four
combinations 00, 01, 10, and 11 each have significance). A very small
probability exists that the DSP will read the status bits synchronized during
transition. Therefore, HF0 and HF1 should be read twice and checked for
consensus.
PR
EL
IM
IN
•
Preliminary Information
4-8
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
SECTION
5
ORDERING INFORMATION
Y
Consult a Motorola Semiconductor sales office or authorized distributor to determine
product availability and to place an order.
Table 5-1 Ordering Information
Package Type
Pin Count
Frequency
(MHz)
Order Number
DSPA56011
5V
Thin Quad Flat Pack
(TQFP)
100
95
XCA56011BU95
DSPB56011
5V
Thin Quad Flat Pack
(TQFP)
100
95
XCB56011BU95
IN
The DSPA56011 and the DSPB56011 include factory-programmed ROM containing support for Dolby AC3 with DVD specifications. These parts can be used only be customers licensed for Dolby AC-3. Future
products in the DSP56011 family will include other ROM-based options. For additional information on
future part development, or to request customer-specific ROM-based support, call your local Motorola
Semiconductor sales office or authorized distributor.
PR
EL
IM
Note:
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Supply
Voltage
Part
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
5-1
OnCE, Mfax, and Symphony are trademarks of Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may
be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights
of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support life, or for any other application in which the
failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer
purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent
regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/Europe/Locations Not Listed:
Motorola Literature Distribution
P.O. Box 5405
Denver, Colorado 80217
303-675-2140
1 (800) 441-2447
Mfax™:
[email protected]
TOUCHTONE (602) 244-6609
US & Canada ONLY (800) 774-1848
Asia/Pacific:
Motorola Semiconductors H.K. Ltd.
8B Tai Ping Industrial Park
51 Ting Kok Road
Tai Po, N.T., Hong Kong
852-26629298
Japan:
Nippon Motorola Ltd.
SPD, Strategic Planning Office
4-32-1, Nishi-Gotanda
Shinagawa-ku, Tokyo 141, Japan
81-3-5487-8488
Technical Resource Center:
1 (800) 521-6274
DSP Helpline
[email protected]
Internet:
http://www.motorola-dsp.com