Samsung DS K6F2008U2E 256kx8 bit super low power and low voltage full cmos static ram Datasheet

K6F2008U2E Family
CMOS SRAM
Document Title
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
Preliminary
0.0
Initial Draft
February 28, 2001
1.0
Finalize
September 27, 2001 Final
2.0
Revise
- Added 48(36)-TBGA-6.00x7.00 products.
April 30, 2002
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 2.0
April 2002
K6F2008U2E Family
CMOS SRAM
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: Full CMOS
• Organization: 256Kx8
• Power Supply Voltage: 2.7~3.3V
• Low Data Retention Voltage: 1.5V(Min)
• Three State Outputs
• Package Type: 32-TSOP1-0813.4F, 48(36)-TBGA-6.00x7.00
The K6F2008U2E families are fabricated by SAMSUNG′s
advanced Full CMOS process technology. The families support
various operating temperature ranges and have various package types for user flexibility of system design. The families also
supports low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed(ns)
Standby
(ISB1, Typ.)
Operating
(ICC1, Max)
Industrial(-40~85°C)
2.7~3.3V
551)/70ns
0.5µA2)
2mA
K6F2008U2E-F
PKG Type
32-TSOP1-0813.4F
48(36)-TBGA-6.00x7.00
1. The parameter is measured with 30pF test load.
2. Typical values are measured at VCC=3.0V, TA =25°C and not 100% tested.
PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-sTSOP
Type1-Forward
Clk gen.
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
Address
A11
A9
A8
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
FUNCTIONAL BLOCK DIAGRAM
2
3
4
5
6
A
A0
A1
CS2
A3
A6
A8
B
I/O5
A2
WE
A4
A7
I/O1
C
I/O6
DNU
A5
D
VSS
VCC
F
I/O7
G
I/O8
H
A9
I/O Circuit
Data
cont
I/O8
Column select
Data
cont
I/O2
Address
VCC
48(36)-TBGA
E
Memory array
1024 rows
256x8 columns
Row
select
I/O1
1
Precharge circuit.
CS1
CS2
WE
OE
VSS
DNU
A17
I/O3
OE
CS1
A16
A15
I/O4
A10
A11
A12
A13
A14
Name
Control
logic
Function
CS1, CS2 Chip Select Input
Name
Function
I/O1~I/O8 Data Inputs/Outputs
OE
Output Enable
Vcc
Power
WE
Write Enable Input
Vss
Ground
A0~A17 Address Inputs
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 2.0
April 2002
K6F2008U2E Family
CMOS SRAM
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
Function
K6F2008U2E-YF55
K6F2008U2E-YF70
32-sTSOP1-F, 55ns, 3.0V, LL
32-sTSOP1-F, 70ns, 3.0V, LL
K6F2008U2E-EF55
K6F2008U2E-EF70
48(36)-TBGA, 55ns, 3.0V, LL
48(36)-TBGA, 70ns, 3.0V, LL
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O
Mode
Power
H
X1)
X1)
X1)
High-Z
Deselected
Standby
X 1)
L
X1)
X1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disable
Active
L
H
L
H
Dout
Read
Active
L
H
X1)
L
Din
Write
Active
1. X means don′t care (Must be high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
Unit
VIN, VOUT
-0.2 to VCC+0.3V
V
Voltage on Vcc supply relative to Vss
VCC
-0.2 to 3.6V
V
Power Dissipation
PD
1.0
W
T STG
-65 to 150
°C
TA
-40 to 85
°C
Voltage on any pin relative to Vss
Storage temperature
Operating Temperature
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 2.0
April 2002
K6F2008U2E Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Symbol
Min
Typ
Max
Unit
Supply voltage
Item
Vcc
2.7
3.0
3.3
V
Ground
Vss
0
0
0
V
Input high voltage
V IH
2.2
-
Vcc+0.22)
V
Input low voltage
V IL
-0.23)
-
0.6
Note:
1. Industrial Product: TA=-40 to 85°C, unless otherwise specified
2. Overshoot: Vcc+2.0V in case of pulse width≤20ns
3. Undershoot: -2.0V in case of pulse width≤20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Min
Typ1)
Max
Unit
Input leakage current
Item
Symbol
ILI
VIN=Vss to Vcc
Test Conditions
-1
-
1
µA
Output leakage current
ILO
CS1=VIH or CS2 =VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
-1
-
1
µA
ICC1
Cycle time=1µs, 100% duty, IIO=0mA, CS1≤0.2V,
CS2≥VCC-0.2V, VIN ≤0.2V or VIN≥VCC-0.2V
-
-
2
mA
ICC2
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL,
CS2=VIH, VIN=VIL or VIH
Average operating current
Output low voltage
VOL
IOL=2.1mA
Output high voltage
VOH
IOH =-1.0mA
Standby Current(CMOS)
ISB1
Other inputs=Vss to Vcc
1) CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or
2) 0V≤CS2≤0.2V CS2 controlled)
70ns
-
-
15
mA
55ns
-
-
20
mA
-
-
0.4
V
2.4
-
-
V
-
0.5
10
µA
1. Typical value are measured at VCC=3.0V, TA=25°C, and not 100% tested.
4
Revision 2.0
April 2002
K6F2008U2E Family
CMOS SRAM
AC OPERATING CONDITIONS
V TM3)
TEST CONDITIONS(Test Load and Test Input/Output Reference)
R12)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL=100pF+1TTL
CL=30pF+1TTL
CL1)
R23)
1. Including scope and jig capacitance
2. R1=3070Ω, R2=3150Ω
3. VTM =2.8V
AC CHARACTERISTICS(Vcc=2.7~3.3V, Industrial product: TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Min
Read
Max
Min
Max
Read Cycle Time
tRC
55
-
70
-
ns
Address Access Time
tAA
-
55
-
70
ns
Chip Select to Output
tCO
-
55
-
70
ns
Output Enable to Valid Output
tOE
-
25
-
35
ns
Chip Select to Low-Z Output
tLZ
10
-
10
-
ns
tOLZ
5
-
5
-
ns
ns
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Write
Units
70ns
55ns1)
tHZ
0
20
0
25
Output Disable to High-Z Output
tOHZ
0
20
0
25
ns
Output Hold from Address Change
tOH
10
-
10
-
ns
Write Cycle Time
tWC
55
-
70
-
ns
Chip Select to End of Write
tCW
45
-
60
-
ns
Address Set-up Time
tAS
0
-
0
-
ns
Address Valid to End of Write
tAW
45
-
60
-
ns
Write Pulse Width
tWP
40
-
50
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
20
0
20
ns
Data to Write Time Overlap
tDW
25
-
30
-
ns
Data Hold from Write Time
tDH
0
-
0
-
ns
End Write to Output Low-Z
tOW
5
-
5
-
ns
1. The parameter is measured with 30pF test load.
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Symbol
VDR
Data retention current
IDR
Data retention set-up time
tSDR
Recovery time
tRDR
Test Condition
CS1≥Vcc-0.2V1)
Vcc=1.5V,
CS1≥Vcc-0.2V 1)
See data retention waveform
Min
Typ2)
Max
Unit
1.5
-
3.3
V
µA
-
0.5
2
0
-
-
tRC
-
-
ns
1. 1) CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or
2) 0≤CS2≤0.2V(CS2 controlled).
2. Typical value are measured at TA=25°C and not 100% tested.
5
Revision 2.0
April 2002
K6F2008U2E Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
Data out
High-Z
tOHZ
tOLZ
tLZ
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 2.0
April 2002
K6F2008U2E Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tWR(4)
tCW(2)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1
Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
tAW
CS2
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
7
Revision 2.0
April 2002
K6F2008U2E Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
tAW
CS2
tWP(2)
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2)
applied in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC
tSDR
Data Retention Mode
tRDR
2.7V
2.2V
VDR
CS1≥VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
2.7V
CS2
tSDR
tRDR
VDR
CS2≤0.2V
0.4V
GND
8
Revision 2.0
April 2002
K6F2008U2E Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
0.20
0.008
+0.10
-0.05
+0.004
-0.002
0.10
MAX
0.004
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
13.40 ±0.20
0.528 ±0.008
#1
#32
0.50
0.0197
#16
0.25
)
0.010
8.00
0.315
8.40
0.331 MAX
(
#17
1.00 ±0.10
0.039 ±0.004
0.25
TYP
0.010
11.80 ±0.10
0.465 ±0.004
+0.10
-0.05
0.006 +0.004
-0.002
0.15
0.05
0.002 MIN
1.20
0.047 MAX
0~8°
0.45~0.75
0.018~0.030
(
9
0.50
)
0.020
Revision 2.0
April 2002
K6F2008U2E Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters
48(36) TAPE BALL GRID ARRAY(0.75mm ball pitch)
Top View
Bottom View
B
B
B1
6
5
4
3
2
1
A
B
#A1
C
C
C
C1
D
E
C1/2
F
G
H
B/2
Detail A
Side View
A
Y
0.55/Typ.
E1
E
0.35/Typ.
E2
D
C
Min
Typ
Max
A
-
0.75
-
B
5.90
6.00
6.10
B1
-
3.75
-
C
6.90
7.00
7.10
C1
-
5.25
-
D
0.40
0.45
0.50
E
0.80
0.90
1.00
E1
-
0.55
-
E2
0.30
0.35
0.40
Y
-
-
0.08
Notes.
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ: Typical
5. Y is coplanarity: 0.08(Max)
10
Revision 2.0
April 2002
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