Samsung DS K7R323682M 1mx36 & 2mx18 & 4mx9 qdrtm ii b2 sram Datasheet

K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
Document Title
1Mx36-bit, 2Mx18-bit, 4Mx9-bit QDRTM II b2 SRAM
Revision History
History
Draft Date
Remark
0.0
1. Initial document.
June, 30 2001
Advance
0.1
1.
2.
3.
4.
5.
6.
Dec. 5 2001
Preliminary
0.2
1. Update current characteristics in DC electrical characteristics
2. Change AC timing characteristics
3. Update JTAG instruction coding and diagrams
July, 29. 2002
Preliminary
0.3
1.
2.
3.
4.
5.
Add 4Mx9 Organization.
Add -FC25 part (Part Number, Idd, AC Characteristics)
Add AC electrical characteristics.
Change AC timing characteristics.
Change DC electrical characteristics(ISB1)
Sep. 6. 2002
Preliminary
0.4
1.
2.
3.
4.
Change the data Setup/Hold time.
Change the Access Time.(tCHQV, tCHQX, etc.)
Change the Clock Cycle Time.(MAX value of tKHKH)
Change the JTAG instruction coding.
Oct. 7. 2002
Preliminary
0.5
1. Change the Boundary scan exit order.
2. Change the AC timing characteristics(-25, -20)
3. Correct the Overshoot and Undershoot timing diagrams.
Dec. 16, 2002
Preliminary
0.6
1. Change the JTAG Block diagram
Dec. 26, 2002
Preliminary
0.7
1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)
3. Change the Isb1 current.
Mar. 20, 2003
Preliminary
0.8
1. Change the Maximum Clock cycle time.
2. Correct the 165FBGA package ball size.
April. 4, 2003
Preliminary
1.0
1. Final spec release
Oct. 31, 2003
Final
2.0
1. Delete the x8 Org. Part
Dec. 1, 2003
Final
Rev. No.
Pin name change from DLL to Doff.
Vddq range change from 1.5V to 1.5V~1.8V.
Update JTAG test conditions.
Reserved pin for high density name change from NC to Vss/SA
Delete AC test condition about Clock Input timing Reference Level
Delete clock description on page 2 and add HSTL I/O comment
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
1Mx36-bit, 2Mx18-bit, 4Mx9-bit QDRTM II b2 SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future
freguency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O.
• Separate independent read and write data ports
with concurrent read and write operation
• HSTL I/O
• Full data coherency, providing most current data .
• Synchronous pipeline read with self timed early write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
• Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
• Single address bus.
• Byte write (x9, x18, x36) function.
• Sepatate read/write control pin(R and W)
• Simple depth expansion with no data contention.
• Programmable output impenance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
Part
Number
Cycle
Time
Access
Time
Unit
K7R323682M-FC20
5.0
0.45
ns
K7R323682M-FC16
6.0
0.50
ns
K7R321882M-FC20
5.0
0.45
ns
K7R321882M-FC16
6.0
0.50
ns
K7R320982M-FC20
5.0
0.45
ns
K7R320982M-FC16
6.0
0.50
ns
Organization
X36
X18
X9
FUNCTIONAL BLOCK DIAGRAM
K
K
C
C
1Mx36
(2Mx18)
MEMORY
ARRAY
72
(or 36)
72
(or 36)
OUTPUT DRIVER
4(or 2)
CTRL
LOGIC
WRITE DRIVER
19
(or 20)
OUTPUT SELECT
R
W
BW X
ADD
REG
36 (or 18)
OUTPUT REG
ADDRESS
36 (or 18)
SENSE AMPS
19 (or 20)
DATA
REG
WRITE/READ DECODE
36 (or 18)
D(Data in)
36 (or 18)
Q(Data Out)
CQ, CQ
(Echo Clock out)
CLK
GEN
SELECT OUTPUT CONTROL
Notes: 1. Numbers in ( ) are for x18 device, x9 device also the same with appropriate adjustments of depth and width.
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung techno logy.
-2-
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
PIN CONFIGURATIONS(TOP VIEW)
1
2
3
A
CQ
V SS /SA*
B
Q27
Q18
C
D27
D
D28
E
F
G
D30
H
Doff
K7R323682M(1Mx36)
4
5
6
7
8
9
10
11
NC/SA*
W
BW 2
K
BW 1
D18
SA
BW 3
K
BW 0
R
SA
V SS /SA*
CQ
SA
D17
Q17
Q8
Q28
D19
V SS
SA
SA
SA
V SS
D20
Q19
V SS
V SS
V SS
V SS
V SS
D16
Q7
D8
Q16
D15
D7
Q29
D29
Q20
V DDQ
V SS
V SS
V SS
V DDQ
Q30
Q21
D21
V DDQ
V DD
V SS
V DD
V DDQ
Q15
D6
Q6
D14
Q14
Q5
D22
Q22
V DDQ
V DD
V SS
V DD
V DDQ
Q13
D13
D5
V REF
V DDQ
V DDQ
V DD
V SS
V DD
V DDQ
V DDQ
V REF
ZQ
J
D31
Q31
D23
V DDQ
V DD
V SS
V DD
V DDQ
D12
Q4
D4
K
Q32
D32
Q23
V DDQ
V DD
V SS
V DD
V DDQ
Q12
D3
Q3
L
Q33
Q24
D24
V DDQ
V SS
V SS
V SS
V DDQ
D11
Q11
Q2
M
D33
Q34
D25
V SS
V SS
V SS
V SS
V SS
D10
Q1
D2
N
D34
D26
Q25
V SS
SA
SA
SA
V SS
Q10
D9
D1
P
Q35
D35
Q26
SA
SA
C
SA
SA
Q9
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
Notes : 1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 3A for 72Mb, 10A for 144Mb and 2A for 288Mb.
2. BW 0 controls write to D0:D8, BW 1 controls write to D9:D17, BW 2 controls write to D18:D26 and BW 3 controls write to D27:D35.
PIN NAME
SYMBOL
PIN NUMBERS
DESCRIPTION
K, K
6B, 6A
Input Clock
NOTE
C, C
6P, 6R
Input Clock for Output Data
CQ, CQ
11A, 1A
Output Echo Clock
1
Doff
1H
DLL Disable when low
SA
9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
Address Inputs
D0-35
10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L
9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N
1C,1D,2E,1G,1J,2K,1M,1N,2P
Data Inputs
Q0-35
11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L
9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N
3P,1B,2C,1E,1F,2J,1K,1L,2M,1P
Data Outputs
W
4A
Write Control Pin,active when low
R
8A
Read Control Pin,active when low
B W0, BW 1,BW 2 , B W3
7B,7A,5A,5B
Block Write Control Pin,active when low
V REF
2H,10H
Input Reference Voltage
ZQ
11H
Output Driver Impedance Control Input
V DD
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply ( 1.8 V )
V DDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
V SS
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M,
8M,4N,8N
Ground
TMS
10R
JTAG Test Mode Select
TDI
11R
JTAG Test Data Input
TCK
2R
JTAG Test Clock
TDO
1R
JTAG Test Data Output
NC
3A
No Connect
2
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VD D output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-3-
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7R321882M(2Mx18)
1
2
3
4
5
6
A
CQ
V SS /SA*
B
NC
Q9
C
NC
D
NC
E
NC
F
NC
7
8
9
10
11
SA
W
BW 1
K
NC
D9
SA
NC
K
BW 0
R
SA
V SS /SA*
CQ
SA
NC
NC
Q8
NC
D10
V SS
SA
SA
SA
V SS
D11
Q10
V SS
V SS
V SS
V SS
V SS
NC
Q7
D8
NC
NC
D7
NC
Q11
V DDQ
V SS
V SS
V SS
V DDQ
Q12
D12
V DDQ
V DD
V SS
V DD
V DDQ
NC
D6
Q6
NC
NC
Q5
G
NC
D13
Q13
V DDQ
V DD
V SS
V DD
V DDQ
NC
NC
D5
H
Doff
V REF
V DDQ
V DDQ
V DD
V SS
V DD
V DDQ
V DDQ
V REF
ZQ
J
NC
NC
D14
V DDQ
V DD
V SS
V DD
V DDQ
NC
Q4
D4
K
NC
NC
Q14
V DDQ
V DD
V SS
V DD
V DDQ
NC
D3
Q3
L
NC
Q15
D15
V DDQ
V SS
V SS
V SS
V DDQ
NC
NC
Q2
M
NC
NC
D16
V SS
V SS
V SS
V SS
V SS
NC
Q1
D2
N
NC
D17
Q16
V SS
SA
SA
SA
V SS
NC
NC
D1
P
NC
NC
Q17
SA
SA
C
SA
SA
NC
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
Notes: 1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 10A for 72Mb and 2A for 144Mb.
2. BW 0 controls write to D0:D8 and BW 1 controls write to D9:D17.
PIN NAME
SYMBOL
PIN NUMBERS
DESCRIPTION
K, K
6B, 6A
Input Clock
NOTE
C, C
6P, 6R
Input Clock for Output Data
CQ, CQ
11A, 1A
Output Echo Clock
Doff
1H
DLL Disable when low
SA
3A,9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
Address Inputs
D0-17
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,
3F,2G,3J,3L,3M,2N
Data Inputs
Q0-17
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,
2F,3G,3K,2L,3N,3P
Data Outputs
W
4A
Write Control Pin,active when low
R
8A
Read Control Pin,active when low
B W0, BW 1
7B, 5A
Block Write Control Pin,active when low
V REF
2H,10H
Input Reference Voltage
ZQ
11H
Output Driver Impedance Control Input
V DD
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply ( 1.8 V )
V DDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
V SS
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
TMS
10R
JTAG Test Mode Select
TDI
11R
JTAG Test Data Input
TCK
2R
JTAG Test Clock
TDO
1R
JTAG Test Data Output
NC
7A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9F,
10F,1G,9G,10G,1J,2J,9J,1K,2K,9J,1L,9L,10L,1M,2M,
9M,1N,9N,10N,1P,2P,9P
No Connect
1
2
3
Notes: 1. C, C, K or K cannot be set to V R E F voltage.
2. When ZQ pin is directly connected to VD D output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-4-
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7R320982M(4Mx9)
1
2
3
4
5
6
A
CQ
V SS /SA*
B
NC
NC
C
NC
D
NC
E
F
7
8
9
10
11
SA
W
NC
K
NC
R
NC
SA
NC
K
BW
SA
SA
SA
CQ
NC
NC
Q3
NC
NC
V SS
SA
SA
SA
V SS
NC
NC
D3
D4
NC
V SS
V SS
V SS
V SS
V SS
NC
NC
NC
NC
NC
Q4
V DDQ
V SS
V SS
V SS
V DDQ
NC
D2
Q2
NC
NC
NC
V DDQ
V DD
V SS
V DD
V DDQ
NC
NC
NC
G
NC
D5
Q5
V DDQ
V DD
V SS
V DD
V DDQ
NC
NC
NC
H
Doff
V REF
V DDQ
V DDQ
V DD
V SS
V DD
V DDQ
V DDQ
V REF
ZQ
J
NC
NC
NC
V DDQ
V DD
V SS
V DD
V DDQ
NC
Q1
D1
K
NC
NC
NC
V DDQ
V DD
V SS
V DD
V DDQ
NC
NC
NC
L
NC
Q6
D6
V DDQ
V SS
V SS
V SS
V DDQ
NC
NC
Q0
M
NC
NC
NC
V SS
V SS
V SS
V SS
V SS
NC
NC
D0
N
NC
D7
NC
V SS
SA
SA
SA
V SS
NC
NC
NC
P
NC
NC
Q7
SA
SA
C
SA
SA
NC
D8
Q8
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
Notes: 1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 2A for 72Mb.
2. BW controls write to D0:D8 .
PIN NAME
SYMBOL
PIN NUMBERS
DESCRIPTION
K, K
6B, 6A
Input Clock
C, C
6P, 6R
Input Clock for Output Data
CQ, CQ
11A, 1A
Output Echo Clock
Doff
1H
DLL Disable when low
Address Inputs
NOTE
1
SA
3A,9A,10A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
D0-8
11M,11J,10E,11C,2D,2G,3L,2N,10P
Data Inputs
Q0-8
11L,10J,11E,11B,3E,3G,2L,3P,11P
Data Outputs
W
4A
Write Control Pin,active when low
R
8A
Read Control Pin,active when low
BW
7B
Nybble Write Control Pin,active when low
V REF
2H,10H
Input Reference Voltage
ZQ
11H
Output Driver Impedance Control Input
V DD
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply ( 1.8 V )
V DDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
V SS
2A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
TMS
10R
JTAG Test Mode Select
TDI
11R
JTAG Test Data Input
TCK
2R
JTAG Test Clock
TDO
1R
JTAG Test Data Output
NC
7A,5A,1B,2B,3B,5B,9B,10B,1C,2C,3C,9C,10C,1D,3D,9D,10D,11D
1E,2E,9E,1F,2F,3F,9F,10F,11F,1G,9G,10G,11G,1J,2J,3J,9J
1K,2K,3K,10K,11K,9K,1L,9L,10L,1M,2M,3M,9M,10M,1N,3N,9N
10N,11N,1P,2P,9P
No Connect
2
3
Notes: 1. C, C, K or K cannot be set to V R E F voltage.
2. When ZQ pin is directly connected to VD D output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-5-
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
GENERAL DESCRIPTION
The K7R323682M,K7R321882M and K7R320982M are 37,748,736-bits QDR(Quad Data Rate)
Synchronous Pipelined Burst SRAMs.
They are organized as 1,048,576 words by 36bits for K7R323682M, 2,097,152 words by 18 bits for K7R321882M and 4,194,304
words by 9bits for K7R320982M.
The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports
with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram
on every rising edge of K and K , and transfered out of sram on every rising edge of C and C.
And totally independent read and write ports eliminate the need for high speed bus turn around.
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read data are referenced to echo clock ( CQ or CQ ) outputs.
Read address is registered on rising edges of the input K clocks, and write address is
registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 2-bit sequential for both read and write operations.
Synchronous pipeline read and early write enable high speed operations.
Simple depth expansion is accomplished by using R and W for port selection.
Byte write operation is supported with BW 0 and BW 1 ( BW 2 and B W3) pins for x18 ( x36 ) device and only BW pin for x9 device.
Nybble write operation is supported with NW 0 and NW1 pins for x8 device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7R323682M,K7R321882M and K7R320982M are implemented with SAMSUNG's high performance
6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read Operations
Read cycles are initiated by activating R at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 2-bit burst DDR operation, it will access two 36-bit or 18-bit or 9-bit or 8-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K insted of C and C.
When the R is disabled after a read operation, the K7R323682M,K7R321882M and K7R320982M will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS , VDD, VDDQ, VREF, then V I N. VDD and VDDQ can be applied
simultaneously, as long as V DDQ does not exceed V DD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: V IN, V REF, VDDQ, VDD, VSS . VDD and V DDQ can be removed simultaneously, as long as VDDQ
does not exceed V DD by more than 0.5V during power-down.
-6-
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
Write Operations
Write cycles are initiated by activating W at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with following K clock.
For 2-bit burst DDR operation, it will write two 36-bit or 18-bit or 9-bit or 8-bit data words with each write command.
The first "early" data is transfered and registered in to the device synchronous with same K clock rising edge with W presented.
Next burst data is transfered and registered synchronous with following K clock rising edge.
Continuous write operations are initated with K rising edge.
And "early writed" data is presented to the device on every rising edge of both K and K clocks.
When the W is disabled, the K7R323682M,K7R321882M and K7R320982M will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7R323682M, K7R321882M and K7R320982M support byte write operations.
With activating BW 0 or BW 1 ( BW 2 or BW 3 ) in write cycle, only one byte of input data is presented.
In K7R321882M, BW 0 controls write operation to D0:D8, BW 1 controls write operation to D9:D17.
And in K7R323682M BW 2 controls write operation to D18:D26, BW 3 controls write operation to D27:D35.
And in K7R320982M BW controls write operation to D0:D8.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to V SS through a precision resistor(RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250 Ω resistor will give an output impedance of 50 Ω .
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM.
To guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles.
Clock Consideration
K7R323682M,K7R321882M and K7R320982M utlizes internal DLL(Delay-Locked Loops) for maximum output
data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
Single Clock Mode
K7R323682M,K7R321882M and K7R320982M can be operated with the single clock pair K and K,
insted of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high
during operation.
After power up, this device can’t change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
Depth Expansion
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures
as output driver.
-7-
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
STATE DIAGRAM
POWER-UP
READ NOP
READ
WRITE
READ
READ
WRITE
LOAD NEW
READ ADDRESS
ALWAYS
(FIXED)
WRITE NOP
LOAD NEW
WRITE ADDRESS
READ
WRITE
WRITE
ALWAYS
(FIXED)
WRITE
NOP
DDRPORT
WRITE
DDR READ
Notes : 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "READ" refers to read active status with R=Low, "READ " refers to read inactive status with R=high. "WRITE" and " WRITE" are the same case.
3. Read and write state machine can be active simulateneously.
4. State machine control timing sequence is controlled by K.
-8-
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
K
R
D
W
Q
OPERATION
D(A0)
D(A1)
Q(A0)
Q(A1)
Stopped
X
X
Previous state
Previous state
Previous state
Previous state
Clock Stop
↑
H
H
X
X
High-Z
High-Z
No Operation
↑
L
X
X
X
D OUT at C(t+1)
D OUT at C(t+2)
Read
↑
X
L
Din at K(t)
Din at K(t)
X
X
Write
Notes: 1. X means "Don ′t Care".
2. The rising edge of clock is symbolized by ( ↑ ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
WRITE TRUTH TABLE(x18)
K
K
↑
↑
↑
↑
↑
↑
↑
↑
BW0
BW 1
OPERATION
L
L
WRITE ALL BYTEs ( K↑ )
L
L
WRITE ALL BYTEs ( K↑ )
L
H
WRITE BYTE 0 ( K↑ )
L
H
WRITE BYTE 0 ( K↑ )
H
L
WRITE BYTE 1 ( K↑ )
H
L
WRITE BYTE 1 ( K↑ )
H
H
WRITE NOTHING ( K↑ )
H
H
WRITE NOTHING ( K↑ )
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices. x9 device operation is similar except that BW controls D0:D8.
WRITE TRUTH TABLE(x36)
K
K
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
BW0
BW 1
BW2
BW 3
OPERATION
L
L
L
L
WRITE ALL BYTEs ( K ↑ )
L
L
L
L
WRITE ALL BYTEs ( K↑ )
L
H
H
H
WRITE BYTE 0 ( K ↑ )
L
H
H
H
WRITE BYTE 0 ( K↑ )
H
L
H
H
WRITE BYTE 1 ( K ↑ )
H
L
H
H
WRITE BYTE 1 ( K↑ )
H
H
L
L
WRITE BYTE 2 and BYTE 3 ( K↑ )
H
H
L
L
WRITE BYTE 2 and BYTE 3 ( K↑ )
H
H
H
H
WRITE NOTHING ( K↑ )
H
H
H
H
WRITE NOTHING ( K↑ )
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
-9-
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
Voltage on V DD Supply Relative to V SS
V DD
-0.5 to 2.9
V
Voltage on V DDQ Supply Relative to V SS
V DDQ
-0.5 to V DD
V
Voltage on Input Pin Relative to VSS
V IN
-0.5 to VDD+0.3
V
Storage Temperature
TSTG
-65 to 150
°C
Operating Temperature
T OPR
0 to 70
°C
Storage Temperature Range Under Bias
TBIAS
-10 to 85
°C
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operati ng sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VD D during normal operation.
DC ELECTRICAL CHARACTERISTICS (VDD =1.8V ±0.1V, T A=0°C to +70°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT NOTES
Input Leakage Current
IIL
V DD=Max ; V IN=V SS to V DDQ
-2
+2
µA
Output Leakage Current
IOL
Output Disabled,
-2
+2
µA
Operating Current (x36): DDR
ICC
Operating Current (x18): DDR
ICC
Operating Current ( x9): DDR
ICC
Standby Current(NOP): DDR
ISB1
V DD=Max , IOUT=0mA
-20
-
870
Cycle Time ≥ tKHKH Min
-16
-
740
V DD=Max , IOUT=0mA
-20
-
760
Cycle Time ≥ tKHKH Min
-16
-
650
V DD=Max , IOUT=0mA
-20
-
720
Cycle Time ≥ tKHKH Min
-16
-
620
Device deselected, I OUT=0mA,
f=Max,
-20
-
300
All Inputs ≤ 0.2V or ≥ V DD-0.2V
-16
-
270
mA
1,5
mA
1,5
mA
1,5
mA
1,6
Output High Voltage
V OH1
V DDQ /2-0.12 V DDQ/2+0.12
V
2,7
Output Low Voltage
V OL1
V DDQ /2-0.12 V DDQ/2+0.12
V
3,7
Output High Voltage
V OH2
IOH=-1.0mA
V DDQ-0.2
V DDQ
V
4
Output Low Voltage
V OL2
IOL =1.0mA
V SS
0.2
V
4
Input Low Voltage
V IL
-0.3
V REF-0.1
V
8,9
Input High Voltage
V IH
V REF+0.1
V DDQ +0.3
V
8,10
Notes: 1. Minimum cycle. IOUT =0mA.
2. |I OH |=(VDDQ /2)/(RQ/5) ±15% for 175 Ω ≤ RQ ≤ 350Ω .
3. |I OL |=(VDDQ /2)/(RQ/5) ±15% for 175Ω ≤ RQ ≤ 350Ω.
4. Minimum Impedance Mode when ZQ pin is connected to VDDQ .
5. Operating current is calculated with 50% read cycles and 50% write cycles.
6. Standby Current is only after all pending read and write burst opeactions are completed.
7. Programmable Impedance Mode.
8. These are DC test criteria. DC design criteria is V R E F±50mV. The AC VIH /V IL levels are defined separately for measuring timing parameters.
9. V IL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).
10. VIH (Max)DC= V DDQ+0.3, V IH (Max)AC=V DDQ+0.85V(pulse width ≤ 3ns).
- 10 -
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
AC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA =0°C to +70°C)
PARAMETER
MAX
UNIT
NOTES
V REF + 0.2
-
V
1,2
-
V REF - 0.2
V
1,2
SYMBOL
MIN
Input High Voltage
V IH (AC)
Input Low Voltage
V IL (AC)
Notes: 1. This condition is for AC function test only, not for AC parameter test.
2. To maintain a valid level, the transitioning edge of the input must :
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or V IH(DC)
Overershoot Timing
Undershoot Timing
20% t KHKH (MIN)
V IH
V DDQ+0.5V
V DDQ+0.25V
V SS
V DDQ
V SS -0.25V
V SS-0.5V
20% tKHKH (MIN)
V IL
Note: For power-up, V IH ≤ VDDQ +0.3V and V D D ≤ 1.7V and VDDQ ≤ 1.4V t ≤ 200ms
OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C)
PARAMETER
SYMBOL
Min
MAX
UNIT
V DD
1.7
1.9
V
V DDQ
1.4
1.9
V
Reference Voltage
V REF
0.68
0.95
V
Ground
V SS
0
0
V
Supply Voltage
AC TEST CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Symbol
Value
Unit
V DD
1.7~1.9
V
V DDQ
1.4~1.9
V
Input High/Low Level
V IH/VIL
1.25/0.25
V
Input Reference Level
V REF
0.75
V
Input Rise/Fall Time
TR/T F
0.3/0.3
ns
V DDQ /2
V
Output Timing Reference Level
AC TEST OUTPUT LOAD
VREF
0.75V
VDDQ /2
50Ω
SRAM
Zo=50Ω
250Ω
ZQ
Note: Parameters are tested with RQ=250Ω
- 11 -
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
AC TIMING CHARACTERISTICS (VDD =1.8V±0.1V, TA=0°C to +70°C)
PARAMETER
SYMBOL
-20
-16
UNITS NOTES
MIN
MAX
MIN
MAX
5.00
7.88
6.00
8.40
ns
0.20
ns
Clock
Clock Cycle Time (K, K, C, C)
tKHKH
Clock Phase Jitter (K, K, C, C)
tKC var
Clock High Time (K, K , C, C)
tKHKL
2.00
2.40
ns
Clock Low Time (K, K, C, C)
tKLKH
2.00
2.40
ns
Clock to Clock (K↑ → K↑, C↑ → C↑)
tKHKH
2.20
Clock to data clock (K ↑ → C↑, K↑→ C↑)
tKHCH
0.00
DLL Lock Time (K, C)
tKC lock
1024
1024
cycle
K Static to DLL reset
tKC reset
30
30
ns
0.20
2.70
2.30
0.00
5
ns
2.80
ns
6
Output Times
C, C High to Output Valid
tCHQV
0.45
C, C High to Output Hold
tCHQX
C, C High to Echo Clock Valid
tCHCQV
-0.45
C, C High to Echo Clock Hold
tCHCQX
CQ, CQ High to Output Valid
tCQHQV
CQ, CQ High to Output Hold
tCQHQX
C, High to Output High-Z
tCHQZ
C, High to Output Low-Z
tCHQX1
-0.45
Address valid to K rising edge
tAVKH
Control inputs valid to K rising edge
tIVKH
Data-in valid to K, K rising edge
0.50
-0.50
0.45
-0.45
0.50
-0.50
0.35
-0.35
3
ns
3
ns
ns
0.40
-0.40
0.45
ns
ns
ns
0.50
ns
3
-0.50
ns
3
0.40
0.50
ns
0.40
0.50
ns
tDVKH
0.40
0.50
ns
K rising edge to address hold
tKHAX
0.40
0.50
ns
K rising edge to control inputs hold
tKHIX
0.40
0.50
ns
K, K rising edge to data-in hold
tKHDX
0.40
0.50
ns
Setup Times
2
Hold Times
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signal are R and W.
In case of BW 0 ,BW 1 ( BW 2, BW 3 , also for x36) signal follow the data setup/hold times.
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention beacuse tCHQX 1 is a MIN parameter that is worst case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
- 12 -
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
PIN CAPACITANCE
PRMETER
SYMBOL
TESTCONDITION
Typ
Max
Unit
C IN
V IN=0V
4
5
pF
Input and Output Capacitance
C OUT
V OUT =0V
6
7
pF
Clock Capacitance
CCLK
-
5
6
pF
Address Control Input Capacitance
NOTES
Note: 1. Parameters are tested with RQ=250 Ω and V DDQ=1.5V.
2. Periodically sampled and not 100% tested.
THERMAL RESISTANCE
PRMETER
SYMBOL
Typ
Unit
Junction to Ambient
θ JA
20.8
°C/W
Junction to Case
θJC
2.3
°C/W
Junction to Pins
θ JB
4.3
°C/W
NOTES
Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site
thermal impedance. TJ=T A + PD x θ JA
APPLICATION INRORMATION
R=250Ω
ZQ R=250Ω
SRAM#1
Vt
D
SA
R
CQ
CQ
Q
R W BW0 BW1 C C K K
Data In
Data Out
Address
R
W
BW
SRAM#4
CQ
CQ
Q
RW BW 0 BW1 C C K K
D
SA
R
ZQ
ZQ
Vt
Vt
MEMORY
CONTROLLER
Return CLK
Source CLK
Return CLK
Source CLK
SRAM1
SRAM1
SRAM4
SRAM4
Input
Input
Input
Input
Vt
Vt
R=50Ω Vt=VREF
CQ
CQ
CQ
CQ
- 13 -
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
TIMING WAVE FORMS OF READ AND NOP
READ
READ
NOP
READ
NOP
tKHKH
t KLKH
K
t K HKH
tKHKL
K
t A V K H t KHAX
A1
SA
A2
A3
tIVKH t KHIX
R
t CHQX 1
Q1-1
Q(Data Out)
t KHKH
t KHCH
tKLKH
tCHQV
Q1-2
Q2-1
Q2-2
t CHQX
Q3-1
t CHQZ
C
t KHKL
tKH K H
C
t CHCQV
t CHQV
tC QHQV
CQ
CQ
tC H C Q X
t CQHQX
tC H C Q V
t CHCQX
Don′t Care
Undefined
Note : 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.
2. Outputs are disabled one cycle after a NOP.
TIMING WAVE FORMS OF WRITE AND NOP
WRITE
WRITE
NOP
WRITE
NOP
t KHKH
t KLKH
K
t KH K H
t KHKL
K
tA V K H
A1
SA
t KHAX
A2
A3
tIVKH t KHIX
W
t KHIX
D(Data In)
D1-1
D1-2
D2-1
D2-2
D3-1
tDVKH
D3-2
tKHDX
Don ′t Care
Undefined
Note: 1.D1-1 refers to input to address A1+0, D1-2 refers to input to address A1+1, i.e the next internal burst address following A1+ 0.
2. BWx ( NWx ) assumed active.
- 14 -
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
TIMING WAVE FORMS OF READ, WRITE AND NOP
READ
WRITE
READ
WRITE
READ
WRITE
NOP
WRITE
NOP
K
K
SA
A1
A2
A3
A4
A5
A6
D2-1
D2-2
D4-1
D4-2
D6-1
D6-2
A7
W
R
D(Data In)
Q(Data Out)
Q1-1
Q1-2
D7-1
Q3-1
D7-2
Q3-2
Q5-1
Q5-2
C
C
CQ
CQ
Don′t Care
Undefined
Note: 1. If address A1=A2, data Q1-1=D2-1, data Q1-2=D2-2.
Write data is forwarded immediately as read results.
2.BWx ( NWx ) assumed active.
- 15 -
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1
IR0
Instruction
TDO Output
Notes
0
0
0
EXTEST
Boundary Scan Register
1
0
0
1
IDCODE
Identification Register
3
0
1
0
SAMPLE-Z
Boundary Scan Register
2
A,D
0
1
1
RESERVED
Do Not Use
6
K,K
1
0
0
SAMPLE
Boundary Scan Register
5
1
0
1
RESERVED
Do Not Use
6
1
1
0
RESERVED
Do Not Use
6
1
1
1
BYPASS
Bypass Register
4
C,C
SRAM
CORE
Q
CQ
CQ
TDI
BYPASS Reg.
TDO
Identification Reg.
Instruction Reg.
Control Signals
TMS
TCK
TAP Controller
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to V SS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
TAP Controller State Diagram
1
Test Logic Reset
0
0
Run Test Idle
1
1
Select DR
0
Exit2 DR
1
1
Update DR
0
- 16 -
1
Capture IR
0
0
Shift IR
1
1
Exit1 DR
0
Pause DR
1
Select IR
0
1
Capture DR
0
Shift DR
1
1
1
0
0
0
Exit1 IR
0
Pause IR
1
Exit2 IR
1
Update IR
1
0
0
0
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
ID Register
Boundary Scan
1Mx36
3 bits
1 bit
32 bits
109 bits
2Mx18
3 bits
1 bit
32 bits
109 bits
4Mx9
3 bits
1 bit
32 bits
109 bits
ID REGISTER DEFINITION
Part
Revision Number
(31:29)
Part Configuration
(28:12)
Samsung JEDEC Code
(11: 1)
Start Bit(0)
1Mx36
000
00def0wx0t0q0b0s0
00001001110
1
2Mx18
000
00def0wx0t0q0b0s0
00001001110
1
4Mx9
000
00def0wx0t0q0b0s0
00001001110
1
Note : Part Configuration
/def=010 for 36Mb, /wx=11 for x36, 10 for x18, 00 for x9.
/t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O
BOUNDARY SCAN EXIT ORDER
ORDER
PIN ID
ORDER
PIN ID
1
2
3
4
5
6
7
6R
6P
6N
7P
7N
7R
8R
37
38
39
10D
9E
10C
8
9
10
11
12
13
14
15
8P
9R
11P
10P
10N
9P
10M
11N
40
41
42
43
44
45
46
47
48
11D
9C
9D
11B
11C
9B
10B
11A
10A
16
17
18
19
20
21
22
23
24
9M
9N
11L
11M
9L
10L
11K
10K
9J
49
50
51
52
53
54
55
56
9A
8B
7C
6C
8A
7A
7B
6B
25
26
27
28
29
30
31
32
9K
10J
11J
11H
10G
9G
11F
11G
57
58
59
60
61
62
63
64
65
6A
5B
5A
4A
5C
4B
3A
2A
1A
33
34
35
36
9F
10F
11E
10E
66
67
68
69
70
71
72
2B
3B
1C
1B
3D
3C
1D
Note : 1. NC pins are read as "X" ( i.e. don′t care.)
- 17 -
ORDER
73
PIN ID
2C
74
75
76
77
78
79
80
81
82
3E
2D
2E
1E
2F
3F
1G
1F
3G
83
84
85
86
87
88
89
90
2G
1H
1J
2J
3K
3J
2K
1K
91
92
93
94
95
96
97
98
99
2L
3L
1M
1L
3N
3M
1N
2M
3P
100
101
102
103
104
105
106
107
2N
2P
1P
3R
4R
4P
5P
5N
108
109
5R
Internal
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
V DD
1.7
Input High Level
VI H
1.3
1.8
1.9
V
-
V DD+0.3
V
Input Low Level
V IL
-0.3
Output High Voltage(IOH=-2mA)
VO H
1.4
-
0.5
V
-
V DD
V
Output Low Voltage(IOL=2mA)
V OL
V SS
-
0.4
V
Note
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Symbol
Min
Unit
Input High/Low Level
Parameter
V IH/VIL
1.8/0.0
V
Input Rise/Fall Time
TR/TF
1.0/1.0
ns
0.9
V
Input and Output Timing Reference Level
Note
1
Note: 1. See SRAM AC test output load on page 11.
JTAG AC Characteristics
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tCHCH
50
-
ns
TCK High Pulse Width
tCHCL
20
-
ns
TCK Low Pulse Width
tCLCH
20
-
ns
TMS Input Setup Time
tMVCH
5
-
ns
TMS Input Hold Time
tCHMX
5
-
ns
TDI Input Setup Time
tDVCH
5
-
ns
TDI Input Hold Time
tCHDX
5
-
ns
SRAM Input Setup Time
tSVCH
5
-
ns
SRAM Input Hold Time
tCHSX
5
-
ns
Clock Low to Output Valid
tCLQV
0
10
ns
Note
JTAG TIMING DIAGRAM
TCK
tC H C H
tC H C L
t MVCH
t CHMX
t DVCH
tC H D X
t SVCH
t CHSX
tC L C H
TMS
TDI
PI
(SRAM)
t CLQV
TDO
- 18 -
Dec. 2003
Rev 2.0
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM
165 FBGA PACKAGE DIMENSIONS
15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
B
Top View
A
Side View
C
D
A
G
E
B
F
Bottom View
∅H
E
Symbol
Value
Units
Symbol
Value
Units
A
15 ± 0.1
mm
Note
E
1.0
mm
B
17 ± 0.1
mm
F
14.0
mm
C
1.3 ± 0.1
mm
G
10.0
mm
D
0.35 ± 0.05
mm
H
0.5 ± 0.05
mm
- 19 -
Note
Dec. 2003
Rev 2.0
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