Semtech E6420BBG Per-pin electronics companion dac Datasheet

Edge6420
Per-Pin Electronics
Companion DAC
HIGH-PERFORMANCE PRODUCTS – ATE
Description
Features
64 Total DACs/Package Including:
• Wide Voltage Output Range (17V Range); Useful
for Supervoltage
• 44 Voltage DACs / Package
• 20 Current DACs / Package
• Adjustable Full Scale Range
• Adjustable Output Voltage Offset
• Small 13x13mm BGA Package
• All DACs are Guaranteed Monotonic
The Edge6420 is a monolithic device which has 64
integrated DACs that are designed specifically for all per
channel wide-voltage and current levels needed for pin
electronics inside automatic test equipment. The chip
can also be used for other applications requiring multiple
integrated voltage or current DAC outputs.
Voltage DACs
• Wide voltage (17V range)
• Adjustable full scale range
• Adjustable minimum output
• 13 bits resolution
Applications
Current DACs
• ~3.6 mA full scale range
• Adjustable full scale range
• 6/13 bits resolution
•
•
Test Equipment
Applications requiring multiple programmable
voltage and currents
The DACs are programmed using a serial interface.
The inclusion of 64 total DACs into 1 package offers an
extremely high density, flexible solution normally
implemented using multiple components.
Functional Block Diagram
SDI
Channel 0
VOUT_CH0_[0:10]
DAC 0
IOUT_CH0_[0:4]
Channel 1
CE
VOUT_CH1_[0:10]
IOUT_CH1[0:4]
CK
Channel 2
UPDATE
VOUT_CH2_[0:10]
IOUT_CH2_[0:4]
RESET*
Channel 3
VOUT_CH3_[0:10]
IOUT_CH3_[0:4]
DAC 63
SDO
Revision 4 / April 29, 2002
CK_OUT
1
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
PIN Description
Ball Name
Ball Location
VOUT_CH[0:3]_[0:4]
G13, G15, F14, F13, F15, G3, F1, F2,
F3, E1, J3, J1, K2, K3, K1, J13, K15,
K14, K13, L15
Group A DAC output volages for channels 0 to 3.
VOUT_CH[0:3]_[5:6]
E14, E15, E2, E3, L2, L1, L14, L13
Group B DAC output voltages for channels 0 to 3.
VOUT_CH[0:3]_[7:8]
E13, D14, D1, D2, L3, M2, M15, M14
Group C DAC output voltaqges for channels 0 to 3.
VOUT_CH[0:3]_[9:10]
D15, D13, D3, C1, M1, M3, M13, N15
Group D DAC output voltages for channels 0 to 3.
IOUT_CH[0:3]_[0:1]
C15, C14, B1, C2, N1, N2, P15, N14
Group E DAC output voltages for channels 0 to 3.
IOUT_CH[0:3]_[2:4]
H14, H15, G14, H3, G1, G2, H2, H1,
J2, H13, J15, J14
Group F DAC output voltages for channels 0 to 3.
R_MASTER
P5
Master external resistor used to define the reference current
for the gain and offset setting block for voltage DACs.
R_GAIN_(A,B,C,D,E,F)
P11, R10, N10, P10, R9, N9
Pins for external resistor to set current gain for both voltage
and current output DACs.
R_OFFSET_(A,B,C,D)
R6, P6, N6, R5
Pins for external resistor to set the offset voltage for Group
A, B, C, and D voltage output DAC's.
SDI
B10
Serial data input.
CK
A11
Clock for the input data shift register.
UPDATE
C6
Strobe to transfer the shift register data to the DACs.
CE
A10
Chip enable.
RESET*
C5
Active low chip reset. Sets the DACs to a known default
state.
SDO
B5
Serial Data Out.
CK_OUT
A6
Regenerated clock output for daisy chain purposes.
SCAN_OUT
B11
TEST_MODE
B6
Test mode pin for internal scan.
VREF
C9
Reference input (for a 2.5V band gap).
AVCC
C3, C12, N4, R12
AVDD
C7, N7
VEE
A9, R8, B9, P9
Negative analog voltage supply.
AGND
B8, N8
Analog ground (minimize noise).
SGND
A8, R7
Supply ground.
DVDD
B7, P7
Digital voltage supply.
DGND
C8, P8
Digital supply ground.
 2000 Semtech Corp.
Description
Analog output test pin.
Positive analog voltage supply.
Analog 5V supply.
2
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
PIN Description (continued)
Ball Name
Ball Location
N/C
A1, A2, A3, A4, A5, A7, A12, A13,
A14, A15, B2, B3, B4, B12, B13,
B14, B15, C4, C10, C11, C13, N3,
N5, N11, N12, N13, P1, P2, P3,
P4, P12, P13, P14, R1, R2, R3,
R4, R11, R13, R14, R15
 2000 Semtech Corp.
Description
Not connected.
3
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
PIN Description (continued)
13mm x 13mm CSPBGA Package
A1 Ball Pad
Indicator
E6420
Top View
13 mm x 13 mm CSPBGA
Top View
A2
A1
A
A6
A7
A8
A9
A10
139
136
134
131
128
125
N/C
N/C
N/C
N/C
N/C
CK_OUT
N/C
SGND
VEE
B2
B3
B4
B5
B6
B7
B8
B9
A11
A12
A13
A14
A15
122
119
116
113
111
CE
CK
N/C
N/C
N/C
B10
B11
B12
B13
2
141
138
135
132
129
127
124
121
118
115
112
110
N/C
N/C
N/C
SDO
TEST_MODE
DVDD
AGND
VEE
SDI
SCAN_OUT
N/C
N/C
N/C
C3
C4
C5
5
4
143
140
VOUT_CH1_10
IOUT_CH1_1
AVCC
N/C
D2
D1
D
D3
8
7
VOUT_CH1_7
VOUT_CH1_8
E1
E2
11
E
D4
E3
F1
F2
F3
13
G1
G2
17
G
IOUT_CH1_3
H1
VOUT_CH1_0
H2
H3
19
J2
23
K1
K2
K3
24
L1
L2
28
L3
M2
M3
IOUT_CH2_0
32
VOUT_CH2_8
VOUT_CH2_10
N/C
D10
E9
F8
G7
N3
J6
K5
G9
K6
K7
K8
G10
K9
L5
L6
L7
L8
M5
M6
M7
M8
N4
N5
N6
N7
N8
N/C
AVCC
N/C
R_OFFSET_C
AVDD
AGND
P4
J11
P5
P6
P7
P8
R_GAIN_F
P9
49
52
55
57
N/C
N/C
N/C
N/C
R_MASTER
R_OFFSET_B
DVDD
DGND
VEE
R4
N/C
3
R5
R6
44
47
N/C
R_OFFSET_D
4
5
R7
50
R_OFFSET_A
6
R8
R9
53
56
SGND
VEE
7
4
8
61
R_GAIN_C
P10
46
41
VOUT_CH0_9
F12
G12
H12
J12
K11
K12
L12
M11
M12
R_GAIN_D
VOUT_CH0_5
VOUT_CH0_6
F13
F14
F15
96
VOUT_CH0_2
VOUT_CH0_4
G13
G14
G15
93
IOUT_CH0_4
VOUT_CH0_1
H13
H14
H15
91
IOUT_CH0_2
J13
J14
R_GAIN_E
9
R_GAIN_B
10
J15
K13
K14
VOUT_CH3_1
L13
L14
L15
82
83
VOUT_CH3_6
VOUT_CH3_5
VOUT_CH3_4
M13
M14
M15
N13
79
80
VOUT_CH3_8
76
77
IOUT_CH3_1
R_GAIN_A
N/C
N/C
N/C
R13
75
IOUT_CH3_0
R14
70
VOUT_CH3_10
P15
P14
74
VOUT_CH3_7
N15
N14
69
12
86
VOUT_CH3_2
P13
11
K15
VOUT_CH3_3
66
AVCC
IOUT_CH3_3
85
63
N/C
89
IOUT_CH3_4
N/C
67
IOUT_CH0_3
88
VOUT_CH3_0
N/C
R12
92
IOUT_CH3_2
N/C
64
95
VOUT_CH0_0
71
P12
98
VOUT_CH0_3
68
R11
62
N12
100
VOUT_CH0_7
65
P11
60
R10
59
N11
E15
99
87
N10
43
R3
103
VOUT_CH0_8
90
L11
58
40
 2000 Semtech Corp.
H11
M10
N9
IOUT_CH2_1
P3
D15
102
E14
VOUT_CH3_9
54
2
E13
D14
78
51
1
E12
106
IOUT_CH0_0
94
L10
M9
48
N/C
D13
105
81
45
N/C
G11
K10
L9
42
39
D12
N/C
C15
IOUT_CH0_1
84
35
R2
F11
NOTE: Balls populating the inner
9x9 grid are for improved thermal
H7
H8
H9
dissipation. This middle
grid of H10
balls should be connected to the
VEE plane or left floating. Order
E6420BBG
if populated
J7
J8
J9middle J10
is desired.
H6
J5
G8
38
37
E11
F10
36
R1
D11
E10
F9
33
P2
P1
P
107
AVCC
D9
E8
F7
G6
H5
M4
30
N2
F6
G5
L4
M1
34
114
N/C
29
VOUT_CH2_7
N1
117
N/C
VOUT_CH2_3
VOUT_CH2_5
N
120
97
K4
VOUT_CH2_6
VOUT_CH2_9
123
VREF
25
27
31
F5
J4
VOUT_CH2_0
L
E7
22
IOUT_CH2_4
VOUT_CH2_2
D8
108
C14
101
H4
J3
VOUT_CH2_4
E6
IOUT_CH1_2
21
26
D7
18
VOUT_CH2_1
K
E5
G4
IOUT_CH1_4
J1
J
D6
C13
VOUT_CH1_3
15
IOUT_CH2_2
126
DGND
C12
VOUT_CH0_10
F4
G3
IOUT_CH2_3
130
AVDD
C11
12
16
20
H
133
UPDATE
C10
104
E4
VOUT_CH1_6
VOUT_CH1_2
C9
9
VOUT_CH1_5
VOUT_CH1_1
D5
C8
VOUT_CH1_9
VOUT_CH1_4
F
137
RESET*
C7
6
10
14
C6
N/C
B15
3
C2
109
B14
IOUT_CH1_0
C
R
A5
142
C1
M
A4
144
B1
B
A3
1
R15
72
73
N/C
N/C
N/C
13
14
15
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
PIN Description (continued)
13mm x 13mm CSPBGA Package
A1 Ball Pad
Indicator
Bottom View
15
A15
14
13
A14
A13
12
A12
11
A11
111
113
116
119
122
N/C
N/C
N/C
N/C
CK
CE
B14
B15
B13
B12
108
110
112
115
N/C
N/C
N/C
N/C
C14
C15
106
C13
105
IOUT_CH0_0
IOUT_CH0_1
D15
D14
103
VOUT_CH0_9
VOUT_CH0_8
100
117
N/C
AVCC
N/C
D12
E13
VOUT_CH0_7
F15
F14
F13
VOUT_CH0_2
G14
G13
H15
H14
H13
IOUT_CH3_3
K15
IOUT_CH3_2
J14
J13
J12
IOUT_CH3_4
VOUT_CH3_0
K14
K13
K12
VOUT_CH3_1
VOUT_CH3_2
VOUT_CH3_3
L14
L13
D10
VOUT_CH3_6
M15
M14
M13
N14
E10
F11
G11
H11
J11
K11
L11
N/C
B5
B6
132
DVDD
B4
138
141
SDO
N/C
N/C
C5
C6
AVDD
B2
B3
135
TEST_MODE
C4
143
4
5
UPDATE
RESET*
N/C
AVCC
IOUT_CH1_1
VOUT_CH1_10
D2
D1
D3
D4
D5
M11
N12
N11
65
VOUT_CH3_10
IOUT_CH3_1
N/C
N/C
N/C
P13
P11
P12
74
69
66
63
N/C
N/C
N/C
R_GAIN_A
R14
R12
R13
R11
73
72
70
67
64
N/C
N/C
N/C
AVCC
N/C
 2000 Semtech Corp.
E6
F10
F8
F9
F7
F5
F6
F4
G10
G8
G9
G7
G4
G5
G6
NOTE: Balls populating the inner
9x9
grid are
for improved
thermal
H8
H7
H9
H6
dissipation. This middle grid of
balls should be connected to the
VEE plane or left floating. Order
E6420BBG
middle
J8 if populated
J7
J9
J6
is desired.
H10
J10
K10
K8
K9
K7
H5
VOUT_CH1_8
J4
J5
VOUT_CH1_5
VOUT_CH1_4
F3
F2
F1
VOUT_CH1_1
G2
G1
16
VOUT_CH1_0
IOUT_CH1_4
H3
H2
J3
K4
L8
L9
L7
L5
L6
M10
M8
M9
M7
M5
M6
M4
N10
R_GAIN_C
P10
N8
N9
61
58
R_GAIN_F
R_GAIN_D
R10
IOUT_CH2_3
J2
J1
R_GAIN_B
N4
K2
K1
VOUT_CH2_2
VOUT_CH2_4
L2
L1
VOUT_CH2_6
M3
M2
M1
32
30
VOUT_CH2_10
VOUT_CH2_8
N2
N3
42
35
AGND
AVDD
R_OFFSET_C
N/C
AVCC
N/C
P5
P4
P3
55
52
49
46
43
40
VEE
DGND
DVDD
R_OFFSET_B
R_MASTER
N/C
N/C
R7
R8
59
R_GAIN_E
R6
56
53
VEE
SGND
5
R5
50
R_OFFSET_A
R_OFFSET_D
31
H
J
K
L
M
VOUT_CH2_9
N1
34
33
IOUT_CH2_1
IOUT_CH2_0
P2
P1
36
38
N/C
R2
R3
R4
47
28
27
VOUT_CH2_5
45
P6
26
24
VOUT_CH2_7
48
P7
23
21
K3
57
R9
62
N5
N6
20
19
IOUT_CH2_2
VOUT_CH2_1
51
G
H1
IOUT_CH2_4
54
P8
P9
60
N7
17
IOUT_CH1_3
VOUT_CH2_0
L3
L4
F
VOUT_CH1_2
15
E
14
13
22
K5
K6
11
VOUT_CH1_6
18
D
E1
10
IOUT_CH1_2
C
VOUT_CH1_7
9
G3
H4
8
7
E2
E3
E4
VOUT_CH3_9
68
P14
E5
B
C1
140
D6
E7
3
IOUT_CH1_0
137
29
M12
N13
N/C
C2
C3
A
B1
2
133
130
D7
E8
E9
L10
71
R15
N/C
VOUT_CH2_3
76
IOUT_CH3_0
D8
N/C
78
79
VOUT_CH3_8
E11
77
75
D9
N/C
25
L12
VOUT_CH3_5
P15
DGND
N/C
81
82
VOUT_CH3_4
N15
VREF
CK_OUT
84
85
L15
VOUT_CH3_7
N/C
87
88
80
126
1
129
C7
123
90
91
83
C8
C9
120
144
VOUT_CH1_3
H12
IOUT_CH0_2
86
AGND
142
12
G12
VOUT_CH0_0
89
VEE
139
94
IOUT_CH0_4
J15
SDI
136
VOUT_CH0_3
93
92
B7
1
A1
134
97
VOUT_CH0_1
IOUT_CH0_3
B8
A2
VOUT_CH1_9
F12
96
95
N/C
2
3
A3
101
VOUT_CH0_5
G15
SGND
4
A4
6
E12
VOUT_CH0_6
VOUT_CH0_4
D11
VEE
127
C10
114
131
124
A5
VOUT_CH0_10
99
98
C11
C12
128
B9
5
6
A6
125
121
SCAN_OUT
7
A7
104
E14
E15
B10
118
107
D13
102
B11
A8
A9
109
8
9
10
A10
Actual Size
N
P
N/C
R1
44
41
39
N/C
N/C
N/C
37
R
N/C
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circuit Description
Chip Overview
Grouping of DACs
The Edge6420 provides 64 output levels (44 voltage and
20 current). These outputs can easily be configured to
generate the specific analog voltage and current
requirements for 4 channels of ATE pin electronics
including:
– 3 level driver
– Window comparator
– Active load
– Per pin PMU
without requiring any scaling or shifting via external
components.
DACs are separated into 4 channels of 6 distinct functional
groups. Groups are defined by:
–
–
–
–
Type (voltage or current output)
Resolution (# of bits)
Output range
Output compliance.
Table 1 defines the DACs on a per channel basis:
The Edge6420 has the flexibility to be used in other
configurations for other applications.
Programming of the chip is done using a 4 bit digital
interface comprised of:
– Serial Data In
– Clock
– Update
– Chip Enable.
Group
A
Group
B
Group
C
Group
D
Group
E
Group
F
5 per channel
2 per channel
2 per channel
2 per channel
2 per channel
3 per channel
Type
V
V
V
V
I
I
Resolution
(# of bits)
13
13
13
13
13
6
11.5V
-3.5V to 2.5V
11.5V
-3.5V to 2.5V
17V
-3.5V to 2.5V
11.5V
-3.5V to 2.5V
3.6 mA
–128 LSB
(Note 2)
3.6 mA
0
yes
yes
yes
yes
no
no
±100 µA
±100 µA
±100 µA
±100 µA
–0.2 to AVDD – 2.2V
(Note 3)
–0.2 to AVDD – 2.2V
(Note 3)
Attribute
Total # of
DACs in Group
Output Range:
Max DAC Range (Note 1)
Offset Range
Adjustable Output Offset
Compliance
Note 1:
Note 2:
Note 3:
The max DAC range is achieved through specific AVCC, AVEE, and Gain resistor settings. See the
equations in the "DAC Voltage Output Overview", "DAC Current Output Overview", and specifications for details.
–128 LSB is equivalent to –128 * LSB, where LSB = Range / 213. For max range case of 3.6 mA,
this offset would thus be: –56.26 µA of offset current at Code 0.
Compliance specified in the table is at IOUT = 1.3mA. Maximum compliance is lower at higher currents.
Please refer to specifications for compliance at other output currents.
Table 1. DAC Grouping
 2000 Semtech Corp.
6
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circuit Description (continued)
DAC Voltage Output Overview
Minimum / Maximum Output Voltages
The output voltage of Group A, B, C, and D DACs is
governed by the following equation:
See Table 2 for the minimum and maximum possible
voltages of a voltage output.
VOUT_[A:D] = KG[A:D] * VREF *
R_GAIN_[A:D]
*
R_MASTER
DATA
8192
+ VOFFSET_[A:D]
DAC Setting
MSB ... LSB
VOUT_[A:D] (V)
0000H
VOFFSET_[A:D]
1FFFH
VMAX_[A:D]
Equation 1.
where:
DATA corresponds to the base-10 value of the binary data
loaded into the shift register shown in Figure 2.
KG[A:D] is a multiplying factor that is fixed, as follows:
Table 2. Minimum/Maximum Output Voltages
KGA = 4
KGC = 8
KGB = 4
KGD = 4
where:
VREF = 2.5V
VOFFSET[A:D] is defined in equation 2
Offset
and
The offset for each of the voltage DACs is governed by the
following equation:
VOFFSET_[A:D] = K
V
OFFSET * REF *
VMAX_[A:D] = KG[A:D] * VREF * R_GAIN_[A:D]
R_MASTER
0.5 – R_OFFSET_[A:D]
R_MASTER
Equation 2.
where:
*
8191
8192
+ VOFFSET_[A:D]
Equation 3.
The most negative voltage possible for the Edge6420 is
–3.5V when VEE = –4.5V.
KOFFSET = 2
Resolution
VREF = 2.5V
The resolution of the DACs in Groups A, B, C, and D is:
VRANGE_[A:D] / 213
External Resistors
where VRANGE_[A:D] is defined in Equation 4.
The recommended resistor values for the above equations
are as follows:
R_MASTER = 100KΩ (0.1% precision)
R_GAIN_[A:D] = (0.4 to 1.15) * R_MASTER
Range
The range of the DACs in Groups A, B, C and D is:
VRANGE_[A:D] = KG[A:D] * VREF * R_GAIN_[A:D] *
R_MASTER
8191
8192
R_OFFSET_[A:D] = (0.0 to 1.2) * R_MASTER
Equation 4.
 2000 Semtech Corp.
7
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circuit Description (continued)
Group A DACs
Group D DACs
There are five Group A DACs/channel. Group A DACs have
a centralized offset, gain and range that is independent of
any other group.
There are two Group D DACs/channel. Group D DACs
have a centralized offset, gain and range that is
independent of any other group.
Group A DACs are characterized by 13 bit resolution and
their typical outputs are governed by the following equation:
Group D DACs are characterized by 13 bit resolution and
their typical outputs are governed by the following
equation:
R_GAIN_A
R_MASTER
VOUT_A = 10 *
*
DATA
8192
+ VOFFSET_A
VOUT_D = 10 *
R_GAIN_D
R_MASTER
VOFFSET_D =
5 * .5 –
where:
VOFFSET_A =
5 * .5 –
DATA
8192
*
+ VOFFSET_D
where:
R_OFFSET_A
R_MASTER
R_OFFSET_D
R_MASTER
Note: VREF = 2.5V
Note: VREF = 2.5V
Group B DACs
DAC Current Output Overview
There are two Group B DACs/channel. Group B DACs
have a centralized offset, gain and range that is
independent of any other group.
Group B DACs are characterized by 13 bit resolution and
their typical outputs are governed by the following
equation:.
VOUT_B = 10 *
R_GAIN_B
R_MASTER
*
DATA
8192
5 * .5 –
IOUT_[E:F] =
KG[E:F] * IREF_[E:F] *
DATA
MAX_COUNT_[E:F]
+ IOFFSET_[E:F]
Equation 5.
where:
+ VOFFSET_B
where:
VOFFSET_B =
The output current of Group E and F DACs is governed by
the following equation:
DATA corresponds to the base-10 value of the binary data
loaded into the shift resister in Figure 2.
R_OFFSET_B
R_MASTER
IREF_[E:F] =
VREF
R_GAIN_[E:F]
Note: VREF = 2.5V
KG[E:F] is a multiplying factor that is fixed, as follows:
Group C DACs
KGE = 80
There are two Group C DACs/channel. Group C DACs have
a centralized offset, gain and range that is independent of
any other group'.
Group C DACs are characterized by 13 bit resolution and
their typical outputs are governed by the following equation:
VOUT_C = 20 *
R_GAIN_C
R_MASTER
*
DATA
8192
KGF = 80
VREF = 2.5V
MAX_COUNT_E = 8192
MAX_COUNT_F = 64
+ VOFFSET_C
where:
VOFFSET_C =
5 * .5 –
R_OFFSET_C
R_MASTER
Note: VREF = 2.5V
 2000 Semtech Corp.
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circuit Description (continued)
Offset
The typical offset for each current DAC is governed by the
following equations:
IOFFSET_E
= –
KGE * VREF
R_GAIN_E
128
*
MAX_COUNT_E
Equation 6.
IOFFSET_F = 0
Group E DACs
There are 2 Group E DACs/channel. Group E DACs are
characterized by:
• Current outputs (current flows out of the chip)
• 13 bit resolution
• Fixed offset (–128 * LSB typical)
• Adjustable full scale range (but < 3.6 mA).
The output current equation for Group E DACs is:
IOUT_E =
where:
DATA
8192
*
200
R_GAIN_E
–
3.125
R_GAIN_E
55 kΩ ≤ R_GAIN_E ≤ 156 kΩ
Note: VREF = 2.5V
Group F DACs
There are 3 Group F DACs/channel. Group F DACs are
characterized by:
• Current outputs (current flows out of the chip)
• 6 bit resolution
• Fixed offset (0 typical)
• Adjustable full scale range (but < 3.6 mA).
The output current equation for Group F DACs is:
IOUT_F =
where:
DATA
*
64
200
R_GAIN_F
55 kΩ ≤ R_GAIN_F ≤ 156 kΩ
Note: VREF = 2.5V
 2000 Semtech Corp.
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circuit Description (continued)
Address Map
Address
Channel
Group
Type
Typical Uses
0
1
2
3
4
0
0
0
0
0
A
A
A
A
A
V
V
V
V
V
Driver & Comparator Levels
5
6
0
0
B
B
V
V
PPMU Comparator Thresholds
7
8
0
0
C
C
V
V
PPMU Force Voltage, Flash
Programming Supervoltage
9
10
0
0
D
D
V
V
Load Commutating Voltage
11
12
0
0
E
E
I
I
Load Source and Sink
Programming currents
13
14
15
0
0
0
F
F
F
I
I
I
Chip Bias, Rising/Falling
Slew Rate Adjust
16-31
1
Same format as above for Channel 1.
32-47
2
Same format as above for Channel 2.
48-63
3
Same format as above for Channel 3.
64
N/A
65-255
 2000 Semtech Corp.
All
V/I
Parallel Load for all DACs
Not used (reserved for future upgradability).
10
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circuit Description (continued)
Decode and Individual DAC Update
RESET*
This is a 13-bit latch for DAC
(Note: there are some current output
DACs that require only 6-bit latches)
L
Q
DAC
DAC output #0
DAC
DAC output #1
EN R
L
Q
.
.
.
.
.
.
L
Q64
Q63
.
.
.
Q1
Q0
.
.
.
(for Parallel Load)
.
.
.
EN R
Q
DAC
DAC output #63
EN R
ADDRESS
DECODER
ADDR
13
7
A0:A6
D0:D12
Delay
UPDATE
D
Q
CE
CK
LOAD
R
CENTRAL DAC LATCH
(24 Latches)
RESET
24-BIT SHIFT REGISTER
CK_OUT
SDO
SDI
RESET
RESET*
Programming Logic
Figure 1. DAC Functionality Block Diagram
 2000 Semtech Corp.
11
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circuit Description (continued)
Programming Sequence
Group F uses only 6 bits, and these bits must be
programmed as shown in Figure 2b. 24 clock cycles are
required for programming, with A0 loaded on the first rising
CK edge, and D8 (as shown in Figure 2b) loaded on the
24th rising CK edge.
The DACs are programmed serially (see Figures 1, 2a,
2b, and 3). On each rising edge of CK, SDI is loaded into
a shift register. It requires 24 Clocks to fully load the shift
register (8 address bits + 16 data bits).
As is the case with other groups, a 24th falling edge of
CK24 is required for proper programming of Group F DACs.
For Groups A, B, C, D, and E DACs:
Address and data are loaded LSB first, MSB last. In a 24
clock sequence, A0, as shown in Figure 2a, is loaded into
the shift register on the first CK rising edge, and D15 is
loaded last on the 24th rising CK edge. Note that a 24th
falling CK edge is required to transfer the data from the
Central DAC Latch to the selected DAC latch (See Figure
1).
See detailed Timing Diagrams in the "AC
Characteristics" specifications section.
Chip Enable
For Group F DACs:
CE
low
CE is a synchronous input which determines whether the
Central DAC latch shown in Figure 1 is loaded with data
from the shift register. CE is also necessary to update a
DAC. If CE is high, rising edges of CK load data from the
shift register to an internal latch. If CE is low, central DAC
latch updating is disabled.
Central and Individual DAC Latch "Load" Status
Central and individual DAC latch loading is
disabled
Central and individual DAC latches are loaded
The loading sequence is the same as Groups A-E, but
high
DATA
SDI
D15 D14 D13 D12 D11 D10
D9
D8
D7
ADDRESS
D6
D5
D4
D3
D2
D1
MSB
D0
A7
A6
LSB
Bits reserved for
future upgradability
A5
A4
A3
A2
A1
MSB
A0
LSB
Bits reserved for
future upgradability
Figure 2a. Format of Address and Data in Shift Register for Group A, B, C, D, and E DACs (13-bits)
"Don't Care" bits that must be
included in programming sequence
DATA
SDI
D8
D7
D6
D5
D4
D3
D2
D1
MSB
D0
X
X
X
X
X
X
X
ADDRESS
A7
LSB
A6
A5
A4
A3
A2
A1
MSB
Bits reserved for
future upgradability
A0
LSB
Bits reserved for
future upgradability
A6
MSB
Addr.
LSB
Data
A7
D0
CK
D1
≈ ≈
A1
≈
A0
D14
MSB
Data
Next Set
of Data
D15
A0
A1
≈
LSB
Addr.
SDI
≈ ≈
Figure 2b. Format of Address and Data in Shift Register for Group F DACs (6-bits)
CK24
CK1
TCK
CE
UPDATE
SDO
Previous Data
A0
A1
≈ ≈
Update Selected
DAC Register
Corresponds to
A0 loaded at CK1
Figure 3. Serial Data Programming Sequence
 2000 Semtech Corp.
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circuit Description (continued)
Digital Outputs
Power Supply Sequence
SDO is a CMOS output, swinging rail to rail between
DVDD and DGND.
Power supplies should be asserted in the following order:
1.
2.
3.
4.
Chip Reset and Power Up
RESET* for the Edge6420 is active low.
VEE
AVDD
DVDD
AVCC
When the Edge6420 first powers up, the latches will turn
on to the same state as though RESET* had been asserted.
To avoid latchup and ensure a predictable power up, the
above sequence should be followed.
When RESET* is brought low, the latches, and therefore
the DAC levels, will go to a known state that corresponds
to a specific DATA code. See the "Application Information"
section for an example of how this functionality works.
The known states are:
Analog Scan Test Feature
Voltage Outputs
Each voltage output of the Edge6420 has high impedance
FET(s) connected from the outputs to a common analog
scan line.
GROUP
RESET* State (Code)
A
1000H
B
1000H
C
1000H
D
1000H
E
0000H
TEST_MODE
SCAN STATE
F
1000H
0
Scan Off
1
Scan On
Care should be taken to ensure RESET* is invoked properly.
It is critical to ensure that if a RESET* is asserted after
UPDATE has transitioned from a high to low state, that
RESET* stay low, at least 2 µs. To understand this
precaution, notice in Figure 1 that UPDATE is delayed in
order to enable individual DAC latches. If RESET* is not
brought low for sufficient time, an individual DAC update
will occur.
By simply forcing the RESET* pulse low for a minimum of
2 µs, when a CK frequency of 50 MHz or less is used, the
6420 will clear properly to the known states shown above.
The feature utilizes the normal address decoding, as shown
on page 8, as well as a "high" level on the TEST_MODE
pin (see truth table below).
To test an output, a DAC should be loaded as shown by
timing in Figure 3. The clock should be stopped after the
falling edge of CK24 after UPDATE is unasserted. At this
point, the SCAN_OUT pin, which is an analog output, will
reflect the voltage at the addressed DAC's output pin.
Note that the scan output is switched off when the parallel
load is selected (address 64). This prevents a parallel
connection of all the DAC outputs when the scan feature
is used.
VOUT_CH0_1
VOUT_CH0_2
TEST_MODE
VOUT_CH0_3
Address
Decoder
SCAN_OUT
NOTE: When address 64 is invoked (parallel load),
scan is disabled.
Figure 5. Voltage Output Scan
 2000 Semtech Corp.
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circuit Description (continued)
Current Outputs
The TEST_MODE and SCAN_OUT pins on the Edge6420
are used in the same way as for voltage outputs. The
scan circuits for current outputs are shown in Figure 6.
The typical "ON" resistance of the FET switch is 100 kΩ,
but can vary from 60 kΩ to 180 kΩ as a function of process
and output voltage.
The voltage measured at the SCAN_OUT pin, using the
configuration in Figure 6, for Group E and F current outputs
are as follows:
Notes when Using SCAN Feature with Multiple Chips
VSCAN_OUT_E = (RSENSE_E + RPAD) * IOUT_E
When multiple 6420s are used on a board, and it is desired
to gang the SCAN_OUT pins of these 6420s, or gang the
TEST_MODE inputs to one point, it is required for proper
functioning that the following rules be followed:
where:
1)
RSENSE_E = 400Ω ± 30%
RPAD = 30Ω ± 30%
If TEST_MODE inputs are ganged together,
SCAN_OUT cannot be ganged, or invalid results
will be observed at the SCAN_OUT pin. Hence,
each SCAN_OUT pin on a 6420 will have to be
measured separately.
If SCAN_OUT is ganged, TEST_MODE pins cannot
be ganged together.
and
2)
VSCAN_OUT_F = (RSENSE_F + RPAD) * IOUT_F
where:
RSENSE_F = 400Ω ± 30%
RPAD = 30Ω ± 30%
+
IDAC
R
SENSE
R
PAD
IOUT_CH0_0
CONNECT TO
VIRTUAL GROUND
–
TEST_MODE
+
IDAC
R
SENSE
R
PAD
IOUT_CH0_1
CONNECT TO
VIRTUAL GROUND
–
+
ADDRESS
DECODER
IDAC
–
R
SENSE
R
PAD
IOUT_CH0_2
CONNECT TO
VIRTUAL GROUND
SCAN_OUT
NOTE: WHEN ADDRESS 64 IS INVOKED (PARALLEL LOAD), SCAN IS DISABLED.
Figure 6. Current Output Scan Circuits
 2000 Semtech Corp.
14
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Application Information
One application for the Edge6420 is to provide necessary
DC voltages and currents for 4 channels of pin electronics
(driver, receiver, load) and per pin measurement units.
For example, using the:
• Edge720 Load / Driver / Comparator
• Edge4707 PPMU
with the following specifications:
–1.5
–1.5
–1.5
–1.5
–1.5
0 <
0 <
•
•
•
•
< driver output high < +7.5V
< driver output low < +7.5V
< comparator threshold high < +7.5V
< comparator threshold low < +7.5V
< commutating voltage < 7.5V
load source current < 24 mA
load sink current < 24 mA
Channel
0
Address
Group
Type
# Bits
Resolution
–2.8 < PPMU (MI) compare high voltage < +2.8V
–2.8 < PPMU (MI) compare low voltage < +2.8V
–3.0 < PPMU (FV) < +14.0V
Other
Edge720
•
•
•
•
•
•
•
Edge 4707 PPMU
Offset
0 < flash programming voltage (VHH) < +14V
Table 8 demonstrates Edge6420 settings that can be
used to fulfill the above requirements.
Power Supplies (for this application):
15.25 ≤ AVCC ≤ 15.75V
–4.75V ≤ VEE ≤ –4.25V
4.6V ≤ AVDD ≤ 5.25V
4.85 ≤ DVDD ≤ 5.15V
AGND = 0, SGND = 0
Resulting
Range
Output
Compliance
Power on Reset Suggested
(DAC Code)
Application
0
1
2
3
4
A
V
13
1.10 mV
–1.5V
–1.5 / +7.5V
±100 µA
1000H (3V)
VIH
VIL
VOH
VOL
VCOM1
5
6
B
V
13
0.684 mV
–2.8V
–2.8 / 2.8V
±100 µA
1000H (0V)
PPMU CH
PPMU CL
7
8
C
V
13
2.07 mV
–3.0V
–3.0 / +14.0V
±100 µA
1000H (6V)
PPMU FV
VHH
9
10
D
V
13
1.10 mV
–1.5V
–1.5 / +7.5V
±100 µA
1000H (3V)
VCM_IN
11
12
E
I
13
159 nA
N/A
0 to 1.3 mA
–.2 / 2.4V
(Note 1)
0000H (0 mA)
ISC_IN
ISK_IN
13
14
15
F
I
6
39 µA
N/A
0 to 2.5 mA
1000H (1.0 mA)
RADJ
FADJ
IBIAS
–.2 / 2.1V
(Note 1)
16 – 31
Same as above for Channel 1.
32 – 47
Same as above for Channel 2.
48 – 63
Same as above for Channel 3.
Note 1:
Max compliance depends on maximum current required. See specifications for limits.
Table 8. Application Chart – Possible Chip Specification
 2000 Semtech Corp.
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Application Information (continued)
0V
+5V
+15.5V
–5V
+5V
0V
+
– 2.5V
0V
AGND
SGND
AVCC
VEE
AVDD
AGND
DVDD
DGND
VREF
VOUT_CH0_0
VOUT_CH0_1
..
.
..
.
VOUT_CH0_2
DAC
Voltage
Outputs
Loading
Requirement:
10 nF to 100 nF
Note: All unused
voltage outputs must have
an external capacitor
attached (between
10 nF and 100 nF).
VOUT_CH0_8
VOUT_CH0_9
Edge6420
VOUT_CH0_10
..
.
..
.
IOUT_CH0_1
Loading
Requirement:
10 nF to 100 nF
Loading
Requirement:
1 nF (see below)
DAC
Current
Outputs
IOUT_CH0_4
For Group A
DACs
Gain and
Offset Control
AGND
For Group B
DACs
Gain and
Offset Control
For Group C
DACs
Gain and
Offset Control
Loading
Requirement:
1 nF (see below)
R_GAIN_F
IREF_F
R_GAIN_E
IREF_E
R_OFFSET_D
IREF
R_GAIN_D
IREF
R_OFFSET_C
IREF
R_GAIN_C
IREF
R_OFFSET_B
IREF
R_GAIN_B
IREF
R_OFFSET_A
IREF
R_GAIN_A
IREF
R_MASTER
IREF
For Group D
DACs
Gain and
Offset Control
The Selection of
R_MASTER
Establishes IREF
Figure 7. Required External Resistors and Components
Loading Requirements
Caution on Exceeding Compliance Limits on Current
Output DACs
Voltage Outputs
All voltage outputs (denoted VOUT_CH[0:3]_[0:10]) require
a load capacitance between 10 nF and 100 nF for stability.
Current Outputs
All current outputs require capacitive loading; the amount
of loading needed to ensure stability is dependent on the
impedance that the current outputs of the 6420 drive.
For impedances of 1.3 KΩ to 1.6 KΩ, such as what is
seen at the E720 current inputs (ISK, ISRC, IBIAS, RADJ,
and FADJ), it is recommended that 1 nF be used.
 2000 Semtech Corp.
16
Current output DACs (i.e., Group E and F DACs) can exhibit
a “lock-up” condition in situations when the actual voltage
seen at the outputs of these DACs exceeds the compliance
limits in the specification. Care should be taken in the
design of circuits being driven by Group E and F outputs
to ensure compliance limits stated in the specifications
are not exceeded.
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Application Information (continued)
Temperature Coefficient Effect on DACs
There is a gain and offset temperature coefficient that
should be taken into account in the system design that
will affect calibration and performance.
Care should be taken to ensure that devices being driven
by Group E and F DACs are designed to be within the
compliance specification.
1 mA
2 mA
3 mA
IOUT
AVDD
The equation for voltage drift on output DACs is as follows:
∆VOUT_A,B,C,D = ∆T * TCOFFSET_A,B,C,D
µV
˚C
+
Current outputs drift follow the following equation:
∆IOUT_E,F = ∆T * TCOFFSET_E,F
µA
˚C
AVDD – 2
+
CODE * LSB * TCGAIN_E,F (%/˚C)
Average values for TCOFFSET and TCGAIN can be found in
the specifications.
Compliance of Current Output DACs (Groups E, F)
The compliance of the current output DACs (Groups E and
F) is governed by the following two equations:
IOUT < 2.5 mA:
VCOMPLIANCE = (–250 Ω * IOUT) + AVDD – 1.875V
IOUT ≥ 2.5 mA:
VCOMPLIANCE = (–600 Ω * IOUT) + AVDD – 1V
See Figure 8 for a graphical depiction.
Note: IOUT is current sourced from output of DAC.
(1.3 mA, AVDD – 2.2V)
(2.5 mA, AVDD – 2.5V)
AVDD – 3
CODE * LSB * TCGAIN_A,B,C,D (%/˚C)
Compliance Exceeded
AVDD – 1
(3.6 mA, AVDD – 3.2V)
VCOMPLIANCE
Figure 8. Compliance of Current Output DACs
(Groups E and F)
Caution Regarding Power Dissipation of the 6420
During Parallel Load:
The Voltage DAC output amplifiers, for a FAST process,
can:
• Source up to 10 mA (8 mA @ TJ = 100˚C)
• Sink up to 4.5 mA (3.5 mA @ TJ = 100˚C)
Caution must be taken during a parallel load, particularly
when the voltage DACs are loaded with a large filtering
capacitor (10 to 100 nF). In this scenario, a large voltage
change can induce a large current peak. For example,
the currents calculated below can be induced in the VCC/
VEE supplies:
• Source case:
44 DACs * 10 mA / DAC + 40 mA = 480 mA
(or 400 mA @ TJ = 100˚C) in the VCC supply
• Sink case:
44 DACs * 4.5 mA / DAC + 120 mA = 320 mA
(or 280 mA @ TJ = 100˚C) in the VEE supply
Therefore, the user must take care of extra power
dissipation due to these currents peaks, and should avoid
large voltage changes during a parallel load.
 2000 Semtech Corp.
17
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Package Information (continued)
Edge6420BBG Package
0.10
Detail B
–A–
D
15 14 13 12 11 10 9
8
7
6
5
4
3
–B–
2
1
A
B
C
D
E
F
G
E2
(E1)
E
H
J
K
L
M
N
P
R
(D1)
D2
BOTTOM VIEW
TOP VIEW
NX
Detail A
f
φ
b
φ0.15
f
M C A M B M
φ0.075
M C
4
SIDE VIEW
DETAIL B
e
// ccc C
c
A2
DETAIL A
// bbb C
A1
A
aaa C
–C–
6
SEATING
PLANE
5
DIMENSIONAL REFERENCES
NOTE: The inner 9x9 balls are for improved thermal dissipation.
They will be at the VEE potential, so board layout should ensure
that these inner balls are connected to the VEE plane.
REF
MIN
NOM
MAX
A
0.96
1.06
1.16
A1
0.21
0.26
0.31
A2
0.50
0.55
0.60
D1
NOTES:
1.
All dimensions are in millimeters.
2.
‘e’ represents the basic solder ball grid pitch.
3.
“M” represents the basic solder ball matrix size, and symbol “N” is the number
of balls after depopulating.
4.
‘b’ is measurable at the maximum solder ball dimaeter after reflow parallel
to primary datum –C–.
5.
Dimension ‘aaa’ is measured parallel to primary datum –C–.
6.
Primary datum –C– and seating plane are defined by the spherical crowns of the
solder balls.
7.
Package surface shall be matte finish charmilles 24 to 27.
8.
Package centering to substrate shall be 0.0780 mm maximum for both X and Y
directions respectively.
9.
Package warp shall be 0.050 mm maximum.
10. Substrate material base is BT resin.
11. The overall package thickness “A” already considers collapse balls.
12. Dimensioning and tolerancing per ASME Y14.5M 1994.
 2000 Semtech Corp.
18
11.20 BSC
D2
12.90
13.00
13.10
E
12.90
13.00
13.10
E1
11.20 BSC
E2
12.90
13.00
13.10
b
0.40
0.45
0.55
c
0.25
aaa
0.12
bbb
0.20
ccc
0.20
e
f
0.8
0.80
0.90
M
15
N
225
1.00
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Positive Analog Power Supply
AVCC
+15.25
+15.5
+15.75
V
Positive Analog Power Supply 2
AVDD
+4.6
+5
+5.25
V
Negative Power Supply
VEE
–5.25
–5
–4.3
V
Reference Voltage (Note 2)
VREF
Supply Ground (Note 1)
SGND
2.500
–.25
V
0
+.25
V
20.5
+23
V
Total Analog Supply 1
AVCC – VEE
Digital Power Supply
DVDD – DGND
3.00
5.0
5.50
V
DGND
–.25
0
+.25
V
Digital Ground (Note 1)
Thermal Resistance of Package (6420BBG)
(measured at top-center of package)
Case Temperature (at top of package)
θjc
3
TCASE
40
˚C/W
˚C
80
All Power Supply voltages are referred to AGND, the reference signal ground, unless othewise specified.
Note 1:
Note 2:
Not production tested.
User should use a precision supply for VREF setting because the offset and gain of all DACs will change
proportionately to a deviation from VREF = 2.500V. See Equations 1 and 5 to determine the extent of
offset and gain change to deviations in VREF.
 2000 Semtech Corp.
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
AVCC
AVDD
VEE
–.35
–.35
–5.5
+20
+5.5
+.35
V
V
V
Digital Power Supply
DVDD – DGND
–.35
+5.5
V
Total Power Supply
AVCC – VEE
AVCC – AVDD
DGND
SGND
–.35
–5.5
–.35
–.35
+25
+20
+.35
+.35
V
V
V
V
Digital Input Voltages
CE, CK, UPDATE, RESET*,
SDI, TEST_MODE
DGND – .35
DVDD + .35
V
Analog Input Voltages
VREF, VMASTER,
VOFFSET_[A:D], VGAIN_[E:F]
AGND – .35
AVDD + .35
V
VGAIN_[A:D]
AVEE – .35
AGND + .35
V
IGAIN_[E:F]
IMASTER
–1
–1
+1
+1
mA
mA
Analog Output Voltages
Groups A, B, C, D
Groups E, F
VOUT_[A:D]
VOUT_[E:F]
AVEE – .35
AGND – .35
AVCC + .35
AVDD + .35
V
V
Analog Output Currents
Groups A, B, C, D Continuous DC Current
IOUT_[A:D]
–300
+300
µA
3.3
V
Positive Analog Supply
Positive Analog Supply 2
Negative Analog Supply
Analog Input Currents
Output Voltage Compliance (Groups E, F) (Note 1)
Minimum Time Required Between Successive
Parallel Loads of all 64 DACs
@ CLOAD = 100 nF, Full Scale Steps (Note 2)
Tmin
2
Storage Temperature
Junction Temperature
Soldering Temperature
(5 seconds, .25" from the pin)
TS
TJ
TSOL
–65
ms
+150
+125
+260
˚C
˚C
˚C
All Power Supply voltages are referred to AGND, the reference signal ground, unless othewise specified.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied.
Exposure to absolute maximum conditions for extended periods may affect device reliability.
Note 1: Exceeding this limit may result in a monostable output state at maximum current.
Note 2: Full scale step definition: 11.5V step for Group A, B, D DACs, 20V step for Group C, 3.6 mA steps for
Groups E and F.
 2000 Semtech Corp.
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
DC Characteristics
Parameter
Digital Inputs (SDI, CE, CK, UPDATE,
RESET*, TEST_MODE)
Input Low Voltage
Input High Voltage
Input Current
Digital Outputs (SD0, CK_OUT)
Output Low Voltage @ IOL = 1.6 mA
Output High Voltage @ IOH = –0.4 mA
Symbol
Min
VIL
VIH
IIL, IIH
2.4
–1
VOL
VOH
2.4
Typ
Max
Units
.8
1
V
V
µA
.4
DVDD
V
V
DAC Outputs
Groups A, B, D (Voltage Outputs)
Resolution
Max Output Voltage Range
@ R_GAIN / R_MASTER = .4
@ R_GAIN / R_MASTER = 1
@ R_GAIN / R_MASTER = 1.15
Output Offset Range (DATA = 0000H)
@ R_OFFSET / R_MASTER = 0.0
@ R_OFFSET / R_MASTER = 0.5
@ R_OFFSET / R_MASTER = 1.0
@ R_OFFSET / R_MASTER = 1.2
13
VOUT_RANGE
9.8
4
10
11.5
10.2
V
V
V
VOFFSET
–2.60
Output Current Compliance
Headroom of Voltage Outputs
(while maintaining current compliance limit) (Note 1)
VOUT(max) to VCC
VOUT(min) to VEE
Bits
2.5
0
–2.5
–3.5
–100
AVCC – VOUT(max)
VOUT(min) – VEE
–2.35
+100
1.25
1.00
V
V
V
V
µA
V
V
Integral Linearity Error with 9 Point
Calibration (Note 2)
–2.5
2.5
LSB
Integral Linearity Error with 2 Point
Calibration (Note 4)
–15
15
LSB
Differential Linearity Error
–1
1
LSB
Gain TempCo (Notes 3, 6)
Offset TempCo (Notes 3, 6)
@ R_OFFSET / R_MASTER = 0.0
@ R_OFFSET / R_MASTER = 0.5
@ R_OFFSET / R_MASTER = 1.0
@ R_OFFSET / R_MASTER = 1.2
 2000 Semtech Corp.
TCGAIN_A,B,D
–.00285
%/˚C
–288
–110
+145
+231
µV/˚C
µV/˚C
µV/˚C
µV/˚C
TCOFFSET_A,B,D
21
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
DC Characteristics (continued)
Parameter
Symbol
Min
Group C (Voltage Outputs)
Resolution
Max Output Voltage Range
(DATA = IFFFH)
@ R_GAIN / R_MASTER = .4
@ R_GAIN / R_MASTER = .6
@ R_GAIN / R_MASTER = .85
Output Offset Range
(DATA = 0000H)
@ R_OFFSET / R_MASTER
@ R_OFFSET / R_MASTER
@ R_OFFSET / R_MASTER
@ R_OFFSET / R_MASTER
Typ
Max
Units
13
Bits
8
12
17
V
V
V
VOUT_RANGE
16.75
17.22
VOFFSET
=
=
=
=
0.0
0.5
1.1
1.2
–3.10
Output Current Compliance
2.5
0
–3.0
–3.5
–100
Headroom of Voltage Outputs – Group C
(while maintaining current compliance limit)
(Note 1)
VOUT(max) to VCC
VOUT(min) to VEE
AVCC – VOUT(max)
VOUT(min) – VEE
–2.9
+100
1.25
1.00
V
V
V
V
µA
V
V
Integral Linearity Error with 9 Point
Calibration (Note 2)
–3
3
LSB
Integral Linearity Error with 2 Point
Calibration (Note 4)
–20
20
LSB
–1
1
LSB
Differential Linearity Error
Gain TempCo (Notes 3, 6)
Offset TempCo (Notes 3, 6)
@ R_OFFSET / R_MASTER
@ R_OFFSET / R_MASTER
@ R_OFFSET / R_MASTER
@ R_OFFSET / R_MASTER
 2000 Semtech Corp.
TCGAIN_C
–.0012
%/˚C
–250
–77
+240
+166
µV/˚C
µV/˚C
µV/˚C
µV/˚C
TCOFFSET_C
=
=
=
=
0.0
0.5
1.1
1.2
22
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
DC Characteristics (continued)
Parameter
Symbol
Min
Group E (Current Outputs)
Resolution
Max Output Current Range
@ R_GAIN_E = 55 kΩ
@ R_GAIN_E = 62.5 kΩ
@ R_GAIN_E = 156 kΩ
Typ
Max
Units
13
Bits
IOUT
3.09
Output Voltage Compliance (Notes 1, 6)
@ 1.3 mA
@ 2.5 mA
@ 3.2 mA
@ 3.6 mA
3.6
3.2
1.28
–0.20
–0.20
–0.20
–0.20
mA
mA
mA
3.35
AVDD
AVDD
AVDD
AVDD
–
–
–
–
2.20
2.50
2.92
3.20
V
V
V
V
Integral Linearity Error with 9 point
Calibration (Note 2)
–2
2
LSB
Integral Linearity Error with 2 point
Calibration (Note 4)
–15
15
LSB
–1
1
LSB
Differential Linearity Error
Current Offset
(–128 * LSB)
– 20
–128 * LSB
(–128 * LSB)
+ 20
µA
Gain TempCo (Notes 3, 6)
TCGAIN_E
–.0021
%/˚C
Offset TempCo (Notes 3, 6)
TCOFFSET_E
±100
nA/˚C
6
Bits
Group F (Current Outputs)
Resolution
Max Output Current Range
@ R_GAIN_F = 55 KΩ
@ R_GAIN_F = 62.5 KΩ
@ R_GAIN_F = 156 KΩ
IOUT
3.09
Output Voltage Compliance (Notes 1, 6)
@ 1.3 mA
@ 2.5 mA
@ 3.15 mA
@ 3.6 mA
3.54
3.15
1.26
– 0.20
– 0.20
– 0.20
–0.20
Integral Linearity Error with
2 Point Calibration (Note 5)
mA
mA
mA
3.35
AVDD
AVDD
AVDD
AVDD
–
–
–
–
2.20
2.50
2.89
3.20
V
V
V
V
–0.25
0.25
LSB
–1
1
LSB
20
µA
Differential Linearity Error
Current Offset
–20
0
Gain TempCo (Notes 3, 6)
TCGAIN_F
–.0057
%/˚C
Offset TempCo (Notes 3, 6)
TCOFFSET_F
±23
nA/˚C
 2000 Semtech Corp.
23
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
DC Characteristics (continued)
Power Supplies
Parameter
Power Supply Consumption
Positive Analog Supply 1 (Note 6)
Positive Analog Supply 2 (Note 6)
Digital Supply (Note 6)
Negative Power Supply 1 (Note 6)
Reference Supply
Symbol
Min
ICC
IADD
IDDD
IEE
IREF
–118
Power Supply Rejection Ratio (Note 1)
5 MHz
1 MHz
100 KHz
PSRR
Power Supply – DC Sensitivity (Note 1)
∆VOUT/ ∆AVDD
Typ
Max
Units
20.5
60
2
–73
0.2
41.5
132
10
mA
mA
mA
mA
mA
1.4
65
45
50
dB
dB
dB
40
dB
All specifications are guaranteed over Recommended Operating Conditions unless otherwise noted.
DC Test Conditions (unless otherwise specified): VREF = 2.50V.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Not production tested. Guaranteed by bench characterization.
The 9 calibration points recommended are:
DATA values of 0000H, 03FFH, 07FFH, 0BFFH, OFFFH, 13FFH, 17FFH, 1BFFH, 1FFFH.
Assuming R_MASTER = 100 KΩ, stable VREF, nominal external resistor values, and stable supply voltage values.
Calibration points are: Data values of 0000H and 1FFFH.
Calibration points are: Data values of OOOOH and OO3FH.
See “Applications Information” for further information.
 2000 Semtech Corp.
24
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
AC Characteristics
Parameter
Digital Inputs
Set Up Times (Note 1)
SDI to Rising CK
CE (rising edge) to Rising CK24
UPDATE (rising edge) to Rising CK24
(Notes 2, 3)
Hold Times (Note 1)
SDI to Rising CK
CE (falling edge) to Rising CK24
UPDATE (falling edge) to Rising CK24
(Notes 2, 3)
Symbol
Min
TSU_SDI
TSU_CE
TSU_UPDT
10
10
5
THLD_SDI
THLD_CE
THLD_UPDT
10
10
5
Typ
Max
Units
70% of TCK
ns
ns
ns
70% of TCK
ns
ns
ns
CK
Fmax at DVDD = 3.3V ± .30V (Notes 1,5)
30 to 50% Duty Cycle (Note 5)
70% Duty Cycle
Fmax at DVDD = 5.0V ± .50 (Notes 4,5)
30 to 50% Duty Cycle
70% Duty Cycle
Duty Cycle (Note 1)
RESET Pulse Width
Output Voltage Settling Time (Note 1)
(from CK Ø corresponding to UPDATE)
Full Scale Step, 10V (to 0.025% FSR)
for Groups A, B, D
Load: 10 nF
Load: 100 nF
Fmax
Fmax
33
20
MHz
MHz
55
35
MHz
MHz
PWCK
30
PWRESET
2
50
70
%
µs
Ts
Full Scale Step, 17V (to 0.025% FSR)
for Group C
Load: 10 nF
Load: 100 nF
Output Current Settling Time
Group E (to .025%)
Load: 1 nF
Load: 10 nF
30
250
70
700
µs
µs
50
0.410
150
1
µs
ms
53
230
100
500
µs
µs
4.4
29
10
50
µs
µs
Group F (to .8%)
Load: 1 nF
Load: 10 nF
Test conditions (unless otherwise specified): "Recommended Operating
Conditions".
CE
TSU_CE
TCK
ª
THLD_CE
Note 4:
Note 5:
UPDATE
TSU_UPDATE
THLD_UPDATE
Figure 9. Central and Individual DAC Updating
SDI
Valid Data
A0
ª ª
Note 2:
Note 3:
Not production tested. Guaranteed by design and
characterization.
The max spec of 70% of TCK is not production tested.
CK24 refers to 24th rising clock edge, which corresponds
to a full shift register. Note that a falling CK24 edge is also
required for proper operation of circuit.
The 6420 is production tested at 55 MHz only, with 50%
duty cycle.
Duty cycle % shown refers to “high” duration of clock
in a period.
Note: A 24th falling
CK edge is required for
DAC updating!
CK24
CK1
TSU_SDI
CK
Valid Data
D15
TSU_SDI
THLD_SDI
CK1
ª
Note 1:
CK
THLD_SDI
CK24
Figure 8. Shift Register Loading Timing Diagram
 2000 Semtech Corp.
25
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Ordering Information
Model Number
Package
E6420BBG
225 Ball, 13 mm x 13 mm BGA
6420EVM
Edge6420 Evaluation Board
Contact Information
Semtech Corporation
High-Performance Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858)695-1808 FAX (858)695-2633
 2000 Semtech Corp.
26
www .semtech.com
Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Revision History
Current Revision: April 29, 2002
Previous Revision: September 25, 2001
Page #
Section Name
Previous Revision
Current Revision
all
All
Preliminary
Remove "Preliminary".
Datasheet now "Final".
1
Description
The DACs are programmed using a 1 bit serial interface.
The DACs are programmed using a serial interface.
3, 4, 5
Pin Descriptions
10
Address Map
17
Package Infromation
21
DC Characteristics
Groups A, B, D
Integral Linearity Error with 9 Point Calibration
Max: ±2
Integral Linearity Error with 2 Point Calibration
Max: ±15
Differential Linearity Error
Max: <±1
Groups A, B, D
Integral Linearity Error with 9 Point Calibration
Min: –2.5, Max: 2.5
Integral Linearity Error with 2 Point Calibration
Min: –15, Max: 15
Differential Linearity Error
Min: –1, Max: 1
22
DC Characteristics
Group C
Integral Linearity Error with 9 Point Calibration
Max: ±3
Integral Linearity Error with 2 Point Calibration
Max: ±20
Differential Linearity Error
Max: <±1
Groups A, B, D
Integral Linearity Error with 9 Point Calibration
Min: –3, Max: 3
Integral Linearity Error with 2 Point Calibration
Min: –20, Max: 20
Differential Linearity Error
Min: –1, Max: 1
23
DC Characteristics
Group E
Integral Linearity Error with 9 Point Calibration
Max: ±2
Integral Linearity Error with 2 Point Calibration
Max: ±15
Differential Linearity Error
Max: <±1
GroupsE
Integral Linearity Error with 9 Point Calibration
Min: –2, Max: 2
Integral Linearity Error with 2 Point Calibration
Min: –15, Max: 15
Differential Linearity Error
Min: –1, Max: 1
Group F
Integral Linearity Error with 2 Point Calibration
MIn: –0.25, Max: 0.25
Differential Linearity Error
Min: –1, Max: 1
Add: N/C (No Connect) Ball Numbers
TBD
Load Commutating Voltage
Remove: Edge6420ABG Package
24
DC Characteristics
Group F
Integral Linearity Error with 2 Point Calibration
Max: ±0.25
Differential Linearity Error
Max: <±1
24
Power Supplies
Negative Power Supply
Move: –118 from Max to Min column
25
AC Characteristics
Full Scale Step, 17V for Group C
Load: 100 nF, Typ: 410
Full Scale Step, 17V for Group C
Load: 100 nF, Typ: 0.410
26
Ordering Information
 2000 Semtech Corp.
Remove: E6420ABG
27
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Revision History
Current Revision: September 25, 2001
Previous Revision: August 3, 2001
Page #
Section Name
Previous Revision
Current Revision
16
Application
Information
Caution Regarding Power Dissipation of the 6420
During Parallel Load
Reword entire section
Delete: (referred to AGND) from all specs
19
Recommended
Operating Conditions
Negative Power Supply1
Negative Power Supply
Analog Ground 2 (Notes 1, 3)
Supply Ground (Note 1)
Delete: Analog Ground
Notes: Delete Note 2, 3, Note 4 becomes new Note 2
Add: "All Power Supply voltages ..." at beginning of notes
20
Ab Max Ratings
Positive Analog Supply 2
Min: –.35
Digital Power Supply, Sym: DVDD
Digital Power Supply, Sym: DVDD – DGND
Total Power Supply
DGND – AGNE, SGND – AGND
Total Power Supply
DGND, SGND
Delete: AVDD – AGND and VEE – AGND specs
Add: "All Power Supply voltages ..." at beginning of notes
21
22
23
24
25
DC Characteristics
DC Characteristics
DC Characteristics
DC Characteristics
AC Characteristics
 2000 Semtech Corp.
Max Output Voltage Range
@ R_GAIN/R_MASTER = 1, Min: 9.86, Max: 10.14
Max Output Voltage Range
@ R_GAIN/R_MASTER = 1, Min: 9.8, Max: 10.2
Output Offset Range
@ R_OFFSET/R_MASTER = 1.0, Min: –2.6, Max: –2.4
Output Offset Range
@ R_OFFSET/R_MASTER = 1.0, Min: –2.60, Max: –2.35
Gain TempCo, Typ: –.000285
Gain TempCo, Typ: –.00285
Offset TempCo
@ VOFFSET = 2.5V
@ VOFFSET = 0, Typ: –72
@ VOFFSET = –2.5V
@ VOFFSET = –3.5V
Offset TempCo
@ R_OFFSET / R_MASTER = 0.0
R_OFFSET / R_MASTER = 0.5, Typ: –110
@ R_OFFSET / R_MASTER = 1.0
@ R_OFFSET / R_MASTER = 1.2
Output Offset Range
@ R_OFFSET/R_MASTER = 1.1,
Min: –3.05, Max: –2.95
Output Offset Range
@ R_OFFSET/R_MASTER = 1.1,
Min: –3.10, Max: –2.9
Gain TempCo, Typ: –.000447
Gain TempCo, Typ: –.0012
Offset TempCo
@ VOFFSET = 2.5V
@ VOFFSET = 0
@ VOFFSET = –3.0V, Typ: +132
@ VOFFSET = –3.5V
Offset TempCo
@ R_OFFSET / R_MASTER = 0.0
@ R_OFFSET / R_MASTER = 0.5
@ R_OFFSET / R_MATER = 1.1, Typ: +240
@ R_OFFSET / R_MASTER = 1.2
Group E
Max Output Current Range
@ R_GAIN_# = 62.5, Min: 3.14, Max: 3.32
Max Output Current Range
@ R_GAIN_# = 62.5, Min: 3.09 Max: 3.35
Output Voltage Compliance
3.6 mA, Min: –0.29
Output Voltage Compliance: Add: @ 3.2 mA
3.6 mA, Min: –0.20
Gain TempCo, Typ: –.00129
Gain TempCo, Typ: –.0021
Group F
Output Voltage Compliance
Group F
Output Voltage Compliance: Add: 3.15 mA
Integral Linearity Error, Max: ±2
Integral Linearity Error, Max: ±0.25
Gain TempCo, Typ: –.00129
Gain TempCo, Typ: –.0057
Offset TempCo, Typ: +23
Offset TempCo, Typ: ±23
Positive Analog Supply2, Digital Supply
Add Note 6
Negative Power Supply, Min: 73, Max: 118
Negative Power Supply, Min: –73, Max: –118
Note 4: ... and IFFFH
Note 4: ... and 1FFFH
Fmax at DVDD
Add Note 5
28
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Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Revision History
Current Revision: August 3, 2001
Previous Revision: June 28, 2001
Page #
7
Section Name
Previous Revision
Current Revision
All
Target
Preliminary
DAC Current Output
Overview & Offset
Add: Equation numbers
8
Offset
The offset for each current ...
The typical offset for each current ...
14
Table 8
Channels 11, 12
Resolution: 0.159 nA
Channels 11, 12
Resolution: 159 nA
15
Application Information
Delete: Note 2
change 100 pF to 1 nF
Current Outputs, last sentence: ... it is
recommended that 100 pF be used.
16
Temperature Coefficient
Effect on DACs
17
6420ABG Package
19
Recommended
Operating Conditions
... it is recommended that 1 nF be used.
Add: Last paragraph, "Contact Semtech for a summary of
equations to derive TCOFFSET and TCGAIN.
Note 3
Delete: all but "f0.30 mm"
Delete: Notes 1 & 2
Add: New Notes 1 and 4, renumber remaining notes
Reference Voltage, Min: 2.475, Typ: 2.50000, Max:
2.525
Reference Voltage, Typ: 2.500, delete Min & Max values
Digital Power Supply, Min: 4.85, Max: 5.15
Digital Power Supply, Min: 3.00, Max: 5.50
Thermal Resistance of Package, Typ: TBD,
Units: ˚C
Thermal Resistance of Package (measured at top-center
of package), Typ: 3, Units: ˚C/W
20
Ab Max Ratings
Digital Input Voltages
Add: "SDI, TEST_MODE" to Symbols
21
DC Characteristics
Gain TempCo, Typ: –.0012
Gain TempCo (Notes 3, 6), Typ: –.000285
Offset Tempco, Typ: –200, 0, +236, +324
Offset Tempco, Typ: –288, –72, +145, +231
Integral Linearity Error with 2 Point Calibration, Max:
±2
Integral Linearity Error with 2 Point Calibration,
Max: ±3
22
23
24
DC Characteristics
DC Characteristics
DC Charcteristics
Gain TempCo, Typ: –.0015
Gain TempCo (Notes 3, 6), Typ: –.000447
Offset TempCo, Typ: –200, 0, TBD, +325
Offset TempCo, Typ: –250, –77, +132, +166
Group E
Gain TempCo, Typ: –.0018
Offset TempCo, Typ: TBD,
Groups E
Gain TempCo (Notes 3, 6), Typ: –.00129
Offset TempCo, Typ: ±100
Group F
Gain Tempco
Offset TempCo, Typ: TBD
Group F
Gain Tempco (Notes 3, 6)
Offset TempCo, Typ: ±23
Digital Supply, Typ: TBD, Max: TBD
Digital Supply, Typ: 2, Max: 10
Power Supply Rejection Ratio
1 MHz, Typ: TBD
500 kHz, Typ: TBD
100 kHz, Typ: TBD
Power Supply Rejection Ratio
5 MHz, Typ: –65
1 MHz, Typ: –45
100 kHz, Typ: –50
Add: Power Supply – DC Sensitivity
24
DC Charcteristics
(Notes)
25
AC Characteristics
VREF = 2.50000V
VREF = 2.50V
Fmax at DVDD = 3.3V (Note 4)
Fmax at DVDD = 3.3V ± .30V (Note 1)
Fmax at DVDD = 5.0V (Note 1)
Fmax at DVDD = 5.0V ± .50V (Note 4)
Full Scale Step, 0 to 10V
Load: 10 nF, Max: TBD, Load: 100 nF, Max: TBD,
Units: ms
Full Scale Step, 10V
Load: 10 nF, Max: 70, Load: 100 nF, Max: 700, Units:
µs
Full Scale Step, 0 to 17V, Load: 100 nF, Units: µS
Full Scale Step, 17V, Load: 100 nF, Units: ms
Note 4: tested at 33 MHz only ...
Note 4: tested at 55 MHz only; delete last sentence
Delete: Power Supply Sensitivity
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