Elpida EBJ41HE4BDFM-DJ-F 4gb registered ddr3 sdram dimm Datasheet

DATA SHEET
4GB Registered DDR3 SDRAM DIMM
EBJ41HE4BDFD
EBJ41HE4BDFM
EBJ41HE4BDFP
(512M words × 72 bits, 2 Ranks)
Specifications
Features
• Density: 4GB
• Organization
 512M words × 72 bits, 2 ranks
• Mounting 36 pieces of 1G bits DDR3 SDRAM sealed
in FBGA
• Package: 240-pin socket type dual in line memory
module (DIMM)
 PCB height: 30.5mm (max.)
 Lead pitch: 1.0mm
 Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD = 1.5V ± 0.075V
• Data rate: 1333Mbps/1066Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_15
• Burst lengths (BL): 8 and 4 with Burst Chop (BC)
• /CAS Latency (CL): 6, 7, 8, 9
• /CAS write latency (CWL): 5, 6, 7
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles
 Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
 TC = 0°C to +95°C
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die-Termination (ODT) for better signal quality
 Synchronous ODT
 Dynamic ODT
 Asynchronous ODT
• Multi Purpose Register (MPR) for temperature read
out
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• /RESET pin for Power-up sequence and reset
function
• SRT range:
 Normal/extended
• Programmable Output driver impedance control
• 1 piece of registering clock driver and 1 piece of
serial EEPROM (256 bytes EEPROM) for Presence
Detect (PD)
• Class B temperature sensor functionality with
EEPROM
Note:
Warranty void if removed DIMM heat
spreader.
Document No. E1580E30 (Ver. 3.0)
Date Published January 2010 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2009-2010
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
Ordering Information
Part number
Component
1
JEDEC speed bin*
Data rate
Mbps(max.) (CL-tRCD-tRP)
EBJ41HE4BDFD-DJ-F
1333
240-pin DIMM Gold
DDR3-1333H (9-9-9) (lead-free and
halogen-free)
EBJ41HE4BDFD-AE-F
1066
DDR3-1066F (7-7-7)
EBJ41HE4BDFM-DJ-F
1333
DDR3-1333H (9-9-9)
EBJ41HE4BDFM-AE-F
1066
DDR3-1066F (7-7-7)
EBJ41HE4BDFP-DJ-F
1333
DDR3-1333H (9-9-9)
EBJ41HE4BDFP-AE-F
1066
DDR3-1066F (7-7-7)
Package
Contact
pad
Mounted devices
EDJ1104BDSE-GL-F
EDJ1104BDSE-GN-F
EDJ1104BDSE-DJ-F
EDJ1104BDSE-GL-F
EDJ1104BDSE-GN-F
EDJ1104BDSE-DJ-F
EDJ1104BDSE-AE-F
EDJ1104BDSE-GL-F
EDJ1104BDSE-GN-F
EDJ1104BDSE-DJ-F
EDJ1104BDSE-GL-F
EDJ1104BDSE-GN-F
EDJ1104BDSE-DJ-F
EDJ1104BDSE-AE-F
EDJ1104BDSE-GL-F
EDJ1104BDSE-GN-F
EDJ1104BDSE-DJ-F
EDJ1104BDSE-GL-F
EDJ1104BDSE-GN-F
EDJ1104BDSE-DJ-F
EDJ1104BDSE-AE-F
Mounted
logic devices
IDT
Montage
Inphi
Note: 1. Module /CAS latency = component CL + 1.
Part Number
E B J 41 H E 4 B D F D - DJ - F
Environment code
F: Lead Free
(RoHS compliant)
and Halogen Free
Elpida Memory
Type
B: Module
DRAM Speed Grade
DJ: DDR3-1333H (9-9-9)
AE: DDR3-1066F (7-7-7)
Product Family
J: DDR3
Density / Rank
41: 4GB/2-rank
Module Type
H: Registered
(with heat spreader)
Logic Device Information
D: IDT
M: Montage
P: Inphi
Mono Density
E: 1Gb
Module Outline
F: 240-pin DIMM
Mono Organization
4: x4
Die Rev. (Mono)
Power Supply, Interface
B: 1.5V, SSTL_15
Data Sheet E1580E30 (Ver. 3.0)
2
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
Pin Configurations
Front side
1 pin
121 pin
48 pin 49 pin
120 pin
168 pin 169 pin
240 pin
Back side
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1
VREFDQ
61
A2
121
VSS
181
A1
2
VSS
62
VDD
122
DQ4
182
VDD
3
DQ0
63
CK1
123
DQ5
183
VDD
4
DQ1
64
/CK1
124
VSS
184
CK0
5
VSS
65
VDD
125
DQS9
185
/CK0
6
/DQS0
66
VDD
126
/DQS9
186
VDD
7
DQS0
67
VREFCA
127
VSS
187
/EVENT
8
VSS
68
Par_In
128
DQ6
188
A0
9
DQ2
69
VDD
129
DQ7
189
VDD
10
DQ3
70
A10(AP)
130
VSS
190
BA1
11
VSS
71
BA0
131
DQ12
191
VDD
12
DQ8
72
VDD
132
DQ13
192
/RAS
13
DQ9
73
/WE
133
VSS
193
/CS0
14
VSS
74
/CAS
134
DQS10
194
VDD
15
/DQS1
75
VDD
135
/DQS10
195
ODT0
16
DQS1
76
/CS1
136
VSS
196
A13
17
VSS
77
ODT1
137
DQ14
197
VDD
18
DQ10
78
VDD
138
DQ15
198
NC
19
DQ11
79
NC
139
VSS
199
VSS
20
VSS
80
VSS
140
DQ20
200
DQ36
21
DQ16
81
DQ32
141
DQ21
201
DQ37
22
DQ17
82
DQ33
142
VSS
202
VSS
23
VSS
83
VSS
143
DQS11
203
DQS13
24
/DQS2
84
/DQS4
144
/DQS11
204
/DQS13
25
DQS2
85
DQS4
145
VSS
205
VSS
26
VSS
86
VSS
146
DQ22
206
DQ38
27
DQ18
87
DQ34
147
DQ23
207
DQ39
28
DQ19
88
DQ35
148
VSS
208
VSS
29
VSS
89
VSS
149
DQ28
209
DQ44
30
DQ24
90
DQ40
150
DQ29
210
DQ45
31
DQ25
91
DQ41
151
VSS
211
VSS
32
VSS
92
VSS
152
DQS12
212
DQS14
33
/DQS3
93
/DQS5
153
/DQS12
213
/DQS14
34
DQS3
94
DQS5
154
VSS
214
VSS
35
VSS
95
VSS
155
DQ30
215
DQ46
36
DQ26
96
DQ42
156
DQ31
216
DQ47
Data Sheet E1580E30 (Ver. 3.0)
3
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
37
DQ27
97
DQ43
157
VSS
217
VSS
38
VSS
98
VSS
158
CB4
218
DQ52
39
CB0
99
DQ48
159
CB5
219
DQ53
40
CB1
100
DQ49
160
VSS
220
VSS
41
VSS
101
VSS
161
DQS17
221
DQS15
42
/DQS8
102
/DQS6
162
/DQS17
222
/DQS15
43
DQS8
103
DQS6
163
VSS
223
VSS
44
VSS
104
VSS
164
CB6
224
DQ54
45
CB2
105
DQ50
165
CB7
225
DQ55
46
CB3
106
DQ51
166
VSS
226
VSS
47
VSS
107
VSS
167
NC
227
DQ60
48
VTT
108
DQ56
168
/RESET
228
DQ61
49
VTT
109
DQ57
169
CKE1
229
VSS
50
CKE0
110
VSS
170
VDD
230
DQS16
51
VDD
111
/DQS7
171
A15
231
/DQS16
52
BA2
112
DQS7
172
A14
232
VSS
53
/Err_Out
113
VSS
173
VDD
233
DQ62
54
VDD
114
DQ58
174
A12
234
DQ63
55
A11
115
DQ59
175
A9
235
VSS
56
A7
116
VSS
176
VDD
236
VDDSPD
57
VDD
117
SA0
177
A8
237
SA1
58
A5
118
SCL
178
A6
238
SDA
59
A4
119
SA2
179
VDD
239
VSS
60
VDD
120
VTT
180
A3
240
VTT
Data Sheet E1580E30 (Ver. 3.0)
4
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
Pin Description
Pin name
Function
A0 to A15
Address input
Row address
Column address
A10 (AP)
Auto precharge
A0 to A13
A0 to A9, A11
A12 (/BC)
Burst chop
BA0, BA1, BA2
Bank select address
DQ0 to DQ63
Data input/output
CB0 to CB7
Check bit (Data input/output)
/RAS
Row address strobe command
/CAS
Column address strobe command
/WE
Write enable
/CS0, /CS1
Chip select
CKE0, CKE1
Clock enable
CK0, CK1
Clock input
/CK0, /CK1
Differential clock input
DQS0 to DQS17, /DQS0 to /DQS17
Input and output data strobe
SCL
Clock input for serial PD
SDA
Data input/output for serial PD
SA0, SA1, SA2
Serial address input
VDD
Power for internal circuit
VDDSPD
Power for serial EEPROM
VREFCA
Reference voltage for CA
VREFDQ
Reference voltage for DQ
VSS
Ground
VTT
Termination Voltage
/RESET
Set DRAM to known state
ODT0, ODT1
ODT control
Par_In
Parity bit for the Address and Control bus
/Err_Out
Parity error found on the Address and Control bus
/Event
Temperature event pin
NC
No connection
Data Sheet E1580E30 (Ver. 3.0)
5
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
Serial PD Matrix
-AE
-DJ
Byte No.
Function described
Hex
Comments
Hex
Comments
0
Number of serial PD bytes written/SPD device
size/CRC coverage
92h
176/256/0-116
92h
176/256/0-116
1
SPD revision
10h
Rev.1.0
10h
Rev.1.0
2
Key byte/DRAM device type
0Bh
DDR3 SDRAM
0Bh
DDR3 SDRAM
3
Key byte/module type
01h
RDIMM
01h
RDIMM
4
SDRAM density and banks
02h
1G bits, 8 banks
02h
1G bits, 8 banks
5
SDRAM addressing
12h
14 rows, 11 columns
12h
14 rows, 11 columns
6
Module nominal voltage, VDD
00h
1.5V
00h
1.5V
7
Module organization
08h
2 ranks/×4 bits
08h
2 ranks/×4 bits
8
Module memory bus width
0Bh
72 bits/ECC
0Bh
72 bits/ECC
9
Fine timebase (FTB) dividend/divisor
52h
5/2
52h
5/2
10
Medium timebase (MTB) dividend
01h
1
01h
1
11
Medium timebase (MTB) divisor
08h
8
08h
8
12
SDRAM minimum cycle time (tCK (min.))
0Fh
1.875ns
0Ch
1.5ns
13
Reserved
00h
—
00h
—
14
SDRAM /CAS latencies supported, LSB
1Ch
6, 7, 8
3Ch
6, 7, 8, 9
15
SDRAM /CAS latencies supported, MSB
00h
—
00h
—
16
SDRAM minimum /CAS latencies time (tAA (min.))
69h
13.125ns
69h
13.125ns
17
SDRAM write recovery time (tWR)
78h
15ns
78h
15ns
18
SDRAM minimum /RAS to /CAS delay (tRCD)
69h
13.125ns
69h
13.125ns
19
SDRAM minimum row active to row active
delay (tRRD)
3Ch
7.5ns
30h
6.0ns
20
SDRAM minimum row precharge time (tRP)
69h
13.125ns
69h
13.125ns
21
SDRAM upper nibbles for tRAS and tRC
11h
—
11h
—
22
SDRAM minimum active to precharge time
(tRAS), LSB
2Ch
37.5ns
20h
36ns
23
SDRAM minimum active to active /auto-refresh time
95h
(tRC), LSB
50.625ns
89h
49.125ns
24
SDRAM minimum refresh recovery time delay
(tRFC), LSB
70h
110ns
70h
110ns
25
SDRAM minimum refresh recovery time delay
(tRFC), MSB
03h
110ns
03h
110ns
26
SDRAM minimum internal write to read
command delay (tWTR)
3Ch
7.5ns
3Ch
7.5ns
27
SDRAM minimum internal read to precharge
command delay (tRTP)
3Ch
7.5ns
3Ch
7.5ns
28
Upper nibble for tFAW
01h
37.5ns
00h
30ns
29
Minimum four activate window delay time (tFAW)
2Ch
37.5ns
F0h
30ns
30
SDRAM output drivers supported
83h
DLL-off, RZQ/6, 7
83h
DLL-off, RZQ/6, 7
31
SDRAM refresh options
81h
PASR/2X refresh at
+85ºC to +95ºC
81h
PASR/2X refresh at
+85ºC to +95ºC
32
Module thermal sensor
80h
Incorporated
80h
Incorporated
33
SDRAM device type
00h
Standard
00h
Standard
34 to 59
Reserved
00h
—
00h
—
Data Sheet E1580E30 (Ver. 3.0)
6
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
-AE
-DJ
Byte No.
Function described
Hex
Comments
Hex
Comments
60
Module nominal height
10h
30 < height ≤ 31mm
10h
30 < height ≤ 31mm
61
Module maximum thickness
33h
Dual sides w/HS
33h
Dual sides w/HS
62
Reference raw card used
24h
Row Card E1
24h
Row Card E1
63
DIMM Module Attributes
09h
2 rows/1 register
09h
2 rows/1 register
64
Heat Spreader Solution
80h
Incorporated
80h
Incorporated
65
Register Vendor ID, LSB
(IDT)
80h
—
80h
—
(Montage)
86h
—
86h
—
(Inphi)
04h
—
04h
—
B3h
—
B3h
—
(Montage)
32h
—
32h
—
(Inphi)
B3h
—
B3h
—
61h
—
61h
—
66
67
Register Vendor ID, MSB
(IDT)
Register Revision
(IDT)
(Montage)
05h
—
05h
—
(Inphi)
11h
—
11h
—
68
Register Type
00h
SSTE32882
00h
SSTE32882
69
Register Control Word Functions (RC1, 0)
00h
Default
00h
Default
70
Register Control Word Functions (RC3, 2)
50h
Default
50h
Default
71
Register Control Word Functions (RC5, 4)
55h
Default
55h
Default
72
Register Control Word Functions (RC7, 6)
00h
Default
00h
Default
73
Register Control Word Functions (RC9, 8)
00h
Default
00h
Default
74
Register Control Word Functions (RC11, 10)
00h
Default
00h
Default
75
Register Control Word Functions (RC13, 12)
00h
Default
00h
Default
76
Register Control Word Functions (RC15, 14)
00h
Default
00h
Default
77 to 116
Reserved
00h
—
00h
—
117
Module ID: manufacturer’s JEDEC ID code, LSB
02h
Elpida Memory
02h
Elpida Memory
118
Module ID: manufacturer’s JEDEC ID code, MSB
FEh
Elpida Memory
FEh
Elpida Memory
119
Module ID: manufacturing location
××
—
××
—
120
Module ID: manufacturing date
yy
Year code (BCD)
yy
Year code (BCD)
121
Module ID: manufacturing date
ww
Week code (BCD)
ww
Week code (BCD)
××
—
××
—
35h
—
77h
—
(Montage)
19h
—
5Bh
—
(Inphi)
2Dh
—
6Fh
—
Cyclical redundancy code (CRC)
(IDT)
6Ah
—
C3h
—
(Montage)
E2h
—
4Bh
—
(Inphi)
54h
—
FDh
—
122 to 125 Module ID: module serial number
126
127
Cyclical redundancy code (CRC)
(IDT)
Data Sheet E1580E30 (Ver. 3.0)
7
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
-AE
-DJ
Byte No.
Function described
Hex
Comments
Hex
Comments
128
Module part number
45h
E
45h
E
129
Module part number
42h
B
42h
B
130
Module part number
4Ah
J
4Ah
J
131
Module part number
34h
4
34h
4
132
Module part number
31h
1
31h
1
133
Module part number
48h
H
48h
H
134
Module part number
45h
E
45h
E
135
Module part number
34h
4
34h
4
136
Module part number
42h
B
42h
B
137
Module part number
44h
D
44h
D
138
Module part number
46h
F
46h
F
139
Module part number
(IDT)
44h
D
44h
D
(Montage)
4Dh
M
4Dh
M
(Inphi)
50h
P
50h
P
140
Module part number
2Dh
—
2Dh
—
141
Module part number
41h
A
44h
D
142
Module part number
45h
E
4Ah
J
143
Module part number
2Dh
—
2Dh
—
144
Module part number
46h
F
46h
F
145
Module part number
20h
(Space)
20h
(Space)
146
Module revision code
30h
Initial
30h
Initial
147
Module revision code
20h
(Space)
20h
(Space)
148
SDRAM manufacturer’s JEDEC ID code, LSB
02h
Elpida Memory
02h
Elpida Memory
149
SDRAM manufacturer’s JEDEC ID code, MSB
FEh
Elpida Memory
FEh
Elpida Memory
00h
—
00h
—
150 to 175 Manufacturer's specific data
176 to 255 Open for customer use
Data Sheet E1580E30 (Ver. 3.0)
8
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
Block Diagram
/RCS0
/RCS1
RDQS9
/RDQS9
RDQ[7:4]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS0
/RDQS0
RDQ[3:0]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS1
/RDQS1
RDQ[11:8]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS10
/RDQS10
RDQ[15:12]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS2
/RDQS2
RDQ[19:16]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS11
/RDQS11
RDQ[23:20]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS3
/RDQS3
RDQ[27:24]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS12
/RDQS12
RDQ[31:28]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS4
/RDQS4
RDQ[35:32]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS13
/RDQS13
RDQ[39:36]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS5
/RDQS5
RDQ[43:40]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS14
/RDQS14
RDQ[47:44]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS6
/RDQS6
RDQ[51:48]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS15
/RDQS15
RDQ[55:52]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RBA[2:0]
RA[15:0]
/RRAS
/RCAS
/RWE
RDQS7
/RDQS7
RDQ[59:56]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS16
/RDQS16
RDQ[63:60]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
/RCS[1:0]
RCKE[1:0]
RODT[1:0]
RDQS8
/RDQS8
RCB[3:0]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
RDQS17
/RDQS17
RCB[7:4]
VSS
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
DQS /CS
/DQS
DQ[3:0]
DM
ZQ
D0
D1
D2
D3
D18
D19
D20
D21
D9
D10
D11
D12
D27
D28
D29
D30
22Ω
/CS0
/CS1
BA[2:0]
A[15:0]
/RAS
/CAS
/WE
CKE0
CKE1
ODT0
ODT1
Par_In
CK0
120Ω
/CK0
/RESET
R
e
g
i
s
t
e
r
/RCS0 : Rank0
/RCS1 : Rank1
RBA[2:0]
RA[15:0]
/RRAS
/RCAS
/RWE
RCKE0 : Rank0
RCKE1 : Rank1
RODT0 : Rank0
RODT1 : Rank1
/Err_Out
PCK[3:0]
a
n
d
P
L
L
/PCK[3:0]
All SDRAMs
D22
D23
D24
D25
D8
D4
D5
D6
D7
D26
D31
D32
D33
D34
D17
D13
D14
D15
D16
D35
15Ω
DQ[63:0]
CB[7:0]
DQS[17:0]
/DQS[17:0]
RDQ[63:0]
RCB[7:0]
RDQS[17:0]
/RDQS[17:0]
36Ω
VTT
36Ω
VTT
PCK[3:0]
75Ω
/PCK[3:0]
CK1
VTT
VTT
D1
D2
D3
D8
D4
D5
D6
D7
VTT
D9
D10
D11
D12
D17
D13
D14
D15
D16
VTT
VTT
VTT
D0
VDDSPD
VREFCA
VTT
VDD
VREFDQ
VSS
D27
D28
D29
D30
D35
D31
D32
D33
D34
VTT
ZQ
VTT
120Ω
/CK1
D18
D19
D20
D21
D26
D22
D23
D24
D25
Register
240Ω
VSS
SPD
All SDRAMs
All SDRAMs
All SDRAMs
All SDRAMs
Serial PD
SCL
A0
A1
A2
Address, command and control
Note :
1. DQ wiring may be changed within a nibble.
SCL
A0
A1
SDA
U1
A2 /EVENT
/EVENT
Data Sheet E1580E30 (Ver. 3.0)
9
SDA
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
Electrical Specifications
• All voltages are referenced to VSS (GND).
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Notes
Power supply voltage
VDD
−0.4 to +1.975
V
1, 3, 4
Input voltage
VIN
−0.4 to +1.975
V
1, 4
Output voltage
VOUT
−0.4 to +1.975
V
1, 4
Reference voltage
VREFCA
−0.4 to 0.6 × VDD
V
3, 4
Reference voltage for DQ
VREFDQ
−0.4 to 0.6 × VDDQ
V
3, 4
1, 2, 4
Storage temperature
Tstg
−55 to +100
°C
Power dissipation
PD
18
W
Short circuit output current
IOUT
50
mA
1, 4
Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage temperature is the case surface temperature on the center/top side of the DRAM.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than
0.6 × VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
4. DDR3 SDRAM component specification.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Operating Temperature Condition
Parameter
Symbol
Rating
Unit
Notes
Operating case temperature
TC
0 to +95
°C
1, 2, 3
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be
supported. During operation, the DRAM case temperature must be maintained between 0°C to +85°C
under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between +85°C
and +95°C case temperature. Full specifications are guaranteed in this range, but the following additional
conditions apply:
a)
Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to
3.9µs. (This double refresh requirement may not apply for some devices.)
b)
If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to
either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 bit
[A6, A7] = [0, 1]) or enable the optional Auto Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]).
Data Sheet E1580E30 (Ver. 3.0)
10
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
Recommended DC Operating Conditions (TC = 0°C to +85°C)
Parameter
Symbol
min.
typ.
max.
Unit
Notes
Supply voltage
VDD, VDDQ
1.425
1.5
1.575
V
1, 2, 3
VSS
0
0
0
V
1
VDDSPD
3.0
3.3
3.6
V
VREFCA (DC)
0.49 × VDD
—
0.51 × VDD
V
1, 4, 5
VREFDQ (DC)
0.49 × VDD
—
0.51 × VDD
V
1, 4, 5
VTT (DC)
0.49 × VDD
—
0.51 × VDD
V
Input reference voltage for
address, command inputs
Input reference voltage for
DQ, DM inputs
Termination voltage
Notes: 1.
2.
3.
4.
DDR3 SDRAM component specification.
Under all conditions VDDQ must be less than or equal to VDD.
VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ±1% VDD (for
reference: approx ±15 mV).
5. For reference: approx. VDD/2 ±15 mV.
Data Sheet E1580E30 (Ver. 3.0)
11
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.5V ± 0.075V, VSS = 0V)
Parameter
Operating current
(ACT-PRE)
Operating current
(ACT-READ-PRE)
Symbol
Data rate (Mbps) max.
Unit
IDD0
1333
1066
2140
2030
mA
IDD1
1333
1066
2400
2260
mA
1333
1066
1333
1066
1333
1066
1333
1066
1333
1066
1333
1066
1650
1610
1290
1240
1810
1670
2540
2410
1810
1670
1650
1610
IDD2P1
Precharge power-down standby current
IDD2P0
mA
Fast PD Exit
mA
Slow PD Exit
mA
Precharge standby current
IDD2N
Precharge standby
ODT current
IDD2NT
Precharge quiet standby current
IDD2Q
Active power-down current
(Always fast exit)
IDD3P
Active standby current
IDD3N
1333
1066
1960
1810
mA
IDD4R
1333
1066
3250
2820
mA
IDD4W
1333
1066
3210
3070
mA
Burst refresh current
IDD5B
1333
1066
5180
4910
mA
Self-refresh current
normal temperature range
IDD6
1340
mA
All bank interleave read current
IDD7
5500
4660
mA
RESET low current
IDD8
180
mA
Operating current
(Burst read operating)
Operating current
(Burst write operating)
1333
1066
Data Sheet E1580E30 (Ver. 3.0)
12
Notes
mA
mA
mA
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
Timings used for IDD and IDDQ Measurement-Loop Patterns
DDR3-1333
DDR3-1066
Parameter
9-9-9
7-7-7
Unit
CL
9
7
nCK
tCK min.
1.5
1.875
ns
nRCD min.
9
7
nCK
nRC min.
33
27
nCK
nRAS min.
24
20
nCK
nRP min.
9
7
nCK
nFAW
20
20
nCK
nRRD
4
4
nCK
nRFC
74
59
nCK
DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)
(DDR3 SDRAM Component Specification)
Parameter
Symbol
Value
Input leakage current
ILI
2
µA
VDD ≥ VIN ≥ VSS
Output leakage current
ILO
5
µA
DDQ ≥ VOUT ≥ VSS
Data Sheet E1580E30 (Ver. 3.0)
13
Unit
Notes
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
Pin Functions
CK, /CK (input pin)
CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK
(both directions of crossing).
/CS (input pin)
All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with
multiple ranks. /CS is considered part of the command code.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE (along with /CS) define the command being entered.
A0 to A15 (input pins)
Provided the row address for active commands and the column address for read/write commands to select one
location out of the memory array in the respective bank. (A10(AP) and A12(/BC) have additional functions, see
below) The address inputs also provide the op-code during mode register set commands.
[Address Pins Table]
Address (A0 to A13)
Row address (RA)
Column address (CA)
AX0 to AX13
AY0 to AY9, A11
Notes
A10(AP) (input pin)
A10 is sampled during read/write commands to determine whether auto-precharge should be performed to the
accessed bank after the read/write operation. (high: auto-precharge; low: no auto-precharge)
A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low)
or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by bank addresses (BA).
A12 (/BC) (input pin)
A12 is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed.
(A12 = high: no burst chop, A12 = low: burst chopped.)
BA0 to BA2 (input pins)
BA0, BA1 and BA2 define to which bank an active, read, write or precharge command is being applied. BA0 and
BA1 also determine if a mode register is to be accessed during a MRS cycle.
[Bank Select Signal Table]
BA0
BA1
BA2
Bank 0
L
L
L
Bank 1
H
L
L
Bank 2
L
H
L
Bank 3
H
H
L
Bank 4
L
L
H
Bank 5
H
L
H
Bank 6
L
H
H
Bank 7
H
H
H
Remark: H: VIH. L: VIL.
Data Sheet E1580E30 (Ver. 3.0)
14
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
CKE (input pin)
CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers.
Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down
(row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the
power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper
self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read
and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers,
excluding CKE, are disabled during self-refresh.
DQ and CB (input and output pins)
Bi-directional data bus.
DQS and /DQS (input and output pin)
Output with read data, input with write data. Edge-aligned with read data, centered in write data.
The data strobe DQS is paired with differential signals /DQS to provide differential pair signaling to the system during
READs and WRITEs.
ODT (input pins)
ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only
applied to each DQ, DQS, /DQS, DM. The ODT pin will be ignored if the mode register (MR1) is programmed to
disable ODT.
VDD (power supply pins)
1.5V is applied. (VDD is for the internal circuit.)
VDDSPD (power supply pin)
3.3V is applied (For serial EEPROM).
VSS (power supply pin)
Ground is connected.
VTT (power supply pin)
Termination supply.
VREFDQ (power supply)
Reference voltage for DQ.
VREFCA (power supply)
Reference voltage for CA.
SCL (input pin)
Clock input for serial PD.
SDA (input and output pins)
Data input/output for serial PD.
SA (input pin)
Serial address input.
/RESET (input pin)
/RESET is negative active signal (active low) and is referred to GND.
Data Sheet E1580E30 (Ver. 3.0)
15
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
Par_In (input pin)
Parity bit for the Address and Control bus.
/Err_Out (output pin)
Parity error found on the Address and Control bus.
/Event (output pin)
Temperature alert output.
Detailed Operation Part, Electrical Characteristics and Timing Waveforms
Refer to the EDJ1104BDSE, EDJ1108BDSEdatasheet (E1494E). DM pins of component device fixed to VSS level
on the module board. DIMM /CAS latency = component CL + 1 for registered type.
Data Sheet E1580E30 (Ver. 3.0)
16
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
Physical Outline
Unit: mm
Front side
8.50 max
(DATUM -A-)
4.00 min
(Front)
1
120
B
A
47.00
1.27 ± 0.10
71.00
133.35
(Back)
30.50 max
240
17.30
121
9.50
Back side
C
±
±
± ± ±
ECA-TS2-0245-02
Data Sheet E1580E30 (Ver. 3.0)
17
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E1580E30 (Ver. 3.0)
18
EBJ41HE4BDFD, EBJ41HE4BDFM, EBJ41HE4BDFP
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Be aware that this product is for use in typical electronic equipment for general-purpose applications.
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
Usage in environments with special characteristics as listed below was not considered in the design.
Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in
environments with the special characteristics listed below.
Example:
1) Usage in liquids, including water, oils, chemicals and organic solvents.
2) Usage in exposure to direct sunlight or the outdoors, or in dusty places.
3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 ,
SO 2 , and NO x .
4) Usage in environments with static electricity, or strong electromagnetic waves or radiation.
5) Usage in places where dew forms.
6) Usage in environments with mechanical vibration, impact, or stress.
7) Usage near heating elements, igniters, or flammable items.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0706
Data Sheet E1580E30 (Ver. 3.0)
19
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