WEDC EDI88130LPSXL32C 128kx8 monolithic sram, smd 5962-89598 Datasheet

White Electronic Designs
EDI88130CS
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
Access Times of 15*, 17, 20, 25, 35, 45, 55ns
Battery Back-up Operation
• 2V Data Retention (EDI88130LPS)
CS1#, CS2 & OE# Functions for Bus Control
Inputs and Outputs Directly TTL Compatible
Organized as 128Kx8
Commercial, Industrial and Military Temperature
Ranges
Thru-hole and Surface Mount Packages JEDEC
Pinout
• 32 pin Sidebrazed Ceramic DIP, 400 mil
(Package 102)
• 32 pin Sidebrazed Ceramic DIP, 600 mil
(Package 9)
• 32 lead Ceramic SOJ (Package 140)
• 32 pad Ceramic Quad LCC (Package 12)
• 32 pad Ceramic LCC (Package 141)
• 32 lead Ceramic Flatpack (Package 142)
Single +5V (±10%) Supply OperationThe
EDI88130CS is a high speed, high performance,
128Kx8 bits monolithic Static RAM.
An additional chip enable line provides system memory
security during power down in non-battery backed up
systems and memory banking in high speed battery
backed systems where large multiple pages of memory
are required.
The EDI88130CS has eight bi-directional input-output lines
to provide simultaneous access to all bits in a word.
A low power version, EDI88130LPS, offers a 2V data
retention function for battery back-up applications.
Military product is available compliant to MIL-PRF38535.
* 15ns access time is advanced information, contact factory for availability.
FIGURE 1 – PIN CONFIGURATION
32 DIP
32 SOJ
32 CLCC
32 FLATPACK
A12
A14
A16
NC
VCC
A15
CS2
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CS2#
WE#
A13
A8
A9
A11
OE#
A10
CS1#
I/O7
I/O6
I/O5
I/O4
I/O3
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
3
2
1
32
31
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14
15
16
17
18
19
WE#
A13
A8
A9
A11
OE#
A10
CS1#
I/O7
I/O0-7
A0-16
WE#
CS1#, CS2
OE#
VCC
VSS
NC
Data Input/Output
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Not Connected
Block Diagram
Memory Array
20
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
PIN DESCRIPTION
32 QUAD LCC
TOP VIEW
A0-16
Address
Buffer
Address
Decoder
I/O
Circuits
I/O0-7
WE#
CS1#
CS2
OE#
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2002
Rev. 11
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White Electronic Designs
EDI88130CS
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Industrial
Military
Storage Temperature, Ceramic
Power Dissipation
Output Current
Junction Temperature, TJ
TRUTH TABLE
-0.2 to 7.0
Unit
V
-40 to +85
-55 to +125
-65 to +150
1.7
40
175
°C
°C
°C
W
mA
°C
OE# CS1# CS2
X
H
X
X
X
L
H
L
H
L
L
H
X
L
H
Min
4.5
0
2.2
-0.5
Typ
5.0
0
—
—
Max
5.5
0
VCC +0.5
+0.8
Power
Icc2, Icc3
Icc2, Icc3
Icc1
Icc1
Icc1
TA = +25°C
Max
Parameter
Symbol
Condition
Address Lines
CI
Data Lines
CO
VIN = Vcc or Vss,
f = 1.0MHz
VOUT = Vcc or Vss,
f = 1.0MHz
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VSS
VIH
VIL
Output
High Z
High Z
High Z
Data Out
Data In
CAPACITANCE
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
WE#
Mode
X
Standby
X
Standby
H
Output Deselect
H
Read
L
Write
Unit
LCC
CSOJ,DIP,
Flatpack
6
12
pF
8
14
pF
Max
±5
±10
300
225
200
25
60
10
15
5
0.4
—
Units
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
These parameters are sampled, not 100% tested.
Unit
V
V
V
V
DC CHARACTERISTICS
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
Symbol
ILI
ILO
Conditions
VIN = 0V to VCC
VI/O = 0V to VCC
Operating Power Supply Current
Icc1
WE#, CS1# = VIL, II/O = 0mA, CS2 = VIH
Standby (TTL) Power Supply Current
Icc2
CS1# ≥ VIH and/or CS2 ≤ VIL,
VIN ≥ VIH or ≤ VIL
Full Standby Power Supply Current
Icc3
Output Low Voltage
Output High Voltage
VOL
VOH
CS1# ≥ VCC -0.2V and/or CS2 ≤ 0.2V
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
IOL = 8.0mA
IOH = -4.0mA
(15-17ns)
(20ns)
(25-55ns)
(17-55ns)
(15ns)
CS (17-55ns)
CS (15ns)
LPS
Min
—
—
—
—
—
—
—
—
—
—
—
2.4
Typ
—
—
3
—
—
—
—
AC Test Conditions
Figure 1
Vcc
Figure 2
480Ω
Q
Vcc
Input Pulse Levels
Q
255Ω
30pF
255Ω
VSS to 3.0V
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
480Ω
5ns
1.5V
Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2
5pF
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March 2002
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EDI88130CS
AC CHARACTERISTICS – READ CYCLE (15 to 20ns)
VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C
Symbol
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in Low Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Chip Enable to Power Up (1)
Chip Enable to Power Down (1)
JEDEC
tAVAV
tAVQV
tE1LQV
tE2HQV
tE1LQX
tE2HQX
tE1HQZ
tE2LQZ
tAVQX
tGLQV
tGLQX
tGHQZ
tE1LICCH
tE2HICCH
tE1HICCL
tE2LICCL
15ns*
Alt.
tRC
tAA
tACS
tACS
tCLZ
tCLZ
tCHZ
tCHZ
tOH
tOE
tOLZ
tOHZ
tPU
tPU
tPD
tPD
Min
15
17ns
Max
Min
17
15
15
15
20ns
Max
Min
20
Max
17
17
17
5
5
20
20
20
5
5
5
5
6
6
7
7
3
8
8
3
3
6
6
0
7
0
0
5
6
0
0
8
0
0
15
15
0
0
17
17
20
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
* 15ns access time is advanced information, contact factory for availability.
AC CHARACTERISTICS – READ CYCLE (25 to 55ns)
VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C
Symbol
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in Low Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Chip Enable to Power Up (1)
Chip Enable to Power Down (1)
JEDEC
tAVAV
tAVQV
tE1LQV
tE2HQV
tE1LQX
tE2HQX
tE1HQZ
tE2LQZ
tAVQX
tGLQV
tGLQX
tGHQZ
tE1LICCH
tE2HICCH
tE1HICCL
tE2LICCL
25ns
Alt.
tRC
tAA
tACS
tACS
tCLZ
tCLZ
tCHZ
tCHZ
tOH
tOE
tOLZ
tOHZ
tPU
tPU
tPD
tPD
Min
25
35ns
Max
Min
35
25
25
25
45ns
Max
Min
45
35
35
35
5
5
5
5
10
10
5
5
0
10
10
25
25
0
0
0
0
25
0
20
0
0
35
35
20
20
20
15
0
0
5
5
0
0
Max
55
55
55
20
20
15
0
Min
55
45
45
45
15
15
0
55ns
Max
20
0
0
45
45
55
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2002
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EDI88130CS
AC CHARACTERISTICS – WRITE CYCLE (15 to 20ns)
VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C
Symbol
JEDEC
Alt.
tWC
tAVAV
tE1LWH
tCW
tE1LE1H
tCW
tE2HWH
tCW
tE2HE2L
tCW
tAVWL
tAS
tAVE1L
tAS
tAVE2H
tAS
tAW
tAVWH
tWLWH
tWP
tWLE1H
tWP
tWLE2L
tWP
tWHAX
tWR
tE1HAX
tWR
tE2LAX
tWR
tWHDX
tDH
tE1HDX
tDH
tE2LDX
tDH
tWHZ
tWLQZ
tDVWH
tDW
tDVE1H
tDW
tDVE2L
tDW
tWHQX
tWLZ
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
15ns*
Min
15
12
12
12
12
0
0
0
12
12
12
12
0
0
0
0
0
0
0
7
7
7
3
17ns
Max
Min
17
13
13
13
13
0
0
0
13
13
13
13
0
0
0
0
0
0
0
8
8
8
3
7
20ns
Max
Min
20
15
15
15
15
0
0
0
15
15
15
15
0
0
0
0
0
0
0
10
10
10
3
8
Max
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE (25 to 55ns)
VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
Symbol
JEDEC
Alt.
tWC
tAVAV
tE1LWH
tCW
tE1LE1H
tCW
tE2HWH
tCW
tE2HE2L
tCW
tAVWL
tAS
tAVE1L
tAS
tAVE2H
tAS
tAVWH
tAW
tAVEH
tAW
tWLWH
tWP
tWLE1H
tWP
tWLE2L
tWP
tWR
tWHAX
tE1HAX
tWR
tE2LAX
tWR
tWHDX
tDH
tE1HDX
tDH
tE2LDX
tDH
tWLQZ
tWHZ
tDW
tDVWH
tDVE1H
tDW
tDVE2L
tDW
tWHQX
tWLZ
Min
25
20
25ns
Max
Min
35
25
16
16
10
Min
45
35
20
20
16
0
0
0
20
20
20
20
20
0
0
0
0
0
0
0
15
15
15
3
35ns
Max
13
Min
55
45
25
25
20
0
0
0
25
25
30
30
30
0
0
0
0
0
0
0
20
20
20
3
45ns
Max
40
40
25
0
0
0
35
35
30
30
30
5
5
5
0
0
0
0
20
20
20
3
55ns
Max
15
40
0
0
0
45
45
35
35
35
5
5
5
0
0
0
0
25
25
25
3
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2002
Rev. 11
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EDI88130CS
FIGURE 2 – TIMING WAVEFORM - READ CYCLES
tAVAV
ADDRESS
tAVQV
CS1#
tAVAV
tE1LQV
tE1LQX
tE1LICCH
tE1HQZ
tE1HICCL
tE2HQV
tE2LICCL
Icc
ADDRESS
ADDRESS 1
ADDRESS 2
CS2
tE2HICCH
tE2HQX
tAVQX
tAVQV
DATA I/O
DATA 1
OE#
DATA 2
tGLQV
tGLQX
tGHQZ
DATA I/O
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
READ CYCLE 2 (CS1# AND/OR CS2 CONTROLLED, WE# HIGH)
FIGURE 3 – WRITE CYCLE 1
tAVAV
ADDRESS
tAVWL
tAVWH
tWLWH
tWHAX
WE#
tE1LWH
CS1#
CS2
tE2HWH
tDVWH
tWHDX
DATA IN
tWLQZ
tWHQX
DATA OUT
WRITE CYCLE 1 - LATE WRITE, WE# CONTROLLED
WRITE CYCLES 3
FIGURE 4 – WRITE CYCLES 2
tAVAV
tAVAV
ADDRESS
ADDRESS
tAVE1L
tE1LE1H
tAVE2H
tE1HAX
WE#
WE#
CS1#
CS1#
CS2
tE2HE2L
tE2LAX
CS2
tDVE1H
tE1HDX
tDVE2L
DATA I/O
tE2LDX
DATA I/O
WRITE CYCLE 2 - EARLY WRITE, CS1# CONTROLLED
WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2002
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EDI88130CS
DATA RETENTION CHARACTERISTICS (EDI88130LPS Only)
-55°C ≤ TA ≤ +125°C
Characteristic
Low Power Version only
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time (1)
Operation Recovery Time (1)
Sym
Conditions
Min
Typ
Max
Units
VCC
ICCDR
TCDR
TR
VCC = 2.0V
CS1# ≥ VCC -0.2V and/or CS2 ≥ VSS +0.2V
VIN ≥ VCC -0.2V
or VIN ≤ 0.2V
2
–
0
Tavav*
–
0.5
–
–
–
2
–
–
V
mA
ns
ns
NOTE:
1. Parameter guaranteed by design, but not tested.
* Read Cycle Time
FIGURE 5 – DATA RETENTION - CS1# CONTROLLED
Data Retention Mode
Vcc
4.5V
VCC
4.5V
tCDR
tR
CS1#
CS1# ≥ VCC -0.2V
DATA RETENTION, CS1# CONTROLLED
FIGURE 6 – DATA RETENTION - CS2 CONTROLLED
Data Retention Mode
Vcc
4.5V
VCC
4.5V
tCDR
CS2
tR
CS2
0.2V
DATA RETENTION, CS2 CONTROLLED
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March 2002
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White Electronic Designs
EDI88130CS
PACKAGE 12: 32 PIN CERAMIC QUAD LCC
0.120
0.060
0.028
0.022
0.020 X 45°
REF.
0.050
BSC.
0.560
0.540
0.055
0.045
0.458
0.442
0.040 X 45°
REF.
ALL DIMENSIONS ARE IN INCHES
PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600 MILS WIDE)
1.616
1.584
0.620
0.600
0.060
0.040
Pin 1 Indicator
0.200
0.125
0.061
0.017
0.155
0.115
0.100
TYP
0.020
0.016
0.600
NOM
15 x 0.100 = 1.500
ALL DIMENSIONS ARE IN INCHES
PACKAGE 102: 32 PIN SIDEBRAZED CERAMIC DIP (400 MILS WIDE)
1.616
1.584
0.420
0.400
0.060
0.040
Pin 1 Indicator
0.200
0.125
0.061
0.017
0.100
TYP
0.020
0.016
0.155
0.115
0.400
NOM
15 x 0.100 = 1.500
ALL DIMENSIONS ARE IN INCHES
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March 2002
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EDI88130CS
PACKAGE 140: 32 LEAD CERAMIC SOJ
0.108
0.088
0.840
0.820
0.040
0.030
0.440
0.430
0.379
REF
0.155
0.120
0.050
TYP
ALL DIMENSIONS ARE IN INCHES
PACKAGE 141: 32 PAD CERAMIC LCC
0.096
0.080
0.028
0.022
0.840
0.820
0.050
TYP
0.405
0.395
ALL DIMENSIONS ARE IN INCHES
PACKAGE 142: 32 PIN CERAMIC FLATPACK
0.830
0.810
0.007
0.003
1.00 REF
0.290
0.270
0.420
0.400
0.040
0.030
Pin 1
0.045
0.020
0.370
0.250
0.019
0.015
0.116
0.100
0.050
TYP
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2002
Rev. 11
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White Electronic Designs
EDI88130CS
ORDERING INFORMATION
EDI 8 8 130 CS X X X
WHITE ELECTRONIC DESIGNS
SRAM
ORGANIZATION, 128Kx8
(130 = Dual CS)
TECHNOLOGY:
CS = CMOS Standard Power (5V)
LPS = Low Power
ACCESS TIME (ns)
PACKAGE TYPE:
C = 32 lead Sidebrazed DIP, 600 mil (Package 9)
F = 32 lead Ceramic Flatpack (Package 142)
L = 32 pad Ceramic LCC (Package 141)
L32 = 32 pad Ceramic Quad LCC (Package 12)
N = 32 lead Ceramic SOJ (Package 140)
T = 32 lead Sidebrazed DIP, 400 mil (Package 102)
DEVICE GRADE:
B = MIL-STD-883 Compliant
M = Military Screened
I = Industrial
C = Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2002
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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