WEDC EDI88130LPXNI 128kx8 monolithic sram, smd 5962-89598 Datasheet

White Electronic Designs
EDI88128C
128Kx8 MONOLITHIC SRAM, SMD 5962-89598
The EDI88128C is a high speed, high performance,
Monolithic CMOS Static RAM organized as 128Kx8.
FEATURES
Access Times of 70, 85, 100ns
Available with Single Chip Selects (EDI88128) or
Dual Chip Selects (EDI88130)
2V Data Retention (LP Versions)
CS# and OE# Functions for Bus Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Organized as 128Kx8
Industrial, Military and Commercial Temperature
Ranges
Thru-hole and Surface Mount Packages JEDEC
Pinout
The device is also available as EDI88130C with an
additional chip select line (CS2) which will automatically
power down the device when proper logic levels are
applied.
The second chip select line (CS2) can be used to provide
system memory security during power down in non-battery
backed up systems and simplifiy decoding schemes in
memory banking where large multiple pages of memory
are required.
The EDI88128C and the EDI88130C have eight bidirectional input-output lines to provide simultaneous
access to all bits in a word. An automatic power down
feature permits the on-chip circuitry to enter a very low
standby mode and be brought back into operation at a
speed equal to the address access time.
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)
• 32 lead Ceramic SOJ (Package 140)
Low power versions, EDI88128LP and EDI88130LP, offer
a 2V data retention function for battery back-up opperation.
Military product is available compliant to Appendix A of
MIL-PRF-38535.
Single +5V (±10%) Supply Operation
FIGURE 1 – PIN CONFIGURATION
PIN DESCRIPTION
I/O0-7
A0-16
WE#
CS1#, CS2
OE#
VCC
VSS
NC
32 DIP
32 SOJ
Top View
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
AØ
I/OØ
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 NC/CS2*
29 WE#
28 A13
27 A8
26 A9
25 A11
24 OE#
23 A10
22 CS1#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
Not Connected
BLOCK DIAGRAM
WE#
CS1#
CS2
OE#
* Pin 30 is NC for 88128 or CS2 for 88130.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 17
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EDI88128C
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Parameter
Voltage on any pin relative to VSS
-0.5 to 7.0
Unit
V
Operating Temperature TA (Ambient)
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, TJ
0 to +70
-40 to +85
-55 to +125
-65 to +150
1
20
175
°C
°C
°C
°C
W
mA
°C
OE# CS1# CS2# WE#
Mode
X
H
X
X
Standby
X
X
L
X
Standby
X
X
L
X
Output Deselect
H
L
H
H
Output Deselect
L
L
H
H
Read
X
L
H
L
Write
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Output
High Z
High Z
High Z
High Z
Data Out
Data In
Power
Icc2, Icc3
Icc2, Icc3
Icc1
Icc1
Icc1
Icc1
Recommended Operating Conditions
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
VCC
VSS
VIH
VIL
Min
4.5
0
2.2
-0.3
Typ
5.0
0
—
—
Max
5.5
0
VCC +0.5
+0.8
Unit
V
V
V
V
CAPACITANCE
TA = +25°C
Symbol
Parameter
Address Lines
CI
Input/Output Lines
CO
Condition
VIN = VCC or VSS, f = 1.0MHz
VOUT = VCC or VSS, f = 1.0MHz
Max Unit
12 pF
14 pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
VCC = 5V, -55°C ≤ TA ≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
Symbol Conditions
VIN = 0V to VCC
ILI
ILO
VI/O = 0V to VCC, CS1# ≥ VIH and/or CS2# ≤ VIL
WE#, CS1# = VIL, II/O = 0mA, Min Cycle
(70-85ns)
ICC1
CS2# = VIH
(100ns)
ICC2
CS1# ≥ VIH and/or CS2# ≤ VIL, VIN ≥ VIH or ≤ VIL
CS1# ≥ VCC -0.2V and/or CS2# ≤ VCC+0.2V
C
ICC3
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
LP
VOL
IOL = 2.1mA
VOH
IOH = -1.0mA
Min
-5
-10
—
—
—
—
—
—
2.4
Typ
—
—
1
—
—
—
Max
+5
+10
120
110
10
5
1
0.4
—
Units
µA
µA
mA
mA
mA
mA
mA
V
V
NOTE: DC test conditions : VIL = 0.3V, VIH = VCC -0.3V
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 17
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EDI88128C
AC Characteristics – Read Cycle
VCC = 5V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Symbol
Parameter
JEDEC
tAVAV
tAVQV
tELQV
tSHQV
tELQX
tSHQX
tEHQZ
tSLQZ
tAVQX
tGLQV
tGLQX
tGHQZ
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z (1)
70ns
Alt.
tRC
tAA
tACS
tACS
tCLZ
tCLZ
tCHZ
tCHZ
tOH
tOE
tOLZ
tOHZ
Min
70
85ns
Max
Min
85
70
70
70
Min
100
85
85
85
3
3
3
3
30
30
3
3
3
25
30
30
3
30
0
0
30
Max
100
100
100
30
30
3
0
0
100ns
Max
30
50
0
0
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
AC Test Conditions
Figure 1
Figure 2
Vcc
480Ω
Q
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Vcc
480Ω
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2
Q
255Ω
30pF
VSS to 3.0V
5ns
1.5V
Figure 1
255Ω
5pF
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April 2005
Rev. 17
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EDI88128C
AC CHARACTERISTICS – WRITE CYCLE
VCC = 5V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
70ns
85ns
Max
Min
100ns
Max
Min
Max
Units
JEDEC
Alt.
Min
Write Cycle Time
tAVAV
tWC
70
85
100
ns
Chip Select to End of Write
tELWH
tELEH
tSHWH
tSHSL
tCW
tCW
tCW
tCW
60
60
60
60
75
75
75
75
85
85
85
85
ns
ns
ns
ns
Address Setup Time
tAVWL
tAVEL
tAVSH
tAS
tAS
tAS
0
0
0
0
0
0
0
0
0
ns
ns
ns
Address Valid to End of Write
tAVWH
tAW
60
75
85
ns
Write Pulse Width
tWLWH
tWLEH
tWLSL
tWP
tWP
tWP
35
35
35
70
70
70
80
80
80
ns
ns
ns
Write Recovery Time
tWHAX
tEHAX
tSLAX
tWR
tWR
tWR
5
5
5
5
5
5
5
5
5
ns
ns
ns
Data Hold Time
tWHDX
tEHDX
tSLDX
tDH
tDH
tDH
0
0
0
0
0
0
0
0
0
ns
ns
ns
Write to Output in High Z (1)
tWLQZ
tWHZ
0
Data to Write Time
tDVWH
tDVEH
tDVSL
tDW
tDW
tDW
35
35
35
40
40
40
40
40
40
ns
ns
ns
Output Active from End of Write (1)
tWHQX
tWLZ
5
5
5
ns
30
0
35
0
40
ns
1. This parameter is guaranteed by design but not tested.
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April 2005
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EDI88128C
FIGURE 2 – TIMING WAVEFORM — READ CYCLE
tAVAV
ADDRESS
tAVQV
CS1#
tAVAV
ADDRESS
ADDRESS 1
ADDRESS 2
tAVQV
tAVQX
DATA I/O
tELQV
tELQX
tEHQZ
tSHQV
tSHQX
tSLQZ
CS2
OE#
DATA 1
tGLQV
tGLQX
DATA 2
tGHQZ
DATA I/O
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
READ CYCLE 2 (WE# HIGH)
FIGURE 3 – WRITE CYCLE 1
tAVAV
ADDRESS
tAVWL
tAVWH
tWLWH
tWHAX
WE#
CS1#
tELWH
CS2
tSHWH
DATA IN
tWHQX
tWHDX
tDVWH
DATA VALID
tWLQZ
HIGH Z
DATA OUT
WRITE CYCLE 1 - LATE WRITE, WE# CONTROLLED
FIGURE 4 – WRITE CYCLE 2
WRITE CYCLE 3
tAVAV
tAVAV
ADDRESS
ADDRESS
tAVEL
tEHAX
tWLEH
tAVSH
WE#
WE#
tELEH
tSHSL
CS1#
CS1#
CS2
CS2
tDVEH
DATA IN
tSLAX
tWLSL
tEHDX
tDVSL
DATA VALID
DATA IN
tSLDX
DATA VALID
WRITE CYCLE 2 - EARLY WRITE, CS1# CONTROLLED
WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 17
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EDI88128C
DATA RETENTION CHARACTERISTICS (EDI88128LP & EDI88130LP ONLY)
-55°C ≤ TA ≤ +125°C
Characteristic
Low Power Version only
Symbol
Conditions
Min
Typ
Max
Units
Data Retention Voltage
VDD
VDD = 2.0V
2
–
–
V
Data Retention Quiescent Current
ICCDR
CS1# ≥ VDD -0.2V
–
–
400
µA
Chip Disable to Data Retention Time (1)
TCDR
VIN ≥ VDD -0.2V
0
–
–
ns
TR
or VIN ≤ 0.2V
TAVAV*
–
–
ns
Operation Recovery Time (1)
NOTE:
1. Parameter guaranteed by design, but not tested.
* Read Cycle Time
FIGURE 5 – DATA RETENTION – CS1# CONTROLLED
Data Retention Mode
4.5V
Vcc
VDD
4.5V
tCDR
tR
CS1#
CS1# VDD -0.2V
DATA RETENTION, CS1# CONTROLLED
FIGURE 6 – DATA RETENTION — CS2 CONTROLLED
Data Retention Mode
4.5V
Vcc
VDD
4.5V
tCDR
CS2
tR
CS2 ≤ 0.2V
DATA RETENTION, CS2 CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 17
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EDI88128C
PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600MILS WIDE)
1.616
1.584
Pin 1 Indicator
0.200
0.125
0.061
0.017
0.020
0.016
0.060
0.040
0.620
0.600
0.155
0.100 0.115
TYP
0.600
NOM
15 x 0.100 = 1.500
ALL DIMENSIONS ARE IN INCHES
PACKAGE 140: 32 LEAD CERAMIC SOJ
0.010
0.006
0.019
0.015
0.840
0.820
0.444
0.430
0.379
0.050
TYP
0.155
0.106
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
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EDI88128C
ORDERING INFORMATION
EDI 8 8 128 C X X X
WHITE ELECTRONIC DESIGNS
SRAM
ORGANIZATION, 128Kx8
8 130 = Dual Chip Select
TECHNOLOGY:
C = CMOS Standard Power
LP = Low Power
ACCESS TIME (ns)
PACKAGE TYPE:
C = 32 lead Sidebrazed DIP, 600 mil (Package 9)
N = 32 lead Ceramic SOJ (Package 140)
DEVICE GRADE:
B = MIL-STD-883 Compliant
M = Military Screened
-55°C to +125°C
I = Industrial
-40°C to +85°C
C = Commercial
0°C to +70°C
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 17
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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